Merge branch 'i2c/for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux
Pull more i2c updates from Wolfram Sang: "I2C has two more new drivers: Altera FPGA and STM32F7" * 'i2c/for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux: i2c: i2c-stm32f7: add driver i2c: i2c-stm32f4: use generic definition of speed enum dt-bindings: i2c-stm32: Document the STM32F7 I2C bindings i2c: altera: Add Altera I2C Controller driver dt-bindings: i2c: Add Altera I2C Controller
This commit is contained in:
Linus Torvalds
commit
bbe05e543b
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@ -0,0 +1,39 @@
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* Altera I2C Controller
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* This is Altera's synthesizable logic block I2C Controller for use
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* in Altera's FPGAs.
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Required properties :
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- compatible : should be "altr,softip-i2c-v1.0"
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- reg : Offset and length of the register set for the device
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- interrupts : <IRQ> where IRQ is the interrupt number.
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- clocks : phandle to input clock.
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- #address-cells = <1>;
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- #size-cells = <0>;
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Recommended properties :
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- clock-frequency : desired I2C bus clock frequency in Hz.
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Optional properties :
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- fifo-size : Size of the RX and TX FIFOs in bytes.
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- Child nodes conforming to i2c bus binding
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Example :
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i2c@100080000 {
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compatible = "altr,softip-i2c-v1.0";
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reg = <0x00000001 0x00080000 0x00000040>;
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interrupt-parent = <&intc>;
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interrupts = <0 43 4>;
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clocks = <&clk_0>;
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clock-frequency = <100000>;
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#address-cells = <1>;
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#size-cells = <0>;
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fifo-size = <4>;
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eeprom@51 {
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compatible = "atmel,24c32";
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reg = <0x51>;
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pagesize = <32>;
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};
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};
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@ -1,7 +1,9 @@
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* I2C controller embedded in STMicroelectronics STM32 I2C platform
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Required properties :
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- compatible : Must be "st,stm32f4-i2c"
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- compatible : Must be one of the following
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- "st,stm32f4-i2c"
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- "st,stm32f7-i2c"
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- reg : Offset and length of the register set for the device
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- interrupts : Must contain the interrupt id for I2C event and then the
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interrupt id for I2C error.
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@ -14,8 +16,16 @@ Required properties :
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Optional properties :
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- clock-frequency : Desired I2C bus clock frequency in Hz. If not specified,
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the default 100 kHz frequency will be used. As only Normal and Fast modes
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are supported, possible values are 100000 and 400000.
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the default 100 kHz frequency will be used.
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For STM32F4 SoC Standard-mode and Fast-mode are supported, possible values are
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100000 and 400000.
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For STM32F7 SoC, Standard-mode, Fast-mode and Fast-mode Plus are supported,
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possible values are 100000, 400000 and 1000000.
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- i2c-scl-rising-time-ns : Only for STM32F7, I2C SCL Rising time for the board
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(default: 25)
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- i2c-scl-falling-time-ns : Only for STM32F7, I2C SCL Falling time for the board
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(default: 10)
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I2C Timings are derived from these 2 values
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Example :
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@ -31,3 +41,16 @@ Example :
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pinctrl-0 = <&i2c1_sda_pin>, <&i2c1_scl_pin>;
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pinctrl-names = "default";
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};
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i2c@40005400 {
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compatible = "st,stm32f7-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40005400 0x400>;
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interrupts = <31>,
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<32>;
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resets = <&rcc STM32F7_APB1_RESET(I2C1)>;
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clocks = <&rcc 1 CLK_I2C1>;
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pinctrl-0 = <&i2c1_sda_pin>, <&i2c1_scl_pin>;
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pinctrl-names = "default";
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};
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@ -644,6 +644,11 @@ ALPS PS/2 TOUCHPAD DRIVER
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R: Pali Rohár <pali.rohar@gmail.com>
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F: drivers/input/mouse/alps.*
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ALTERA I2C CONTROLLER DRIVER
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M: Thor Thayer <thor.thayer@linux.intel.com>
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S: Maintained
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F: drivers/i2c/busses/i2c-altera.c
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ALTERA MAILBOX DRIVER
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M: Ley Foon Tan <lftan@altera.com>
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L: nios2-dev@lists.rocketboards.org (moderated for non-subscribers)
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@ -336,6 +336,16 @@ config I2C_POWERMAC
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comment "I2C system bus drivers (mostly embedded / system-on-chip)"
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config I2C_ALTERA
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tristate "Altera Soft IP I2C"
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depends on (ARCH_SOCFPGA || NIOS2) && OF
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help
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If you say yes to this option, support will be included for the
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Altera Soft IP I2C interfaces on SoCFPGA and Nios2 architectures.
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This driver can also be built as a module. If so, the module
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will be called i2c-altera.
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config I2C_ASPEED
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tristate "Aspeed I2C Controller"
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depends on ARCH_ASPEED || COMPILE_TEST
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@ -935,6 +945,16 @@ config I2C_STM32F4
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This driver can also be built as module. If so, the module
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will be called i2c-stm32f4.
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config I2C_STM32F7
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tristate "STMicroelectronics STM32F7 I2C support"
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depends on ARCH_STM32 || COMPILE_TEST
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help
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Enable this option to add support for STM32 I2C controller embedded
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in STM32F7 SoCs.
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This driver can also be built as module. If so, the module
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will be called i2c-stm32f7.
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config I2C_STU300
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tristate "ST Microelectronics DDC I2C interface"
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depends on MACH_U300
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@ -30,6 +30,7 @@ obj-$(CONFIG_I2C_HYDRA) += i2c-hydra.o
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obj-$(CONFIG_I2C_POWERMAC) += i2c-powermac.o
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# Embedded system I2C/SMBus host controller drivers
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obj-$(CONFIG_I2C_ALTERA) += i2c-altera.o
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obj-$(CONFIG_I2C_ASPEED) += i2c-aspeed.o
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obj-$(CONFIG_I2C_AT91) += i2c-at91.o
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obj-$(CONFIG_I2C_AU1550) += i2c-au1550.o
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@ -93,6 +94,7 @@ obj-$(CONFIG_I2C_SIRF) += i2c-sirf.o
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obj-$(CONFIG_I2C_SPRD) += i2c-sprd.o
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obj-$(CONFIG_I2C_ST) += i2c-st.o
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obj-$(CONFIG_I2C_STM32F4) += i2c-stm32f4.o
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obj-$(CONFIG_I2C_STM32F7) += i2c-stm32f7.o
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obj-$(CONFIG_I2C_STU300) += i2c-stu300.o
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obj-$(CONFIG_I2C_SUN6I_P2WI) += i2c-sun6i-p2wi.o
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obj-$(CONFIG_I2C_TEGRA) += i2c-tegra.o
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@ -0,0 +1,511 @@
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/*
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* Copyright Intel Corporation (C) 2017.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
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*
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||||
* You should have received a copy of the GNU General Public License along with
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||||
* this program. If not, see <http://www.gnu.org/licenses/>.
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*
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* Based on the i2c-axxia.c driver.
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*/
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include <linux/err.h>
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#include <linux/i2c.h>
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#include <linux/iopoll.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/platform_device.h>
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#define ALTR_I2C_TFR_CMD 0x00 /* Transfer Command register */
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#define ALTR_I2C_TFR_CMD_STA BIT(9) /* send START before byte */
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#define ALTR_I2C_TFR_CMD_STO BIT(8) /* send STOP after byte */
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#define ALTR_I2C_TFR_CMD_RW_D BIT(0) /* Direction of transfer */
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#define ALTR_I2C_RX_DATA 0x04 /* RX data FIFO register */
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#define ALTR_I2C_CTRL 0x08 /* Control register */
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#define ALTR_I2C_CTRL_RXT_SHFT 4 /* RX FIFO Threshold */
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#define ALTR_I2C_CTRL_TCT_SHFT 2 /* TFER CMD FIFO Threshold */
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#define ALTR_I2C_CTRL_BSPEED BIT(1) /* Bus Speed (1=Fast) */
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#define ALTR_I2C_CTRL_EN BIT(0) /* Enable Core (1=Enable) */
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#define ALTR_I2C_ISER 0x0C /* Interrupt Status Enable register */
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#define ALTR_I2C_ISER_RXOF_EN BIT(4) /* Enable RX OVERFLOW IRQ */
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#define ALTR_I2C_ISER_ARB_EN BIT(3) /* Enable ARB LOST IRQ */
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#define ALTR_I2C_ISER_NACK_EN BIT(2) /* Enable NACK DET IRQ */
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#define ALTR_I2C_ISER_RXRDY_EN BIT(1) /* Enable RX Ready IRQ */
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#define ALTR_I2C_ISER_TXRDY_EN BIT(0) /* Enable TX Ready IRQ */
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#define ALTR_I2C_ISR 0x10 /* Interrupt Status register */
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#define ALTR_I2C_ISR_RXOF BIT(4) /* RX OVERFLOW IRQ */
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#define ALTR_I2C_ISR_ARB BIT(3) /* ARB LOST IRQ */
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#define ALTR_I2C_ISR_NACK BIT(2) /* NACK DET IRQ */
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#define ALTR_I2C_ISR_RXRDY BIT(1) /* RX Ready IRQ */
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#define ALTR_I2C_ISR_TXRDY BIT(0) /* TX Ready IRQ */
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#define ALTR_I2C_STATUS 0x14 /* Status register */
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#define ALTR_I2C_STAT_CORE BIT(0) /* Core Status (0=idle) */
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#define ALTR_I2C_TC_FIFO_LVL 0x18 /* Transfer FIFO LVL register */
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#define ALTR_I2C_RX_FIFO_LVL 0x1C /* Receive FIFO LVL register */
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#define ALTR_I2C_SCL_LOW 0x20 /* SCL low count register */
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#define ALTR_I2C_SCL_HIGH 0x24 /* SCL high count register */
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#define ALTR_I2C_SDA_HOLD 0x28 /* SDA hold count register */
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#define ALTR_I2C_ALL_IRQ (ALTR_I2C_ISR_RXOF | ALTR_I2C_ISR_ARB | \
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ALTR_I2C_ISR_NACK | ALTR_I2C_ISR_RXRDY | \
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ALTR_I2C_ISR_TXRDY)
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#define ALTR_I2C_THRESHOLD 0 /* IRQ Threshold at 1 element */
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#define ALTR_I2C_DFLT_FIFO_SZ 4
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#define ALTR_I2C_TIMEOUT 100000 /* 100ms */
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#define ALTR_I2C_XFER_TIMEOUT (msecs_to_jiffies(250))
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/**
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* altr_i2c_dev - I2C device context
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* @base: pointer to register struct
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* @msg: pointer to current message
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* @msg_len: number of bytes transferred in msg
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* @msg_err: error code for completed message
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* @msg_complete: xfer completion object
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* @dev: device reference
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* @adapter: core i2c abstraction
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* @i2c_clk: clock reference for i2c input clock
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* @bus_clk_rate: current i2c bus clock rate
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* @buf: ptr to msg buffer for easier use.
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* @fifo_size: size of the FIFO passed in.
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* @isr_mask: cached copy of local ISR enables.
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* @isr_status: cached copy of local ISR status.
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* @lock: spinlock for IRQ synchronization.
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*/
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struct altr_i2c_dev {
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void __iomem *base;
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struct i2c_msg *msg;
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size_t msg_len;
|
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int msg_err;
|
||||
struct completion msg_complete;
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struct device *dev;
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struct i2c_adapter adapter;
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struct clk *i2c_clk;
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u32 bus_clk_rate;
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u8 *buf;
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u32 fifo_size;
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u32 isr_mask;
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u32 isr_status;
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spinlock_t lock; /* IRQ synchronization */
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};
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static void
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altr_i2c_int_enable(struct altr_i2c_dev *idev, u32 mask, bool enable)
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{
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unsigned long flags;
|
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u32 int_en;
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||||
|
||||
spin_lock_irqsave(&idev->lock, flags);
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|
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int_en = readl(idev->base + ALTR_I2C_ISER);
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if (enable)
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idev->isr_mask = int_en | mask;
|
||||
else
|
||||
idev->isr_mask = int_en & ~mask;
|
||||
|
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writel(idev->isr_mask, idev->base + ALTR_I2C_ISER);
|
||||
|
||||
spin_unlock_irqrestore(&idev->lock, flags);
|
||||
}
|
||||
|
||||
static void altr_i2c_int_clear(struct altr_i2c_dev *idev, u32 mask)
|
||||
{
|
||||
u32 int_en = readl(idev->base + ALTR_I2C_ISR);
|
||||
|
||||
writel(int_en | mask, idev->base + ALTR_I2C_ISR);
|
||||
}
|
||||
|
||||
static void altr_i2c_core_disable(struct altr_i2c_dev *idev)
|
||||
{
|
||||
u32 tmp = readl(idev->base + ALTR_I2C_CTRL);
|
||||
|
||||
writel(tmp & ~ALTR_I2C_CTRL_EN, idev->base + ALTR_I2C_CTRL);
|
||||
}
|
||||
|
||||
static void altr_i2c_core_enable(struct altr_i2c_dev *idev)
|
||||
{
|
||||
u32 tmp = readl(idev->base + ALTR_I2C_CTRL);
|
||||
|
||||
writel(tmp | ALTR_I2C_CTRL_EN, idev->base + ALTR_I2C_CTRL);
|
||||
}
|
||||
|
||||
static void altr_i2c_reset(struct altr_i2c_dev *idev)
|
||||
{
|
||||
altr_i2c_core_disable(idev);
|
||||
altr_i2c_core_enable(idev);
|
||||
}
|
||||
|
||||
static inline void altr_i2c_stop(struct altr_i2c_dev *idev)
|
||||
{
|
||||
writel(ALTR_I2C_TFR_CMD_STO, idev->base + ALTR_I2C_TFR_CMD);
|
||||
}
|
||||
|
||||
static void altr_i2c_init(struct altr_i2c_dev *idev)
|
||||
{
|
||||
u32 divisor = clk_get_rate(idev->i2c_clk) / idev->bus_clk_rate;
|
||||
u32 clk_mhz = clk_get_rate(idev->i2c_clk) / 1000000;
|
||||
u32 tmp = (ALTR_I2C_THRESHOLD << ALTR_I2C_CTRL_RXT_SHFT) |
|
||||
(ALTR_I2C_THRESHOLD << ALTR_I2C_CTRL_TCT_SHFT);
|
||||
u32 t_high, t_low;
|
||||
|
||||
if (idev->bus_clk_rate <= 100000) {
|
||||
tmp &= ~ALTR_I2C_CTRL_BSPEED;
|
||||
/* Standard mode SCL 50/50 */
|
||||
t_high = divisor * 1 / 2;
|
||||
t_low = divisor * 1 / 2;
|
||||
} else {
|
||||
tmp |= ALTR_I2C_CTRL_BSPEED;
|
||||
/* Fast mode SCL 33/66 */
|
||||
t_high = divisor * 1 / 3;
|
||||
t_low = divisor * 2 / 3;
|
||||
}
|
||||
writel(tmp, idev->base + ALTR_I2C_CTRL);
|
||||
|
||||
dev_dbg(idev->dev, "rate=%uHz per_clk=%uMHz -> ratio=1:%u\n",
|
||||
idev->bus_clk_rate, clk_mhz, divisor);
|
||||
|
||||
/* Reset controller */
|
||||
altr_i2c_reset(idev);
|
||||
|
||||
/* SCL High Time */
|
||||
writel(t_high, idev->base + ALTR_I2C_SCL_HIGH);
|
||||
/* SCL Low Time */
|
||||
writel(t_low, idev->base + ALTR_I2C_SCL_LOW);
|
||||
/* SDA Hold Time, 300ns */
|
||||
writel(div_u64(300 * clk_mhz, 1000), idev->base + ALTR_I2C_SDA_HOLD);
|
||||
|
||||
/* Mask all master interrupt bits */
|
||||
altr_i2c_int_enable(idev, ALTR_I2C_ALL_IRQ, false);
|
||||
}
|
||||
|
||||
/**
|
||||
* altr_i2c_transfer - On the last byte to be transmitted, send
|
||||
* a Stop bit on the last byte.
|
||||
*/
|
||||
static void altr_i2c_transfer(struct altr_i2c_dev *idev, u32 data)
|
||||
{
|
||||
/* On the last byte to be transmitted, send STOP */
|
||||
if (idev->msg_len == 1)
|
||||
data |= ALTR_I2C_TFR_CMD_STO;
|
||||
if (idev->msg_len > 0)
|
||||
writel(data, idev->base + ALTR_I2C_TFR_CMD);
|
||||
}
|
||||
|
||||
/**
|
||||
* altr_i2c_empty_rx_fifo - Fetch data from RX FIFO until end of
|
||||
* transfer. Send a Stop bit on the last byte.
|
||||
*/
|
||||
static void altr_i2c_empty_rx_fifo(struct altr_i2c_dev *idev)
|
||||
{
|
||||
size_t rx_fifo_avail = readl(idev->base + ALTR_I2C_RX_FIFO_LVL);
|
||||
int bytes_to_transfer = min(rx_fifo_avail, idev->msg_len);
|
||||
|
||||
while (bytes_to_transfer-- > 0) {
|
||||
*idev->buf++ = readl(idev->base + ALTR_I2C_RX_DATA);
|
||||
idev->msg_len--;
|
||||
altr_i2c_transfer(idev, 0);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* altr_i2c_fill_tx_fifo - Fill TX FIFO from current message buffer.
|
||||
* @return: Number of bytes left to transfer.
|
||||
*/
|
||||
static int altr_i2c_fill_tx_fifo(struct altr_i2c_dev *idev)
|
||||
{
|
||||
size_t tx_fifo_avail = idev->fifo_size - readl(idev->base +
|
||||
ALTR_I2C_TC_FIFO_LVL);
|
||||
int bytes_to_transfer = min(tx_fifo_avail, idev->msg_len);
|
||||
int ret = idev->msg_len - bytes_to_transfer;
|
||||
|
||||
while (bytes_to_transfer-- > 0) {
|
||||
altr_i2c_transfer(idev, *idev->buf++);
|
||||
idev->msg_len--;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static irqreturn_t altr_i2c_isr_quick(int irq, void *_dev)
|
||||
{
|
||||
struct altr_i2c_dev *idev = _dev;
|
||||
irqreturn_t ret = IRQ_HANDLED;
|
||||
|
||||
/* Read IRQ status but only interested in Enabled IRQs. */
|
||||
idev->isr_status = readl(idev->base + ALTR_I2C_ISR) & idev->isr_mask;
|
||||
if (idev->isr_status)
|
||||
ret = IRQ_WAKE_THREAD;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static irqreturn_t altr_i2c_isr(int irq, void *_dev)
|
||||
{
|
||||
int ret;
|
||||
bool read, finish = false;
|
||||
struct altr_i2c_dev *idev = _dev;
|
||||
u32 status = idev->isr_status;
|
||||
|
||||
if (!idev->msg) {
|
||||
dev_warn(idev->dev, "unexpected interrupt\n");
|
||||
altr_i2c_int_clear(idev, ALTR_I2C_ALL_IRQ);
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
read = (idev->msg->flags & I2C_M_RD) != 0;
|
||||
|
||||
/* handle Lost Arbitration */
|
||||
if (unlikely(status & ALTR_I2C_ISR_ARB)) {
|
||||
altr_i2c_int_clear(idev, ALTR_I2C_ISR_ARB);
|
||||
idev->msg_err = -EAGAIN;
|
||||
finish = true;
|
||||
} else if (unlikely(status & ALTR_I2C_ISR_NACK)) {
|
||||
dev_dbg(idev->dev, "Could not get ACK\n");
|
||||
idev->msg_err = -ENXIO;
|
||||
altr_i2c_int_clear(idev, ALTR_I2C_ISR_NACK);
|
||||
altr_i2c_stop(idev);
|
||||
finish = true;
|
||||
} else if (read && unlikely(status & ALTR_I2C_ISR_RXOF)) {
|
||||
/* handle RX FIFO Overflow */
|
||||
altr_i2c_empty_rx_fifo(idev);
|
||||
altr_i2c_int_clear(idev, ALTR_I2C_ISR_RXRDY);
|
||||
altr_i2c_stop(idev);
|
||||
dev_err(idev->dev, "RX FIFO Overflow\n");
|
||||
finish = true;
|
||||
} else if (read && (status & ALTR_I2C_ISR_RXRDY)) {
|
||||
/* RX FIFO needs service? */
|
||||
altr_i2c_empty_rx_fifo(idev);
|
||||
altr_i2c_int_clear(idev, ALTR_I2C_ISR_RXRDY);
|
||||
if (!idev->msg_len)
|
||||
finish = true;
|
||||
} else if (!read && (status & ALTR_I2C_ISR_TXRDY)) {
|
||||
/* TX FIFO needs service? */
|
||||
altr_i2c_int_clear(idev, ALTR_I2C_ISR_TXRDY);
|
||||
if (idev->msg_len > 0)
|
||||
altr_i2c_fill_tx_fifo(idev);
|
||||
else
|
||||
finish = true;
|
||||
} else {
|
||||
dev_warn(idev->dev, "Unexpected interrupt: 0x%x\n", status);
|
||||
altr_i2c_int_clear(idev, ALTR_I2C_ALL_IRQ);
|
||||
}
|
||||
|
||||
if (finish) {
|
||||
/* Wait for the Core to finish */
|
||||
ret = readl_poll_timeout_atomic(idev->base + ALTR_I2C_STATUS,
|
||||
status,
|
||||
!(status & ALTR_I2C_STAT_CORE),
|
||||
1, ALTR_I2C_TIMEOUT);
|
||||
if (ret)
|
||||
dev_err(idev->dev, "message timeout\n");
|
||||
altr_i2c_int_enable(idev, ALTR_I2C_ALL_IRQ, false);
|
||||
altr_i2c_int_clear(idev, ALTR_I2C_ALL_IRQ);
|
||||
complete(&idev->msg_complete);
|
||||
dev_dbg(idev->dev, "Message Complete\n");
|
||||
}
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static int altr_i2c_xfer_msg(struct altr_i2c_dev *idev, struct i2c_msg *msg)
|
||||
{
|
||||
u32 imask = ALTR_I2C_ISR_RXOF | ALTR_I2C_ISR_ARB | ALTR_I2C_ISR_NACK;
|
||||
unsigned long time_left;
|
||||
u32 value;
|
||||
u8 addr = i2c_8bit_addr_from_msg(msg);
|
||||
|
||||
idev->msg = msg;
|
||||
idev->msg_len = msg->len;
|
||||
idev->buf = msg->buf;
|
||||
idev->msg_err = 0;
|
||||
reinit_completion(&idev->msg_complete);
|
||||
altr_i2c_core_enable(idev);
|
||||
|
||||
/* Make sure RX FIFO is empty */
|
||||
do {
|
||||
readl(idev->base + ALTR_I2C_RX_DATA);
|
||||
} while (readl(idev->base + ALTR_I2C_RX_FIFO_LVL));
|
||||
|
||||
writel(ALTR_I2C_TFR_CMD_STA | addr, idev->base + ALTR_I2C_TFR_CMD);
|
||||
|
||||
if ((msg->flags & I2C_M_RD) != 0) {
|
||||
imask |= ALTR_I2C_ISER_RXOF_EN | ALTR_I2C_ISER_RXRDY_EN;
|
||||
altr_i2c_int_enable(idev, imask, true);
|
||||
/* write the first byte to start the RX */
|
||||
altr_i2c_transfer(idev, 0);
|
||||
} else {
|
||||
imask |= ALTR_I2C_ISR_TXRDY;
|
||||
altr_i2c_int_enable(idev, imask, true);
|
||||
altr_i2c_fill_tx_fifo(idev);
|
||||
}
|
||||
|
||||
time_left = wait_for_completion_timeout(&idev->msg_complete,
|
||||
ALTR_I2C_XFER_TIMEOUT);
|
||||
altr_i2c_int_enable(idev, imask, false);
|
||||
|
||||
value = readl(idev->base + ALTR_I2C_STATUS) & ALTR_I2C_STAT_CORE;
|
||||
if (value)
|
||||
dev_err(idev->dev, "Core Status not IDLE...\n");
|
||||
|
||||
if (time_left == 0) {
|
||||
idev->msg_err = -ETIMEDOUT;
|
||||
dev_dbg(idev->dev, "Transaction timed out.\n");
|
||||
}
|
||||
|
||||
altr_i2c_core_disable(idev);
|
||||
|
||||
return idev->msg_err;
|
||||
}
|
||||
|
||||
static int
|
||||
altr_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
|
||||
{
|
||||
struct altr_i2c_dev *idev = i2c_get_adapdata(adap);
|
||||
int i, ret;
|
||||
|
||||
for (i = 0; i < num; i++) {
|
||||
ret = altr_i2c_xfer_msg(idev, msgs++);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
return num;
|
||||
}
|
||||
|
||||
static u32 altr_i2c_func(struct i2c_adapter *adap)
|
||||
{
|
||||
return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
|
||||
}
|
||||
|
||||
static const struct i2c_algorithm altr_i2c_algo = {
|
||||
.master_xfer = altr_i2c_xfer,
|
||||
.functionality = altr_i2c_func,
|
||||
};
|
||||
|
||||
static int altr_i2c_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct altr_i2c_dev *idev = NULL;
|
||||
struct resource *res;
|
||||
int irq, ret;
|
||||
u32 val;
|
||||
|
||||
idev = devm_kzalloc(&pdev->dev, sizeof(*idev), GFP_KERNEL);
|
||||
if (!idev)
|
||||
return -ENOMEM;
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
idev->base = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(idev->base))
|
||||
return PTR_ERR(idev->base);
|
||||
|
||||
irq = platform_get_irq(pdev, 0);
|
||||
if (irq < 0) {
|
||||
dev_err(&pdev->dev, "missing interrupt resource\n");
|
||||
return irq;
|
||||
}
|
||||
|
||||
idev->i2c_clk = devm_clk_get(&pdev->dev, NULL);
|
||||
if (IS_ERR(idev->i2c_clk)) {
|
||||
dev_err(&pdev->dev, "missing clock\n");
|
||||
return PTR_ERR(idev->i2c_clk);
|
||||
}
|
||||
|
||||
idev->dev = &pdev->dev;
|
||||
init_completion(&idev->msg_complete);
|
||||
spin_lock_init(&idev->lock);
|
||||
|
||||
val = device_property_read_u32(idev->dev, "fifo-size",
|
||||
&idev->fifo_size);
|
||||
if (val) {
|
||||
dev_err(&pdev->dev, "FIFO size set to default of %d\n",
|
||||
ALTR_I2C_DFLT_FIFO_SZ);
|
||||
idev->fifo_size = ALTR_I2C_DFLT_FIFO_SZ;
|
||||
}
|
||||
|
||||
val = device_property_read_u32(idev->dev, "clock-frequency",
|
||||
&idev->bus_clk_rate);
|
||||
if (val) {
|
||||
dev_err(&pdev->dev, "Default to 100kHz\n");
|
||||
idev->bus_clk_rate = 100000; /* default clock rate */
|
||||
}
|
||||
|
||||
if (idev->bus_clk_rate > 400000) {
|
||||
dev_err(&pdev->dev, "invalid clock-frequency %d\n",
|
||||
idev->bus_clk_rate);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
ret = devm_request_threaded_irq(&pdev->dev, irq, altr_i2c_isr_quick,
|
||||
altr_i2c_isr, IRQF_ONESHOT,
|
||||
pdev->name, idev);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "failed to claim IRQ %d\n", irq);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = clk_prepare_enable(idev->i2c_clk);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "failed to enable clock\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
altr_i2c_init(idev);
|
||||
|
||||
i2c_set_adapdata(&idev->adapter, idev);
|
||||
strlcpy(idev->adapter.name, pdev->name, sizeof(idev->adapter.name));
|
||||
idev->adapter.owner = THIS_MODULE;
|
||||
idev->adapter.algo = &altr_i2c_algo;
|
||||
idev->adapter.dev.parent = &pdev->dev;
|
||||
idev->adapter.dev.of_node = pdev->dev.of_node;
|
||||
|
||||
platform_set_drvdata(pdev, idev);
|
||||
|
||||
ret = i2c_add_adapter(&idev->adapter);
|
||||
if (ret) {
|
||||
clk_disable_unprepare(idev->i2c_clk);
|
||||
return ret;
|
||||
}
|
||||
dev_info(&pdev->dev, "Altera SoftIP I2C Probe Complete\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int altr_i2c_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct altr_i2c_dev *idev = platform_get_drvdata(pdev);
|
||||
|
||||
clk_disable_unprepare(idev->i2c_clk);
|
||||
i2c_del_adapter(&idev->adapter);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Match table for of_platform binding */
|
||||
static const struct of_device_id altr_i2c_of_match[] = {
|
||||
{ .compatible = "altr,softip-i2c-v1.0" },
|
||||
{},
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, altr_i2c_of_match);
|
||||
|
||||
static struct platform_driver altr_i2c_driver = {
|
||||
.probe = altr_i2c_probe,
|
||||
.remove = altr_i2c_remove,
|
||||
.driver = {
|
||||
.name = "altera-i2c",
|
||||
.of_match_table = altr_i2c_of_match,
|
||||
},
|
||||
};
|
||||
|
||||
module_platform_driver(altr_i2c_driver);
|
||||
|
||||
MODULE_DESCRIPTION("Altera Soft IP I2C bus driver");
|
||||
MODULE_AUTHOR("Thor Thayer <thor.thayer@linux.intel.com>");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
/*
|
||||
* i2c-stm32.h
|
||||
*
|
||||
* Copyright (C) M'boumba Cedric Madianga 2017
|
||||
* Author: M'boumba Cedric Madianga <cedric.madianga@gmail.com>
|
||||
*
|
||||
* License terms: GNU General Public License (GPL), version 2
|
||||
*/
|
||||
|
||||
#ifndef _I2C_STM32_H
|
||||
#define _I2C_STM32_H
|
||||
|
||||
enum stm32_i2c_speed {
|
||||
STM32_I2C_SPEED_STANDARD, /* 100 kHz */
|
||||
STM32_I2C_SPEED_FAST, /* 400 kHz */
|
||||
STM32_I2C_SPEED_FAST_PLUS, /* 1 MHz */
|
||||
STM32_I2C_SPEED_END,
|
||||
};
|
||||
|
||||
#endif /* _I2C_STM32_H */
|
||||
|
|
@ -27,6 +27,8 @@
|
|||
#include <linux/platform_device.h>
|
||||
#include <linux/reset.h>
|
||||
|
||||
#include "i2c-stm32.h"
|
||||
|
||||
/* STM32F4 I2C offset registers */
|
||||
#define STM32F4_I2C_CR1 0x00
|
||||
#define STM32F4_I2C_CR2 0x04
|
||||
|
|
@ -90,12 +92,6 @@
|
|||
#define STM32F4_I2C_MAX_FREQ 46U
|
||||
#define HZ_TO_MHZ 1000000
|
||||
|
||||
enum stm32f4_i2c_speed {
|
||||
STM32F4_I2C_SPEED_STANDARD, /* 100 kHz */
|
||||
STM32F4_I2C_SPEED_FAST, /* 400 kHz */
|
||||
STM32F4_I2C_SPEED_END,
|
||||
};
|
||||
|
||||
/**
|
||||
* struct stm32f4_i2c_msg - client specific data
|
||||
* @addr: 8-bit slave addr, including r/w bit
|
||||
|
|
@ -159,7 +155,7 @@ static int stm32f4_i2c_set_periph_clk_freq(struct stm32f4_i2c_dev *i2c_dev)
|
|||
i2c_dev->parent_rate = clk_get_rate(i2c_dev->clk);
|
||||
freq = DIV_ROUND_UP(i2c_dev->parent_rate, HZ_TO_MHZ);
|
||||
|
||||
if (i2c_dev->speed == STM32F4_I2C_SPEED_STANDARD) {
|
||||
if (i2c_dev->speed == STM32_I2C_SPEED_STANDARD) {
|
||||
/*
|
||||
* To reach 100 kHz, the parent clk frequency should be between
|
||||
* a minimum value of 2 MHz and a maximum value of 46 MHz due
|
||||
|
|
@ -216,7 +212,7 @@ static void stm32f4_i2c_set_rise_time(struct stm32f4_i2c_dev *i2c_dev)
|
|||
* is not higher than 46 MHz . As a result trise is at most 4 bits wide
|
||||
* and so fits into the TRISE bits [5:0].
|
||||
*/
|
||||
if (i2c_dev->speed == STM32F4_I2C_SPEED_STANDARD)
|
||||
if (i2c_dev->speed == STM32_I2C_SPEED_STANDARD)
|
||||
trise = freq + 1;
|
||||
else
|
||||
trise = freq * 3 / 10 + 1;
|
||||
|
|
@ -230,7 +226,7 @@ static void stm32f4_i2c_set_speed_mode(struct stm32f4_i2c_dev *i2c_dev)
|
|||
u32 val;
|
||||
u32 ccr = 0;
|
||||
|
||||
if (i2c_dev->speed == STM32F4_I2C_SPEED_STANDARD) {
|
||||
if (i2c_dev->speed == STM32_I2C_SPEED_STANDARD) {
|
||||
/*
|
||||
* In standard mode:
|
||||
* t_scl_high = t_scl_low = CCR * I2C parent clk period
|
||||
|
|
@ -808,10 +804,10 @@ static int stm32f4_i2c_probe(struct platform_device *pdev)
|
|||
udelay(2);
|
||||
reset_control_deassert(rst);
|
||||
|
||||
i2c_dev->speed = STM32F4_I2C_SPEED_STANDARD;
|
||||
i2c_dev->speed = STM32_I2C_SPEED_STANDARD;
|
||||
ret = of_property_read_u32(np, "clock-frequency", &clk_rate);
|
||||
if (!ret && clk_rate >= 400000)
|
||||
i2c_dev->speed = STM32F4_I2C_SPEED_FAST;
|
||||
i2c_dev->speed = STM32_I2C_SPEED_FAST;
|
||||
|
||||
i2c_dev->dev = &pdev->dev;
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,972 @@
|
|||
/*
|
||||
* Driver for STMicroelectronics STM32F7 I2C controller
|
||||
*
|
||||
* This I2C controller is described in the STM32F75xxx and STM32F74xxx Soc
|
||||
* reference manual.
|
||||
* Please see below a link to the documentation:
|
||||
* http://www.st.com/resource/en/reference_manual/dm00124865.pdf
|
||||
*
|
||||
* Copyright (C) M'boumba Cedric Madianga 2017
|
||||
* Author: M'boumba Cedric Madianga <cedric.madianga@gmail.com>
|
||||
*
|
||||
* This driver is based on i2c-stm32f4.c
|
||||
*
|
||||
* License terms: GNU General Public License (GPL), version 2
|
||||
*/
|
||||
#include <linux/clk.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/i2c.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/iopoll.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/reset.h>
|
||||
#include <linux/slab.h>
|
||||
|
||||
#include "i2c-stm32.h"
|
||||
|
||||
/* STM32F7 I2C registers */
|
||||
#define STM32F7_I2C_CR1 0x00
|
||||
#define STM32F7_I2C_CR2 0x04
|
||||
#define STM32F7_I2C_TIMINGR 0x10
|
||||
#define STM32F7_I2C_ISR 0x18
|
||||
#define STM32F7_I2C_ICR 0x1C
|
||||
#define STM32F7_I2C_RXDR 0x24
|
||||
#define STM32F7_I2C_TXDR 0x28
|
||||
|
||||
/* STM32F7 I2C control 1 */
|
||||
#define STM32F7_I2C_CR1_ANFOFF BIT(12)
|
||||
#define STM32F7_I2C_CR1_ERRIE BIT(7)
|
||||
#define STM32F7_I2C_CR1_TCIE BIT(6)
|
||||
#define STM32F7_I2C_CR1_STOPIE BIT(5)
|
||||
#define STM32F7_I2C_CR1_NACKIE BIT(4)
|
||||
#define STM32F7_I2C_CR1_ADDRIE BIT(3)
|
||||
#define STM32F7_I2C_CR1_RXIE BIT(2)
|
||||
#define STM32F7_I2C_CR1_TXIE BIT(1)
|
||||
#define STM32F7_I2C_CR1_PE BIT(0)
|
||||
#define STM32F7_I2C_ALL_IRQ_MASK (STM32F7_I2C_CR1_ERRIE \
|
||||
| STM32F7_I2C_CR1_TCIE \
|
||||
| STM32F7_I2C_CR1_STOPIE \
|
||||
| STM32F7_I2C_CR1_NACKIE \
|
||||
| STM32F7_I2C_CR1_RXIE \
|
||||
| STM32F7_I2C_CR1_TXIE)
|
||||
|
||||
/* STM32F7 I2C control 2 */
|
||||
#define STM32F7_I2C_CR2_RELOAD BIT(24)
|
||||
#define STM32F7_I2C_CR2_NBYTES_MASK GENMASK(23, 16)
|
||||
#define STM32F7_I2C_CR2_NBYTES(n) (((n) & 0xff) << 16)
|
||||
#define STM32F7_I2C_CR2_NACK BIT(15)
|
||||
#define STM32F7_I2C_CR2_STOP BIT(14)
|
||||
#define STM32F7_I2C_CR2_START BIT(13)
|
||||
#define STM32F7_I2C_CR2_RD_WRN BIT(10)
|
||||
#define STM32F7_I2C_CR2_SADD7_MASK GENMASK(7, 1)
|
||||
#define STM32F7_I2C_CR2_SADD7(n) (((n) & 0x7f) << 1)
|
||||
|
||||
/* STM32F7 I2C Interrupt Status */
|
||||
#define STM32F7_I2C_ISR_BUSY BIT(15)
|
||||
#define STM32F7_I2C_ISR_ARLO BIT(9)
|
||||
#define STM32F7_I2C_ISR_BERR BIT(8)
|
||||
#define STM32F7_I2C_ISR_TCR BIT(7)
|
||||
#define STM32F7_I2C_ISR_TC BIT(6)
|
||||
#define STM32F7_I2C_ISR_STOPF BIT(5)
|
||||
#define STM32F7_I2C_ISR_NACKF BIT(4)
|
||||
#define STM32F7_I2C_ISR_RXNE BIT(2)
|
||||
#define STM32F7_I2C_ISR_TXIS BIT(1)
|
||||
|
||||
/* STM32F7 I2C Interrupt Clear */
|
||||
#define STM32F7_I2C_ICR_ARLOCF BIT(9)
|
||||
#define STM32F7_I2C_ICR_BERRCF BIT(8)
|
||||
#define STM32F7_I2C_ICR_STOPCF BIT(5)
|
||||
#define STM32F7_I2C_ICR_NACKCF BIT(4)
|
||||
|
||||
/* STM32F7 I2C Timing */
|
||||
#define STM32F7_I2C_TIMINGR_PRESC(n) (((n) & 0xf) << 28)
|
||||
#define STM32F7_I2C_TIMINGR_SCLDEL(n) (((n) & 0xf) << 20)
|
||||
#define STM32F7_I2C_TIMINGR_SDADEL(n) (((n) & 0xf) << 16)
|
||||
#define STM32F7_I2C_TIMINGR_SCLH(n) (((n) & 0xff) << 8)
|
||||
#define STM32F7_I2C_TIMINGR_SCLL(n) ((n) & 0xff)
|
||||
|
||||
#define STM32F7_I2C_MAX_LEN 0xff
|
||||
|
||||
#define STM32F7_I2C_DNF_DEFAULT 0
|
||||
#define STM32F7_I2C_DNF_MAX 16
|
||||
|
||||
#define STM32F7_I2C_ANALOG_FILTER_ENABLE 1
|
||||
#define STM32F7_I2C_ANALOG_FILTER_DELAY_MIN 50 /* ns */
|
||||
#define STM32F7_I2C_ANALOG_FILTER_DELAY_MAX 260 /* ns */
|
||||
|
||||
#define STM32F7_I2C_RISE_TIME_DEFAULT 25 /* ns */
|
||||
#define STM32F7_I2C_FALL_TIME_DEFAULT 10 /* ns */
|
||||
|
||||
#define STM32F7_PRESC_MAX BIT(4)
|
||||
#define STM32F7_SCLDEL_MAX BIT(4)
|
||||
#define STM32F7_SDADEL_MAX BIT(4)
|
||||
#define STM32F7_SCLH_MAX BIT(8)
|
||||
#define STM32F7_SCLL_MAX BIT(8)
|
||||
|
||||
/**
|
||||
* struct stm32f7_i2c_spec - private i2c specification timing
|
||||
* @rate: I2C bus speed (Hz)
|
||||
* @rate_min: 80% of I2C bus speed (Hz)
|
||||
* @rate_max: 100% of I2C bus speed (Hz)
|
||||
* @fall_max: Max fall time of both SDA and SCL signals (ns)
|
||||
* @rise_max: Max rise time of both SDA and SCL signals (ns)
|
||||
* @hddat_min: Min data hold time (ns)
|
||||
* @vddat_max: Max data valid time (ns)
|
||||
* @sudat_min: Min data setup time (ns)
|
||||
* @l_min: Min low period of the SCL clock (ns)
|
||||
* @h_min: Min high period of the SCL clock (ns)
|
||||
*/
|
||||
struct stm32f7_i2c_spec {
|
||||
u32 rate;
|
||||
u32 rate_min;
|
||||
u32 rate_max;
|
||||
u32 fall_max;
|
||||
u32 rise_max;
|
||||
u32 hddat_min;
|
||||
u32 vddat_max;
|
||||
u32 sudat_min;
|
||||
u32 l_min;
|
||||
u32 h_min;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct stm32f7_i2c_setup - private I2C timing setup parameters
|
||||
* @speed: I2C speed mode (standard, Fast Plus)
|
||||
* @speed_freq: I2C speed frequency (Hz)
|
||||
* @clock_src: I2C clock source frequency (Hz)
|
||||
* @rise_time: Rise time (ns)
|
||||
* @fall_time: Fall time (ns)
|
||||
* @dnf: Digital filter coefficient (0-16)
|
||||
* @analog_filter: Analog filter delay (On/Off)
|
||||
*/
|
||||
struct stm32f7_i2c_setup {
|
||||
enum stm32_i2c_speed speed;
|
||||
u32 speed_freq;
|
||||
u32 clock_src;
|
||||
u32 rise_time;
|
||||
u32 fall_time;
|
||||
u8 dnf;
|
||||
bool analog_filter;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct stm32f7_i2c_timings - private I2C output parameters
|
||||
* @prec: Prescaler value
|
||||
* @scldel: Data setup time
|
||||
* @sdadel: Data hold time
|
||||
* @sclh: SCL high period (master mode)
|
||||
* @sclh: SCL low period (master mode)
|
||||
*/
|
||||
struct stm32f7_i2c_timings {
|
||||
struct list_head node;
|
||||
u8 presc;
|
||||
u8 scldel;
|
||||
u8 sdadel;
|
||||
u8 sclh;
|
||||
u8 scll;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct stm32f7_i2c_msg - client specific data
|
||||
* @addr: 8-bit slave addr, including r/w bit
|
||||
* @count: number of bytes to be transferred
|
||||
* @buf: data buffer
|
||||
* @result: result of the transfer
|
||||
* @stop: last I2C msg to be sent, i.e. STOP to be generated
|
||||
*/
|
||||
struct stm32f7_i2c_msg {
|
||||
u8 addr;
|
||||
u32 count;
|
||||
u8 *buf;
|
||||
int result;
|
||||
bool stop;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct stm32f7_i2c_dev - private data of the controller
|
||||
* @adap: I2C adapter for this controller
|
||||
* @dev: device for this controller
|
||||
* @base: virtual memory area
|
||||
* @complete: completion of I2C message
|
||||
* @clk: hw i2c clock
|
||||
* @speed: I2C clock frequency of the controller. Standard, Fast or Fast+
|
||||
* @msg: Pointer to data to be written
|
||||
* @msg_num: number of I2C messages to be executed
|
||||
* @msg_id: message identifiant
|
||||
* @f7_msg: customized i2c msg for driver usage
|
||||
* @setup: I2C timing input setup
|
||||
* @timing: I2C computed timings
|
||||
*/
|
||||
struct stm32f7_i2c_dev {
|
||||
struct i2c_adapter adap;
|
||||
struct device *dev;
|
||||
void __iomem *base;
|
||||
struct completion complete;
|
||||
struct clk *clk;
|
||||
int speed;
|
||||
struct i2c_msg *msg;
|
||||
unsigned int msg_num;
|
||||
unsigned int msg_id;
|
||||
struct stm32f7_i2c_msg f7_msg;
|
||||
struct stm32f7_i2c_setup *setup;
|
||||
struct stm32f7_i2c_timings timing;
|
||||
};
|
||||
|
||||
/**
|
||||
* All these values are coming from I2C Specification, Version 6.0, 4th of
|
||||
* April 2014.
|
||||
*
|
||||
* Table10. Characteristics of the SDA and SCL bus lines for Standard, Fast,
|
||||
* and Fast-mode Plus I2C-bus devices
|
||||
*/
|
||||
static struct stm32f7_i2c_spec i2c_specs[] = {
|
||||
[STM32_I2C_SPEED_STANDARD] = {
|
||||
.rate = 100000,
|
||||
.rate_min = 80000,
|
||||
.rate_max = 100000,
|
||||
.fall_max = 300,
|
||||
.rise_max = 1000,
|
||||
.hddat_min = 0,
|
||||
.vddat_max = 3450,
|
||||
.sudat_min = 250,
|
||||
.l_min = 4700,
|
||||
.h_min = 4000,
|
||||
},
|
||||
[STM32_I2C_SPEED_FAST] = {
|
||||
.rate = 400000,
|
||||
.rate_min = 320000,
|
||||
.rate_max = 400000,
|
||||
.fall_max = 300,
|
||||
.rise_max = 300,
|
||||
.hddat_min = 0,
|
||||
.vddat_max = 900,
|
||||
.sudat_min = 100,
|
||||
.l_min = 1300,
|
||||
.h_min = 600,
|
||||
},
|
||||
[STM32_I2C_SPEED_FAST_PLUS] = {
|
||||
.rate = 1000000,
|
||||
.rate_min = 800000,
|
||||
.rate_max = 1000000,
|
||||
.fall_max = 100,
|
||||
.rise_max = 120,
|
||||
.hddat_min = 0,
|
||||
.vddat_max = 450,
|
||||
.sudat_min = 50,
|
||||
.l_min = 500,
|
||||
.h_min = 260,
|
||||
},
|
||||
};
|
||||
|
||||
struct stm32f7_i2c_setup stm32f7_setup = {
|
||||
.rise_time = STM32F7_I2C_RISE_TIME_DEFAULT,
|
||||
.fall_time = STM32F7_I2C_FALL_TIME_DEFAULT,
|
||||
.dnf = STM32F7_I2C_DNF_DEFAULT,
|
||||
.analog_filter = STM32F7_I2C_ANALOG_FILTER_ENABLE,
|
||||
};
|
||||
|
||||
static inline void stm32f7_i2c_set_bits(void __iomem *reg, u32 mask)
|
||||
{
|
||||
writel_relaxed(readl_relaxed(reg) | mask, reg);
|
||||
}
|
||||
|
||||
static inline void stm32f7_i2c_clr_bits(void __iomem *reg, u32 mask)
|
||||
{
|
||||
writel_relaxed(readl_relaxed(reg) & ~mask, reg);
|
||||
}
|
||||
|
||||
static int stm32f7_i2c_compute_timing(struct stm32f7_i2c_dev *i2c_dev,
|
||||
struct stm32f7_i2c_setup *setup,
|
||||
struct stm32f7_i2c_timings *output)
|
||||
{
|
||||
u32 p_prev = STM32F7_PRESC_MAX;
|
||||
u32 i2cclk = DIV_ROUND_CLOSEST(NSEC_PER_SEC,
|
||||
setup->clock_src);
|
||||
u32 i2cbus = DIV_ROUND_CLOSEST(NSEC_PER_SEC,
|
||||
setup->speed_freq);
|
||||
u32 clk_error_prev = i2cbus;
|
||||
u32 tsync;
|
||||
u32 af_delay_min, af_delay_max;
|
||||
u32 dnf_delay;
|
||||
u32 clk_min, clk_max;
|
||||
int sdadel_min, sdadel_max;
|
||||
int scldel_min;
|
||||
struct stm32f7_i2c_timings *v, *_v, *s;
|
||||
struct list_head solutions;
|
||||
u16 p, l, a, h;
|
||||
int ret = 0;
|
||||
|
||||
if (setup->speed >= STM32_I2C_SPEED_END) {
|
||||
dev_err(i2c_dev->dev, "speed out of bound {%d/%d}\n",
|
||||
setup->speed, STM32_I2C_SPEED_END - 1);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if ((setup->rise_time > i2c_specs[setup->speed].rise_max) ||
|
||||
(setup->fall_time > i2c_specs[setup->speed].fall_max)) {
|
||||
dev_err(i2c_dev->dev,
|
||||
"timings out of bound Rise{%d>%d}/Fall{%d>%d}\n",
|
||||
setup->rise_time, i2c_specs[setup->speed].rise_max,
|
||||
setup->fall_time, i2c_specs[setup->speed].fall_max);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (setup->dnf > STM32F7_I2C_DNF_MAX) {
|
||||
dev_err(i2c_dev->dev,
|
||||
"DNF out of bound %d/%d\n",
|
||||
setup->dnf, STM32F7_I2C_DNF_MAX);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (setup->speed_freq > i2c_specs[setup->speed].rate) {
|
||||
dev_err(i2c_dev->dev, "ERROR: Freq {%d/%d}\n",
|
||||
setup->speed_freq, i2c_specs[setup->speed].rate);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* Analog and Digital Filters */
|
||||
af_delay_min =
|
||||
(setup->analog_filter ?
|
||||
STM32F7_I2C_ANALOG_FILTER_DELAY_MIN : 0);
|
||||
af_delay_max =
|
||||
(setup->analog_filter ?
|
||||
STM32F7_I2C_ANALOG_FILTER_DELAY_MAX : 0);
|
||||
dnf_delay = setup->dnf * i2cclk;
|
||||
|
||||
sdadel_min = setup->fall_time - i2c_specs[setup->speed].hddat_min -
|
||||
af_delay_min - (setup->dnf + 3) * i2cclk;
|
||||
|
||||
sdadel_max = i2c_specs[setup->speed].vddat_max - setup->rise_time -
|
||||
af_delay_max - (setup->dnf + 4) * i2cclk;
|
||||
|
||||
scldel_min = setup->rise_time + i2c_specs[setup->speed].sudat_min;
|
||||
|
||||
if (sdadel_min < 0)
|
||||
sdadel_min = 0;
|
||||
if (sdadel_max < 0)
|
||||
sdadel_max = 0;
|
||||
|
||||
dev_dbg(i2c_dev->dev, "SDADEL(min/max): %i/%i, SCLDEL(Min): %i\n",
|
||||
sdadel_min, sdadel_max, scldel_min);
|
||||
|
||||
INIT_LIST_HEAD(&solutions);
|
||||
/* Compute possible values for PRESC, SCLDEL and SDADEL */
|
||||
for (p = 0; p < STM32F7_PRESC_MAX; p++) {
|
||||
for (l = 0; l < STM32F7_SCLDEL_MAX; l++) {
|
||||
u32 scldel = (l + 1) * (p + 1) * i2cclk;
|
||||
|
||||
if (scldel < scldel_min)
|
||||
continue;
|
||||
|
||||
for (a = 0; a < STM32F7_SDADEL_MAX; a++) {
|
||||
u32 sdadel = (a * (p + 1) + 1) * i2cclk;
|
||||
|
||||
if (((sdadel >= sdadel_min) &&
|
||||
(sdadel <= sdadel_max)) &&
|
||||
(p != p_prev)) {
|
||||
v = kmalloc(sizeof(*v), GFP_KERNEL);
|
||||
if (!v) {
|
||||
ret = -ENOMEM;
|
||||
goto exit;
|
||||
}
|
||||
|
||||
v->presc = p;
|
||||
v->scldel = l;
|
||||
v->sdadel = a;
|
||||
p_prev = p;
|
||||
|
||||
list_add_tail(&v->node,
|
||||
&solutions);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (list_empty(&solutions)) {
|
||||
dev_err(i2c_dev->dev, "no Prescaler solution\n");
|
||||
ret = -EPERM;
|
||||
goto exit;
|
||||
}
|
||||
|
||||
tsync = af_delay_min + dnf_delay + (2 * i2cclk);
|
||||
s = NULL;
|
||||
clk_max = NSEC_PER_SEC / i2c_specs[setup->speed].rate_min;
|
||||
clk_min = NSEC_PER_SEC / i2c_specs[setup->speed].rate_max;
|
||||
|
||||
/*
|
||||
* Among Prescaler possibilities discovered above figures out SCL Low
|
||||
* and High Period. Provided:
|
||||
* - SCL Low Period has to be higher than SCL Clock Low Period
|
||||
* defined by I2C Specification. I2C Clock has to be lower than
|
||||
* (SCL Low Period - Analog/Digital filters) / 4.
|
||||
* - SCL High Period has to be lower than SCL Clock High Period
|
||||
* defined by I2C Specification
|
||||
* - I2C Clock has to be lower than SCL High Period
|
||||
*/
|
||||
list_for_each_entry(v, &solutions, node) {
|
||||
u32 prescaler = (v->presc + 1) * i2cclk;
|
||||
|
||||
for (l = 0; l < STM32F7_SCLL_MAX; l++) {
|
||||
u32 tscl_l = (l + 1) * prescaler + tsync;
|
||||
|
||||
if ((tscl_l < i2c_specs[setup->speed].l_min) ||
|
||||
(i2cclk >=
|
||||
((tscl_l - af_delay_min - dnf_delay) / 4))) {
|
||||
continue;
|
||||
}
|
||||
|
||||
for (h = 0; h < STM32F7_SCLH_MAX; h++) {
|
||||
u32 tscl_h = (h + 1) * prescaler + tsync;
|
||||
u32 tscl = tscl_l + tscl_h +
|
||||
setup->rise_time + setup->fall_time;
|
||||
|
||||
if ((tscl >= clk_min) && (tscl <= clk_max) &&
|
||||
(tscl_h >= i2c_specs[setup->speed].h_min) &&
|
||||
(i2cclk < tscl_h)) {
|
||||
int clk_error = tscl - i2cbus;
|
||||
|
||||
if (clk_error < 0)
|
||||
clk_error = -clk_error;
|
||||
|
||||
if (clk_error < clk_error_prev) {
|
||||
clk_error_prev = clk_error;
|
||||
v->scll = l;
|
||||
v->sclh = h;
|
||||
s = v;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (!s) {
|
||||
dev_err(i2c_dev->dev, "no solution at all\n");
|
||||
ret = -EPERM;
|
||||
goto exit;
|
||||
}
|
||||
|
||||
output->presc = s->presc;
|
||||
output->scldel = s->scldel;
|
||||
output->sdadel = s->sdadel;
|
||||
output->scll = s->scll;
|
||||
output->sclh = s->sclh;
|
||||
|
||||
dev_dbg(i2c_dev->dev,
|
||||
"Presc: %i, scldel: %i, sdadel: %i, scll: %i, sclh: %i\n",
|
||||
output->presc,
|
||||
output->scldel, output->sdadel,
|
||||
output->scll, output->sclh);
|
||||
|
||||
exit:
|
||||
/* Release list and memory */
|
||||
list_for_each_entry_safe(v, _v, &solutions, node) {
|
||||
list_del(&v->node);
|
||||
kfree(v);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int stm32f7_i2c_setup_timing(struct stm32f7_i2c_dev *i2c_dev,
|
||||
struct stm32f7_i2c_setup *setup)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
setup->speed = i2c_dev->speed;
|
||||
setup->speed_freq = i2c_specs[setup->speed].rate;
|
||||
setup->clock_src = clk_get_rate(i2c_dev->clk);
|
||||
|
||||
if (!setup->clock_src) {
|
||||
dev_err(i2c_dev->dev, "clock rate is 0\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
do {
|
||||
ret = stm32f7_i2c_compute_timing(i2c_dev, setup,
|
||||
&i2c_dev->timing);
|
||||
if (ret) {
|
||||
dev_err(i2c_dev->dev,
|
||||
"failed to compute I2C timings.\n");
|
||||
if (i2c_dev->speed > STM32_I2C_SPEED_STANDARD) {
|
||||
i2c_dev->speed--;
|
||||
setup->speed = i2c_dev->speed;
|
||||
setup->speed_freq =
|
||||
i2c_specs[setup->speed].rate;
|
||||
dev_warn(i2c_dev->dev,
|
||||
"downgrade I2C Speed Freq to (%i)\n",
|
||||
i2c_specs[setup->speed].rate);
|
||||
} else {
|
||||
break;
|
||||
}
|
||||
}
|
||||
} while (ret);
|
||||
|
||||
if (ret) {
|
||||
dev_err(i2c_dev->dev, "Impossible to compute I2C timings.\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
dev_dbg(i2c_dev->dev, "I2C Speed(%i), Freq(%i), Clk Source(%i)\n",
|
||||
setup->speed, setup->speed_freq, setup->clock_src);
|
||||
dev_dbg(i2c_dev->dev, "I2C Rise(%i) and Fall(%i) Time\n",
|
||||
setup->rise_time, setup->fall_time);
|
||||
dev_dbg(i2c_dev->dev, "I2C Analog Filter(%s), DNF(%i)\n",
|
||||
(setup->analog_filter ? "On" : "Off"), setup->dnf);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void stm32f7_i2c_hw_config(struct stm32f7_i2c_dev *i2c_dev)
|
||||
{
|
||||
struct stm32f7_i2c_timings *t = &i2c_dev->timing;
|
||||
u32 timing = 0;
|
||||
|
||||
/* Timing settings */
|
||||
timing |= STM32F7_I2C_TIMINGR_PRESC(t->presc);
|
||||
timing |= STM32F7_I2C_TIMINGR_SCLDEL(t->scldel);
|
||||
timing |= STM32F7_I2C_TIMINGR_SDADEL(t->sdadel);
|
||||
timing |= STM32F7_I2C_TIMINGR_SCLH(t->sclh);
|
||||
timing |= STM32F7_I2C_TIMINGR_SCLL(t->scll);
|
||||
writel_relaxed(timing, i2c_dev->base + STM32F7_I2C_TIMINGR);
|
||||
|
||||
/* Enable I2C */
|
||||
if (i2c_dev->setup->analog_filter)
|
||||
stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
|
||||
STM32F7_I2C_CR1_ANFOFF);
|
||||
else
|
||||
stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
|
||||
STM32F7_I2C_CR1_ANFOFF);
|
||||
stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
|
||||
STM32F7_I2C_CR1_PE);
|
||||
}
|
||||
|
||||
static void stm32f7_i2c_write_tx_data(struct stm32f7_i2c_dev *i2c_dev)
|
||||
{
|
||||
struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
|
||||
void __iomem *base = i2c_dev->base;
|
||||
|
||||
if (f7_msg->count) {
|
||||
writeb_relaxed(*f7_msg->buf++, base + STM32F7_I2C_TXDR);
|
||||
f7_msg->count--;
|
||||
}
|
||||
}
|
||||
|
||||
static void stm32f7_i2c_read_rx_data(struct stm32f7_i2c_dev *i2c_dev)
|
||||
{
|
||||
struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
|
||||
void __iomem *base = i2c_dev->base;
|
||||
|
||||
if (f7_msg->count) {
|
||||
*f7_msg->buf++ = readb_relaxed(base + STM32F7_I2C_RXDR);
|
||||
f7_msg->count--;
|
||||
}
|
||||
}
|
||||
|
||||
static void stm32f7_i2c_reload(struct stm32f7_i2c_dev *i2c_dev)
|
||||
{
|
||||
struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
|
||||
u32 cr2;
|
||||
|
||||
cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
|
||||
|
||||
cr2 &= ~STM32F7_I2C_CR2_NBYTES_MASK;
|
||||
if (f7_msg->count > STM32F7_I2C_MAX_LEN) {
|
||||
cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN);
|
||||
} else {
|
||||
cr2 &= ~STM32F7_I2C_CR2_RELOAD;
|
||||
cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
|
||||
}
|
||||
|
||||
writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
|
||||
}
|
||||
|
||||
static int stm32f7_i2c_wait_free_bus(struct stm32f7_i2c_dev *i2c_dev)
|
||||
{
|
||||
u32 status;
|
||||
int ret;
|
||||
|
||||
ret = readl_relaxed_poll_timeout(i2c_dev->base + STM32F7_I2C_ISR,
|
||||
status,
|
||||
!(status & STM32F7_I2C_ISR_BUSY),
|
||||
10, 1000);
|
||||
if (ret) {
|
||||
dev_dbg(i2c_dev->dev, "bus busy\n");
|
||||
ret = -EBUSY;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void stm32f7_i2c_xfer_msg(struct stm32f7_i2c_dev *i2c_dev,
|
||||
struct i2c_msg *msg)
|
||||
{
|
||||
struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
|
||||
void __iomem *base = i2c_dev->base;
|
||||
u32 cr1, cr2;
|
||||
|
||||
f7_msg->addr = msg->addr;
|
||||
f7_msg->buf = msg->buf;
|
||||
f7_msg->count = msg->len;
|
||||
f7_msg->result = 0;
|
||||
f7_msg->stop = (i2c_dev->msg_id >= i2c_dev->msg_num - 1);
|
||||
|
||||
reinit_completion(&i2c_dev->complete);
|
||||
|
||||
cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
|
||||
cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
|
||||
|
||||
/* Set transfer direction */
|
||||
cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
|
||||
if (msg->flags & I2C_M_RD)
|
||||
cr2 |= STM32F7_I2C_CR2_RD_WRN;
|
||||
|
||||
/* Set slave address */
|
||||
cr2 &= ~STM32F7_I2C_CR2_SADD7_MASK;
|
||||
cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr);
|
||||
|
||||
/* Set nb bytes to transfer and reload if needed */
|
||||
cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
|
||||
if (f7_msg->count > STM32F7_I2C_MAX_LEN) {
|
||||
cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN);
|
||||
cr2 |= STM32F7_I2C_CR2_RELOAD;
|
||||
} else {
|
||||
cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
|
||||
}
|
||||
|
||||
/* Enable NACK, STOP, error and transfer complete interrupts */
|
||||
cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE |
|
||||
STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE;
|
||||
|
||||
/* Clear TX/RX interrupt */
|
||||
cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE);
|
||||
|
||||
/* Enable RX/TX interrupt according to msg direction */
|
||||
if (msg->flags & I2C_M_RD)
|
||||
cr1 |= STM32F7_I2C_CR1_RXIE;
|
||||
else
|
||||
cr1 |= STM32F7_I2C_CR1_TXIE;
|
||||
|
||||
/* Configure Start/Repeated Start */
|
||||
cr2 |= STM32F7_I2C_CR2_START;
|
||||
|
||||
/* Write configurations registers */
|
||||
writel_relaxed(cr1, base + STM32F7_I2C_CR1);
|
||||
writel_relaxed(cr2, base + STM32F7_I2C_CR2);
|
||||
}
|
||||
|
||||
static void stm32f7_i2c_disable_irq(struct stm32f7_i2c_dev *i2c_dev, u32 mask)
|
||||
{
|
||||
stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, mask);
|
||||
}
|
||||
|
||||
static irqreturn_t stm32f7_i2c_isr_event(int irq, void *data)
|
||||
{
|
||||
struct stm32f7_i2c_dev *i2c_dev = data;
|
||||
struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
|
||||
void __iomem *base = i2c_dev->base;
|
||||
u32 status, mask;
|
||||
|
||||
status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
|
||||
|
||||
/* Tx empty */
|
||||
if (status & STM32F7_I2C_ISR_TXIS)
|
||||
stm32f7_i2c_write_tx_data(i2c_dev);
|
||||
|
||||
/* RX not empty */
|
||||
if (status & STM32F7_I2C_ISR_RXNE)
|
||||
stm32f7_i2c_read_rx_data(i2c_dev);
|
||||
|
||||
/* NACK received */
|
||||
if (status & STM32F7_I2C_ISR_NACKF) {
|
||||
dev_dbg(i2c_dev->dev, "<%s>: Receive NACK\n", __func__);
|
||||
writel_relaxed(STM32F7_I2C_ICR_NACKCF, base + STM32F7_I2C_ICR);
|
||||
f7_msg->result = -ENXIO;
|
||||
}
|
||||
|
||||
/* STOP detection flag */
|
||||
if (status & STM32F7_I2C_ISR_STOPF) {
|
||||
/* Disable interrupts */
|
||||
stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_ALL_IRQ_MASK);
|
||||
|
||||
/* Clear STOP flag */
|
||||
writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR);
|
||||
|
||||
complete(&i2c_dev->complete);
|
||||
}
|
||||
|
||||
/* Transfer complete */
|
||||
if (status & STM32F7_I2C_ISR_TC) {
|
||||
if (f7_msg->stop) {
|
||||
mask = STM32F7_I2C_CR2_STOP;
|
||||
stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
|
||||
} else {
|
||||
i2c_dev->msg_id++;
|
||||
i2c_dev->msg++;
|
||||
stm32f7_i2c_xfer_msg(i2c_dev, i2c_dev->msg);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Transfer Complete Reload: 255 data bytes have been transferred
|
||||
* We have to prepare the I2C controller to transfer the remaining
|
||||
* data.
|
||||
*/
|
||||
if (status & STM32F7_I2C_ISR_TCR)
|
||||
stm32f7_i2c_reload(i2c_dev);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static irqreturn_t stm32f7_i2c_isr_error(int irq, void *data)
|
||||
{
|
||||
struct stm32f7_i2c_dev *i2c_dev = data;
|
||||
struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
|
||||
void __iomem *base = i2c_dev->base;
|
||||
struct device *dev = i2c_dev->dev;
|
||||
u32 status;
|
||||
|
||||
status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
|
||||
|
||||
/* Bus error */
|
||||
if (status & STM32F7_I2C_ISR_BERR) {
|
||||
dev_err(dev, "<%s>: Bus error\n", __func__);
|
||||
writel_relaxed(STM32F7_I2C_ICR_BERRCF, base + STM32F7_I2C_ICR);
|
||||
f7_msg->result = -EIO;
|
||||
}
|
||||
|
||||
/* Arbitration loss */
|
||||
if (status & STM32F7_I2C_ISR_ARLO) {
|
||||
dev_dbg(dev, "<%s>: Arbitration loss\n", __func__);
|
||||
writel_relaxed(STM32F7_I2C_ICR_ARLOCF, base + STM32F7_I2C_ICR);
|
||||
f7_msg->result = -EAGAIN;
|
||||
}
|
||||
|
||||
stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_ALL_IRQ_MASK);
|
||||
|
||||
complete(&i2c_dev->complete);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static int stm32f7_i2c_xfer(struct i2c_adapter *i2c_adap,
|
||||
struct i2c_msg msgs[], int num)
|
||||
{
|
||||
struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap);
|
||||
struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
|
||||
unsigned long time_left;
|
||||
int ret;
|
||||
|
||||
i2c_dev->msg = msgs;
|
||||
i2c_dev->msg_num = num;
|
||||
i2c_dev->msg_id = 0;
|
||||
|
||||
ret = clk_enable(i2c_dev->clk);
|
||||
if (ret) {
|
||||
dev_err(i2c_dev->dev, "Failed to enable clock\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = stm32f7_i2c_wait_free_bus(i2c_dev);
|
||||
if (ret)
|
||||
goto clk_free;
|
||||
|
||||
stm32f7_i2c_xfer_msg(i2c_dev, msgs);
|
||||
|
||||
time_left = wait_for_completion_timeout(&i2c_dev->complete,
|
||||
i2c_dev->adap.timeout);
|
||||
ret = f7_msg->result;
|
||||
|
||||
if (!time_left) {
|
||||
dev_dbg(i2c_dev->dev, "Access to slave 0x%x timed out\n",
|
||||
i2c_dev->msg->addr);
|
||||
ret = -ETIMEDOUT;
|
||||
}
|
||||
|
||||
clk_free:
|
||||
clk_disable(i2c_dev->clk);
|
||||
|
||||
return (ret < 0) ? ret : num;
|
||||
}
|
||||
|
||||
static u32 stm32f7_i2c_func(struct i2c_adapter *adap)
|
||||
{
|
||||
return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
|
||||
}
|
||||
|
||||
static struct i2c_algorithm stm32f7_i2c_algo = {
|
||||
.master_xfer = stm32f7_i2c_xfer,
|
||||
.functionality = stm32f7_i2c_func,
|
||||
};
|
||||
|
||||
static int stm32f7_i2c_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device_node *np = pdev->dev.of_node;
|
||||
struct stm32f7_i2c_dev *i2c_dev;
|
||||
const struct stm32f7_i2c_setup *setup;
|
||||
struct resource *res;
|
||||
u32 irq_error, irq_event, clk_rate, rise_time, fall_time;
|
||||
struct i2c_adapter *adap;
|
||||
struct reset_control *rst;
|
||||
int ret;
|
||||
|
||||
i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
|
||||
if (!i2c_dev)
|
||||
return -ENOMEM;
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
i2c_dev->base = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(i2c_dev->base))
|
||||
return PTR_ERR(i2c_dev->base);
|
||||
|
||||
irq_event = irq_of_parse_and_map(np, 0);
|
||||
if (!irq_event) {
|
||||
dev_err(&pdev->dev, "IRQ event missing or invalid\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
irq_error = irq_of_parse_and_map(np, 1);
|
||||
if (!irq_error) {
|
||||
dev_err(&pdev->dev, "IRQ error missing or invalid\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
i2c_dev->clk = devm_clk_get(&pdev->dev, NULL);
|
||||
if (IS_ERR(i2c_dev->clk)) {
|
||||
dev_err(&pdev->dev, "Error: Missing controller clock\n");
|
||||
return PTR_ERR(i2c_dev->clk);
|
||||
}
|
||||
ret = clk_prepare_enable(i2c_dev->clk);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "Failed to prepare_enable clock\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
i2c_dev->speed = STM32_I2C_SPEED_STANDARD;
|
||||
ret = device_property_read_u32(&pdev->dev, "clock-frequency",
|
||||
&clk_rate);
|
||||
if (!ret && clk_rate >= 1000000)
|
||||
i2c_dev->speed = STM32_I2C_SPEED_FAST_PLUS;
|
||||
else if (!ret && clk_rate >= 400000)
|
||||
i2c_dev->speed = STM32_I2C_SPEED_FAST;
|
||||
else if (!ret && clk_rate >= 100000)
|
||||
i2c_dev->speed = STM32_I2C_SPEED_STANDARD;
|
||||
|
||||
rst = devm_reset_control_get(&pdev->dev, NULL);
|
||||
if (IS_ERR(rst)) {
|
||||
dev_err(&pdev->dev, "Error: Missing controller reset\n");
|
||||
ret = PTR_ERR(rst);
|
||||
goto clk_free;
|
||||
}
|
||||
reset_control_assert(rst);
|
||||
udelay(2);
|
||||
reset_control_deassert(rst);
|
||||
|
||||
i2c_dev->dev = &pdev->dev;
|
||||
|
||||
ret = devm_request_irq(&pdev->dev, irq_event, stm32f7_i2c_isr_event, 0,
|
||||
pdev->name, i2c_dev);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "Failed to request irq event %i\n",
|
||||
irq_event);
|
||||
goto clk_free;
|
||||
}
|
||||
|
||||
ret = devm_request_irq(&pdev->dev, irq_error, stm32f7_i2c_isr_error, 0,
|
||||
pdev->name, i2c_dev);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "Failed to request irq error %i\n",
|
||||
irq_error);
|
||||
goto clk_free;
|
||||
}
|
||||
|
||||
setup = of_device_get_match_data(&pdev->dev);
|
||||
i2c_dev->setup->rise_time = setup->rise_time;
|
||||
i2c_dev->setup->fall_time = setup->fall_time;
|
||||
i2c_dev->setup->dnf = setup->dnf;
|
||||
i2c_dev->setup->analog_filter = setup->analog_filter;
|
||||
|
||||
ret = device_property_read_u32(i2c_dev->dev, "i2c-scl-rising-time-ns",
|
||||
&rise_time);
|
||||
if (!ret)
|
||||
i2c_dev->setup->rise_time = rise_time;
|
||||
|
||||
ret = device_property_read_u32(i2c_dev->dev, "i2c-scl-falling-time-ns",
|
||||
&fall_time);
|
||||
if (!ret)
|
||||
i2c_dev->setup->fall_time = fall_time;
|
||||
|
||||
ret = stm32f7_i2c_setup_timing(i2c_dev, i2c_dev->setup);
|
||||
if (ret)
|
||||
goto clk_free;
|
||||
|
||||
stm32f7_i2c_hw_config(i2c_dev);
|
||||
|
||||
adap = &i2c_dev->adap;
|
||||
i2c_set_adapdata(adap, i2c_dev);
|
||||
snprintf(adap->name, sizeof(adap->name), "STM32F7 I2C(%pa)",
|
||||
&res->start);
|
||||
adap->owner = THIS_MODULE;
|
||||
adap->timeout = 2 * HZ;
|
||||
adap->retries = 3;
|
||||
adap->algo = &stm32f7_i2c_algo;
|
||||
adap->dev.parent = &pdev->dev;
|
||||
adap->dev.of_node = pdev->dev.of_node;
|
||||
|
||||
init_completion(&i2c_dev->complete);
|
||||
|
||||
ret = i2c_add_adapter(adap);
|
||||
if (ret)
|
||||
goto clk_free;
|
||||
|
||||
platform_set_drvdata(pdev, i2c_dev);
|
||||
|
||||
clk_disable(i2c_dev->clk);
|
||||
|
||||
dev_info(i2c_dev->dev, "STM32F7 I2C-%d bus adapter\n", adap->nr);
|
||||
|
||||
return 0;
|
||||
|
||||
clk_free:
|
||||
clk_disable_unprepare(i2c_dev->clk);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int stm32f7_i2c_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct stm32f7_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
|
||||
|
||||
i2c_del_adapter(&i2c_dev->adap);
|
||||
|
||||
clk_unprepare(i2c_dev->clk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id stm32f7_i2c_match[] = {
|
||||
{ .compatible = "st,stm32f7-i2c", .data = &stm32f7_setup},
|
||||
{},
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, stm32f7_i2c_match);
|
||||
|
||||
static struct platform_driver stm32f7_i2c_driver = {
|
||||
.driver = {
|
||||
.name = "stm32f7-i2c",
|
||||
.of_match_table = stm32f7_i2c_match,
|
||||
},
|
||||
.probe = stm32f7_i2c_probe,
|
||||
.remove = stm32f7_i2c_remove,
|
||||
};
|
||||
|
||||
module_platform_driver(stm32f7_i2c_driver);
|
||||
|
||||
MODULE_AUTHOR("M'boumba Cedric Madianga <cedric.madianga@gmail.com>");
|
||||
MODULE_DESCRIPTION("STMicroelectronics STM32F7 I2C driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
Loading…
Reference in New Issue