MIPS: Alchemy: MTX-1: Use linux gpio api.
Replace a few GPIO register accesses in the board init code with calls to the gpio api. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -28,6 +28,7 @@
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/gpio.h>
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#include <linux/init.h>
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#include <asm/mach-au1x00/au1000.h>
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@ -55,10 +56,11 @@ void __init board_setup(void)
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}
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#endif
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alchemy_gpio2_enable();
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#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
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/* Enable USB power switch */
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au_writel(au_readl(GPIO2_DIR) | 0x10, GPIO2_DIR);
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au_writel(0x100000, GPIO2_OUTPUT);
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alchemy_gpio_direction_output(204, 0);
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#endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */
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#ifdef CONFIG_PCI
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@ -74,14 +76,14 @@ void __init board_setup(void)
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/* Initialize GPIO */
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au_writel(0xFFFFFFFF, SYS_TRIOUTCLR);
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au_writel(0x00000001, SYS_OUTPUTCLR); /* set M66EN (PCI 66MHz) to OFF */
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au_writel(0x00000008, SYS_OUTPUTSET); /* set PCI CLKRUN# to OFF */
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au_writel(0x00000002, SYS_OUTPUTSET); /* set EXT_IO3 ON */
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au_writel(0x00000020, SYS_OUTPUTCLR); /* set eth PHY TX_ER to OFF */
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alchemy_gpio_direction_output(0, 0); /* Disable M66EN (PCI 66MHz) */
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alchemy_gpio_direction_output(3, 1); /* Disable PCI CLKRUN# */
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alchemy_gpio_direction_output(1, 1); /* Enable EXT_IO3 */
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alchemy_gpio_direction_output(5, 0); /* Disable eth PHY TX_ER */
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/* Enable LED and set it to green */
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au_writel(au_readl(GPIO2_DIR) | 0x1800, GPIO2_DIR);
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au_writel(0x18000800, GPIO2_OUTPUT);
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alchemy_gpio_direction_output(211, 1); /* green on */
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alchemy_gpio_direction_output(212, 0); /* red off */
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board_pci_idsel = mtx1_pci_idsel;
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@ -101,10 +103,10 @@ mtx1_pci_idsel(unsigned int devsel, int assert)
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if (assert && devsel != 0)
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/* Suppress signal to Cardbus */
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au_writel(0x00000002, SYS_OUTPUTCLR); /* set EXT_IO3 OFF */
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gpio_set_value(1, 0); /* set EXT_IO3 OFF */
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else
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au_writel(0x00000002, SYS_OUTPUTSET); /* set EXT_IO3 ON */
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gpio_set_value(1, 1); /* set EXT_IO3 ON */
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au_sync_udelay(1);
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return 1;
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}
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