igb: add support for 82580 MAC
This patch adds support for the 82580 MAC. Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Alexander Duyck
David S. Miller
parent
2909c3f79d
commit
bb2ac47bcf
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@ -46,7 +46,10 @@ static s32 igb_get_cfg_done_82575(struct e1000_hw *);
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static s32 igb_init_hw_82575(struct e1000_hw *);
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static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *);
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static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16 *);
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static s32 igb_read_phy_reg_82580(struct e1000_hw *, u32, u16 *);
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static s32 igb_write_phy_reg_82580(struct e1000_hw *, u32, u16);
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static s32 igb_reset_hw_82575(struct e1000_hw *);
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static s32 igb_reset_hw_82580(struct e1000_hw *);
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static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *, bool);
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static s32 igb_setup_copper_link_82575(struct e1000_hw *);
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static s32 igb_setup_serdes_link_82575(struct e1000_hw *);
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@ -62,6 +65,12 @@ static s32 igb_reset_init_script_82575(struct e1000_hw *);
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static s32 igb_read_mac_addr_82575(struct e1000_hw *);
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static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw);
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static const u16 e1000_82580_rxpbs_table[] =
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{ 36, 72, 144, 1, 2, 4, 8, 16,
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35, 70, 140 };
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#define E1000_82580_RXPBS_TABLE_SIZE \
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(sizeof(e1000_82580_rxpbs_table)/sizeof(u16))
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static s32 igb_get_invariants_82575(struct e1000_hw *hw)
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{
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struct e1000_phy_info *phy = &hw->phy;
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@ -88,6 +97,13 @@ static s32 igb_get_invariants_82575(struct e1000_hw *hw)
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case E1000_DEV_ID_82576_SERDES_QUAD:
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mac->type = e1000_82576;
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break;
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case E1000_DEV_ID_82580_COPPER:
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case E1000_DEV_ID_82580_FIBER:
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case E1000_DEV_ID_82580_SERDES:
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case E1000_DEV_ID_82580_SGMII:
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case E1000_DEV_ID_82580_COPPER_DUAL:
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mac->type = e1000_82580;
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break;
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default:
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return -E1000_ERR_MAC_INIT;
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break;
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@ -110,6 +126,7 @@ static s32 igb_get_invariants_82575(struct e1000_hw *hw)
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dev_spec->sgmii_active = true;
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ctrl_ext |= E1000_CTRL_I2C_ENA;
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break;
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case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
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case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
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hw->phy.media_type = e1000_media_type_internal_serdes;
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ctrl_ext |= E1000_CTRL_I2C_ENA;
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@ -121,12 +138,26 @@ static s32 igb_get_invariants_82575(struct e1000_hw *hw)
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wr32(E1000_CTRL_EXT, ctrl_ext);
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/*
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* if using i2c make certain the MDICNFG register is cleared to prevent
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* communications from being misrouted to the mdic registers
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*/
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if ((ctrl_ext & E1000_CTRL_I2C_ENA) && (hw->mac.type == e1000_82580))
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wr32(E1000_MDICNFG, 0);
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/* Set mta register count */
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mac->mta_reg_count = 128;
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/* Set rar entry count */
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mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
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if (mac->type == e1000_82576)
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mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
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if (mac->type == e1000_82580)
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mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
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/* reset */
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if (mac->type == e1000_82580)
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mac->ops.reset_hw = igb_reset_hw_82580;
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else
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mac->ops.reset_hw = igb_reset_hw_82575;
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/* Set if part includes ASF firmware */
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mac->asf_firmware_present = true;
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/* Set if manageability features are enabled. */
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@ -194,6 +225,10 @@ static s32 igb_get_invariants_82575(struct e1000_hw *hw)
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phy->ops.reset = igb_phy_hw_reset_sgmii_82575;
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phy->ops.read_reg = igb_read_phy_reg_sgmii_82575;
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phy->ops.write_reg = igb_write_phy_reg_sgmii_82575;
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} else if (hw->mac.type == e1000_82580) {
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phy->ops.reset = igb_phy_hw_reset;
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phy->ops.read_reg = igb_read_phy_reg_82580;
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phy->ops.write_reg = igb_write_phy_reg_82580;
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} else {
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phy->ops.reset = igb_phy_hw_reset;
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phy->ops.read_reg = igb_read_phy_reg_igp;
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@ -225,6 +260,12 @@ static s32 igb_get_invariants_82575(struct e1000_hw *hw)
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phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82575;
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phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state;
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break;
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case I82580_I_PHY_ID:
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phy->type = e1000_phy_82580;
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phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_82580;
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phy->ops.get_cable_length = igb_get_cable_length_82580;
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phy->ops.get_phy_info = igb_get_phy_info_82580;
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break;
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default:
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return -E1000_ERR_PHY;
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}
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@ -635,6 +676,10 @@ static s32 igb_get_cfg_done_82575(struct e1000_hw *hw)
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if (hw->bus.func == 1)
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mask = E1000_NVM_CFG_DONE_PORT_1;
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else if (hw->bus.func == E1000_FUNC_2)
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mask = E1000_NVM_CFG_DONE_PORT_2;
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else if (hw->bus.func == E1000_FUNC_3)
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mask = E1000_NVM_CFG_DONE_PORT_3;
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while (timeout) {
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if (rd32(E1000_EEMNGCTL) & mask)
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@ -754,6 +799,10 @@ void igb_shutdown_serdes_link_82575(struct e1000_hw *hw)
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if (hw->bus.func == E1000_FUNC_0)
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hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
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else if (hw->mac.type == e1000_82580)
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hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
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NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
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&eeprom_data);
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else if (hw->bus.func == E1000_FUNC_1)
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hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
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@ -918,6 +967,9 @@ static s32 igb_setup_copper_link_82575(struct e1000_hw *hw)
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goto out;
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if (igb_sgmii_active_82575(hw) && !hw->phy.reset_disable) {
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/* allow time for SFP cage time to power up phy */
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msleep(300);
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ret_val = hw->phy.ops.reset(hw);
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if (ret_val) {
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hw_dbg("Error resetting the PHY.\n");
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@ -931,6 +983,9 @@ static s32 igb_setup_copper_link_82575(struct e1000_hw *hw)
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case e1000_phy_igp_3:
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ret_val = igb_copper_link_setup_igp(hw);
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break;
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case e1000_phy_82580:
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ret_val = igb_copper_link_setup_82580(hw);
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break;
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default:
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ret_val = -E1000_ERR_PHY;
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break;
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@ -955,7 +1010,8 @@ out:
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**/
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static s32 igb_setup_serdes_link_82575(struct e1000_hw *hw)
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{
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u32 ctrl_reg, reg;
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u32 ctrl_ext, ctrl_reg, reg;
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bool pcs_autoneg;
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if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
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!igb_sgmii_active_82575(hw))
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@ -970,9 +1026,9 @@ static s32 igb_setup_serdes_link_82575(struct e1000_hw *hw)
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wr32(E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
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/* power on the sfp cage if present */
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reg = rd32(E1000_CTRL_EXT);
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reg &= ~E1000_CTRL_EXT_SDP3_DATA;
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wr32(E1000_CTRL_EXT, reg);
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ctrl_ext = rd32(E1000_CTRL_EXT);
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ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
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wr32(E1000_CTRL_EXT, ctrl_ext);
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ctrl_reg = rd32(E1000_CTRL);
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ctrl_reg |= E1000_CTRL_SLU;
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@ -989,15 +1045,31 @@ static s32 igb_setup_serdes_link_82575(struct e1000_hw *hw)
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reg = rd32(E1000_PCS_LCTL);
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if (igb_sgmii_active_82575(hw)) {
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/* allow time for SFP cage to power up phy */
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msleep(300);
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/* default pcs_autoneg to the same setting as mac autoneg */
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pcs_autoneg = hw->mac.autoneg;
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/* AN time out should be disabled for SGMII mode */
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switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
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case E1000_CTRL_EXT_LINK_MODE_SGMII:
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/* sgmii mode lets the phy handle forcing speed/duplex */
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pcs_autoneg = true;
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/* autoneg time out should be disabled for SGMII mode */
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reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
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} else {
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break;
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case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
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/* disable PCS autoneg and support parallel detect only */
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pcs_autoneg = false;
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default:
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/*
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* non-SGMII modes only supports a speed of 1000/Full for the
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* link so it is best to just force the MAC and let the pcs
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* link either autoneg or be forced to 1000/Full
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*/
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ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
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E1000_CTRL_FD | E1000_CTRL_FRCDPX;
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/* set speed of 1000/Full if speed/duplex is forced */
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reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
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break;
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}
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wr32(E1000_CTRL, ctrl_reg);
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@ -1008,7 +1080,6 @@ static s32 igb_setup_serdes_link_82575(struct e1000_hw *hw)
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* mode that will be compatible with older link partners and switches.
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* However, both are supported by the hardware and some drivers/tools.
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*/
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reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
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E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
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@ -1018,34 +1089,18 @@ static s32 igb_setup_serdes_link_82575(struct e1000_hw *hw)
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*/
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reg |= E1000_PCS_LCTL_FORCE_FCTRL;
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/*
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* we always set sgmii to autoneg since it is the phy that will be
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* forcing the link and the serdes is just a go-between
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*/
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if (hw->mac.autoneg || igb_sgmii_active_82575(hw)) {
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if (pcs_autoneg) {
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/* Set PCS register for autoneg */
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reg |= E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */
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E1000_PCS_LCTL_FDV_FULL | /* SerDes Full dplx */
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E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
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reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
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E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
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hw_dbg("Configuring Autoneg; PCS_LCTL = 0x%08X\n", reg);
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hw_dbg("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
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} else {
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/* Check for duplex first */
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if (hw->mac.forced_speed_duplex & E1000_ALL_FULL_DUPLEX)
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reg |= E1000_PCS_LCTL_FDV_FULL;
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/* Set PCS register for forced link */
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reg |= E1000_PCS_LCTL_FSD | /* Force Speed */
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E1000_PCS_LCTL_FORCE_LINK | /* Force Link */
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E1000_PCS_LCTL_FLV_LINK_UP; /* Force link value up */
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/* No need to check for 1000/full since the spec states that
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* it requires autoneg to be enabled */
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/* Now set speed */
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if (hw->mac.forced_speed_duplex & E1000_ALL_100_SPEED)
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reg |= E1000_PCS_LCTL_FSV_100;
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/* Force speed and force link */
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reg |= E1000_PCS_LCTL_FSD |
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E1000_PCS_LCTL_FORCE_LINK |
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E1000_PCS_LCTL_FLV_LINK_UP;
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hw_dbg("Configuring Forced Link; PCS_LCTL = 0x%08X\n", reg);
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hw_dbg("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
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}
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wr32(E1000_PCS_LCTL, reg);
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@ -1354,8 +1409,183 @@ void igb_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
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wr32(E1000_VT_CTL, vt_ctl);
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}
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/**
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* igb_read_phy_reg_82580 - Read 82580 MDI control register
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* @hw: pointer to the HW structure
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* @offset: register offset to be read
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* @data: pointer to the read data
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*
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* Reads the MDI control register in the PHY at offset and stores the
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* information read to data.
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**/
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static s32 igb_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
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{
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u32 mdicnfg = 0;
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s32 ret_val;
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ret_val = hw->phy.ops.acquire(hw);
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if (ret_val)
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goto out;
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/*
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* We config the phy address in MDICNFG register now. Same bits
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* as before. The values in MDIC can be written but will be
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* ignored. This allows us to call the old function after
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* configuring the PHY address in the new register
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*/
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mdicnfg = (hw->phy.addr << E1000_MDIC_PHY_SHIFT);
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wr32(E1000_MDICNFG, mdicnfg);
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ret_val = igb_read_phy_reg_mdic(hw, offset, data);
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hw->phy.ops.release(hw);
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out:
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return ret_val;
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}
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/**
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* igb_write_phy_reg_82580 - Write 82580 MDI control register
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* @hw: pointer to the HW structure
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* @offset: register offset to write to
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* @data: data to write to register at offset
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*
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* Writes data to MDI control register in the PHY at offset.
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**/
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static s32 igb_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
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{
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u32 mdicnfg = 0;
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s32 ret_val;
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ret_val = hw->phy.ops.acquire(hw);
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if (ret_val)
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goto out;
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/*
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* We config the phy address in MDICNFG register now. Same bits
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* as before. The values in MDIC can be written but will be
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* ignored. This allows us to call the old function after
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* configuring the PHY address in the new register
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*/
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mdicnfg = (hw->phy.addr << E1000_MDIC_PHY_SHIFT);
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wr32(E1000_MDICNFG, mdicnfg);
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ret_val = igb_write_phy_reg_mdic(hw, offset, data);
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hw->phy.ops.release(hw);
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out:
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return ret_val;
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}
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/**
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* igb_reset_hw_82580 - Reset hardware
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* @hw: pointer to the HW structure
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*
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* This resets function or entire device (all ports, etc.)
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* to a known state.
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**/
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static s32 igb_reset_hw_82580(struct e1000_hw *hw)
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{
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s32 ret_val = 0;
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/* BH SW mailbox bit in SW_FW_SYNC */
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u16 swmbsw_mask = E1000_SW_SYNCH_MB;
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u32 ctrl, icr;
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bool global_device_reset = hw->dev_spec._82575.global_device_reset;
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hw->dev_spec._82575.global_device_reset = false;
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/* Get current control state. */
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ctrl = rd32(E1000_CTRL);
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/*
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* Prevent the PCI-E bus from sticking if there is no TLP connection
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* on the last TLP read/write transaction when MAC is reset.
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*/
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ret_val = igb_disable_pcie_master(hw);
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if (ret_val)
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hw_dbg("PCI-E Master disable polling has failed.\n");
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hw_dbg("Masking off all interrupts\n");
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wr32(E1000_IMC, 0xffffffff);
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wr32(E1000_RCTL, 0);
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wr32(E1000_TCTL, E1000_TCTL_PSP);
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wrfl();
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msleep(10);
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/* Determine whether or not a global dev reset is requested */
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if (global_device_reset &&
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igb_acquire_swfw_sync_82575(hw, swmbsw_mask))
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global_device_reset = false;
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if (global_device_reset &&
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!(rd32(E1000_STATUS) & E1000_STAT_DEV_RST_SET))
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ctrl |= E1000_CTRL_DEV_RST;
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else
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ctrl |= E1000_CTRL_RST;
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wr32(E1000_CTRL, ctrl);
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/* Add delay to insure DEV_RST has time to complete */
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if (global_device_reset)
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msleep(5);
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ret_val = igb_get_auto_rd_done(hw);
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if (ret_val) {
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/*
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* When auto config read does not complete, do not
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* return with an error. This can happen in situations
|
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* where there is no eeprom and prevents getting link.
|
||||
*/
|
||||
hw_dbg("Auto Read Done did not complete\n");
|
||||
}
|
||||
|
||||
/* If EEPROM is not present, run manual init scripts */
|
||||
if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0)
|
||||
igb_reset_init_script_82575(hw);
|
||||
|
||||
/* clear global device reset status bit */
|
||||
wr32(E1000_STATUS, E1000_STAT_DEV_RST_SET);
|
||||
|
||||
/* Clear any pending interrupt events. */
|
||||
wr32(E1000_IMC, 0xffffffff);
|
||||
icr = rd32(E1000_ICR);
|
||||
|
||||
/* Install any alternate MAC address into RAR0 */
|
||||
ret_val = igb_check_alt_mac_addr(hw);
|
||||
|
||||
/* Release semaphore */
|
||||
if (global_device_reset)
|
||||
igb_release_swfw_sync_82575(hw, swmbsw_mask);
|
||||
|
||||
return ret_val;
|
||||
}
|
||||
|
||||
/**
|
||||
* igb_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual RX PBA size
|
||||
* @data: data received by reading RXPBS register
|
||||
*
|
||||
* The 82580 uses a table based approach for packet buffer allocation sizes.
|
||||
* This function converts the retrieved value into the correct table value
|
||||
* 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
|
||||
* 0x0 36 72 144 1 2 4 8 16
|
||||
* 0x8 35 70 140 rsv rsv rsv rsv rsv
|
||||
*/
|
||||
u16 igb_rxpbs_adjust_82580(u32 data)
|
||||
{
|
||||
u16 ret_val = 0;
|
||||
|
||||
if (data < E1000_82580_RXPBS_TABLE_SIZE)
|
||||
ret_val = e1000_82580_rxpbs_table[data];
|
||||
|
||||
return ret_val;
|
||||
}
|
||||
|
||||
static struct e1000_mac_operations e1000_mac_ops_82575 = {
|
||||
.reset_hw = igb_reset_hw_82575,
|
||||
.init_hw = igb_init_hw_82575,
|
||||
.check_for_link = igb_check_for_link_82575,
|
||||
.rar_set = igb_rar_set,
|
||||
|
|
|
|||
|
|
@ -38,6 +38,11 @@ extern void igb_rx_fifo_flush_82575(struct e1000_hw *hw);
|
|||
|
||||
#define E1000_RAR_ENTRIES_82575 16
|
||||
#define E1000_RAR_ENTRIES_82576 24
|
||||
#define E1000_RAR_ENTRIES_82580 24
|
||||
|
||||
#define E1000_SW_SYNCH_MB 0x00000100
|
||||
#define E1000_STAT_DEV_RST_SET 0x00100000
|
||||
#define E1000_CTRL_DEV_RST 0x20000000
|
||||
|
||||
/* SRRCTL bit definitions */
|
||||
#define E1000_SRRCTL_BSIZEPKT_SHIFT 10 /* Shift _right_ */
|
||||
|
|
@ -232,5 +237,6 @@ struct e1000_adv_tx_context_desc {
|
|||
#define E1000_RXPBS_SIZE_MASK_82576 0x0000007F
|
||||
void igb_vmdq_set_loopback_pf(struct e1000_hw *, bool);
|
||||
void igb_vmdq_set_replication_pf(struct e1000_hw *, bool);
|
||||
u16 igb_rxpbs_adjust_82580(u32 data);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -49,6 +49,7 @@
|
|||
#define E1000_CTRL_EXT_PFRSTD 0x00004000
|
||||
#define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
|
||||
#define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000
|
||||
#define E1000_CTRL_EXT_LINK_MODE_1000BASE_KX 0x00400000
|
||||
#define E1000_CTRL_EXT_LINK_MODE_SGMII 0x00800000
|
||||
#define E1000_CTRL_EXT_EIAME 0x01000000
|
||||
#define E1000_CTRL_EXT_IRCA 0x00000001
|
||||
|
|
@ -557,8 +558,12 @@
|
|||
#define NVM_ALT_MAC_ADDR_PTR 0x0037
|
||||
#define NVM_CHECKSUM_REG 0x003F
|
||||
|
||||
#define E1000_NVM_CFG_DONE_PORT_0 0x40000 /* MNG config cycle done */
|
||||
#define E1000_NVM_CFG_DONE_PORT_1 0x80000 /* ...for second port */
|
||||
#define E1000_NVM_CFG_DONE_PORT_0 0x040000 /* MNG config cycle done */
|
||||
#define E1000_NVM_CFG_DONE_PORT_1 0x080000 /* ...for second port */
|
||||
#define E1000_NVM_CFG_DONE_PORT_2 0x100000 /* ...for third port */
|
||||
#define E1000_NVM_CFG_DONE_PORT_3 0x200000 /* ...for fourth port */
|
||||
|
||||
#define NVM_82580_LAN_FUNC_OFFSET(a) (a ? (0x40 + (0x40 * a)) : 0)
|
||||
|
||||
/* Mask bits for fields in Word 0x0f of the NVM */
|
||||
#define NVM_WORD0F_PAUSE_MASK 0x3000
|
||||
|
|
@ -625,6 +630,7 @@
|
|||
*/
|
||||
#define M88E1111_I_PHY_ID 0x01410CC0
|
||||
#define IGP03E1000_E_PHY_ID 0x02A80390
|
||||
#define I82580_I_PHY_ID 0x015403A0
|
||||
#define M88_VENDOR 0x0141
|
||||
|
||||
/* M88E1000 Specific Registers */
|
||||
|
|
|
|||
|
|
@ -47,19 +47,30 @@ struct e1000_hw;
|
|||
#define E1000_DEV_ID_82575EB_COPPER 0x10A7
|
||||
#define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9
|
||||
#define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6
|
||||
#define E1000_DEV_ID_82580_COPPER 0x150E
|
||||
#define E1000_DEV_ID_82580_FIBER 0x150F
|
||||
#define E1000_DEV_ID_82580_SERDES 0x1510
|
||||
#define E1000_DEV_ID_82580_SGMII 0x1511
|
||||
#define E1000_DEV_ID_82580_COPPER_DUAL 0x1516
|
||||
|
||||
#define E1000_REVISION_2 2
|
||||
#define E1000_REVISION_4 4
|
||||
|
||||
#define E1000_FUNC_0 0
|
||||
#define E1000_FUNC_1 1
|
||||
#define E1000_FUNC_2 2
|
||||
#define E1000_FUNC_3 3
|
||||
|
||||
#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0
|
||||
#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3
|
||||
#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2 6
|
||||
#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3 9
|
||||
|
||||
enum e1000_mac_type {
|
||||
e1000_undefined = 0,
|
||||
e1000_82575,
|
||||
e1000_82576,
|
||||
e1000_82580,
|
||||
e1000_num_macs /* List is 1-based, so subtract 1 for true count. */
|
||||
};
|
||||
|
||||
|
|
@ -290,6 +301,7 @@ struct e1000_mac_operations {
|
|||
|
||||
struct e1000_phy_operations {
|
||||
s32 (*acquire)(struct e1000_hw *);
|
||||
s32 (*check_polarity)(struct e1000_hw *);
|
||||
s32 (*check_reset_block)(struct e1000_hw *);
|
||||
s32 (*force_speed_duplex)(struct e1000_hw *);
|
||||
s32 (*get_cfg_done)(struct e1000_hw *hw);
|
||||
|
|
@ -466,6 +478,7 @@ struct e1000_mbx_info {
|
|||
|
||||
struct e1000_dev_spec_82575 {
|
||||
bool sgmii_active;
|
||||
bool global_device_reset;
|
||||
};
|
||||
|
||||
struct e1000_hw {
|
||||
|
|
|
|||
|
|
@ -136,7 +136,7 @@ out:
|
|||
* Reads the MDI control regsiter in the PHY at offset and stores the
|
||||
* information read to data.
|
||||
**/
|
||||
static s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
|
||||
s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
|
||||
{
|
||||
struct e1000_phy_info *phy = &hw->phy;
|
||||
u32 i, mdic = 0;
|
||||
|
|
@ -194,7 +194,7 @@ out:
|
|||
*
|
||||
* Writes data to MDI control register in the PHY at offset.
|
||||
**/
|
||||
static s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
|
||||
s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
|
||||
{
|
||||
struct e1000_phy_info *phy = &hw->phy;
|
||||
u32 i, mdic = 0;
|
||||
|
|
@ -1947,7 +1947,7 @@ s32 igb_phy_init_script_igp3(struct e1000_hw *hw)
|
|||
*
|
||||
* Polarity is determined based on the PHY specific status register.
|
||||
**/
|
||||
s32 igb_check_polarity_82580(struct e1000_hw *hw)
|
||||
static s32 igb_check_polarity_82580(struct e1000_hw *hw)
|
||||
{
|
||||
struct e1000_phy_info *phy = &hw->phy;
|
||||
s32 ret_val;
|
||||
|
|
|
|||
|
|
@ -61,10 +61,11 @@ s32 igb_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data);
|
|||
s32 igb_phy_has_link(struct e1000_hw *hw, u32 iterations,
|
||||
u32 usec_interval, bool *success);
|
||||
s32 igb_phy_init_script_igp3(struct e1000_hw *hw);
|
||||
s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data);
|
||||
s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data);
|
||||
s32 igb_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data);
|
||||
s32 igb_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data);
|
||||
s32 igb_copper_link_setup_82580(struct e1000_hw *hw);
|
||||
s32 igb_check_polarity_82580(struct e1000_hw *hw);
|
||||
s32 igb_get_phy_info_82580(struct e1000_hw *hw);
|
||||
s32 igb_phy_force_speed_duplex_82580(struct e1000_hw *hw);
|
||||
s32 igb_get_cable_length_82580(struct e1000_hw *hw);
|
||||
|
|
|
|||
|
|
@ -34,6 +34,7 @@
|
|||
#define E1000_EERD 0x00014 /* EEPROM Read - RW */
|
||||
#define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */
|
||||
#define E1000_MDIC 0x00020 /* MDI Control - RW */
|
||||
#define E1000_MDICNFG 0x00E04 /* MDI Config - RW */
|
||||
#define E1000_SCTL 0x00024 /* SerDes Control - RW */
|
||||
#define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */
|
||||
#define E1000_FCAH 0x0002C /* Flow Control Address High -RW */
|
||||
|
|
|
|||
Loading…
Reference in New Issue