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drm/nouveau/bus: convert to new-style nvkm_subdev 

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs 2015-08-20 14:54:20 +10:00
parent 46484438ab
commit bb23f9d791
22 changed files with 246 additions and 318 deletions
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42
drivers/gpu/drm/nouveau/include/nvkm/subdev/bus.h
View File

@ -2,49 +2,23 @@
#define __NVKM_BUS_H__
#include <core/subdev.h>
struct nvkm_bus_intr {
u32 stat;
u32 unit;
};
struct nvkm_bus {
const struct nvkm_bus_func *func;
struct nvkm_subdev subdev;
int (*hwsq_exec)(struct nvkm_bus *, u32 *, u32);
u32 hwsq_size;
};
static inline struct nvkm_bus *
nvkm_bus(void *obj)
{
return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_BUS);
}
#define nvkm_bus_create(p, e, o, d) \
nvkm_subdev_create_((p), (e), (o), 0, "PBUS", "master", \
sizeof(**d), (void **)d)
#define nvkm_bus_destroy(p) \
nvkm_subdev_destroy(&(p)->subdev)
#define nvkm_bus_init(p) \
nvkm_subdev_init_old(&(p)->subdev)
#define nvkm_bus_fini(p, s) \
nvkm_subdev_fini_old(&(p)->subdev, (s))
#define _nvkm_bus_dtor _nvkm_subdev_dtor
#define _nvkm_bus_init _nvkm_subdev_init
#define _nvkm_bus_fini _nvkm_subdev_fini
extern struct nvkm_oclass *nv04_bus_oclass;
extern struct nvkm_oclass *nv31_bus_oclass;
extern struct nvkm_oclass *nv50_bus_oclass;
extern struct nvkm_oclass *g94_bus_oclass;
extern struct nvkm_oclass *gf100_bus_oclass;
/* interface to sequencer */
struct nvkm_hwsq;
int nvkm_hwsq_init(struct nvkm_bus *, struct nvkm_hwsq **);
int nvkm_hwsq_init(struct nvkm_subdev *, struct nvkm_hwsq **);
int nvkm_hwsq_fini(struct nvkm_hwsq **, bool exec);
void nvkm_hwsq_wr32(struct nvkm_hwsq *, u32 addr, u32 data);
void nvkm_hwsq_setf(struct nvkm_hwsq *, u8 flag, int data);
void nvkm_hwsq_wait(struct nvkm_hwsq *, u8 flag, u8 data);
void nvkm_hwsq_nsec(struct nvkm_hwsq *, u32 nsec);
int nv04_bus_new(struct nvkm_device *, int, struct nvkm_bus **);
int nv31_bus_new(struct nvkm_device *, int, struct nvkm_bus **);
int nv50_bus_new(struct nvkm_device *, int, struct nvkm_bus **);
int g94_bus_new(struct nvkm_device *, int, struct nvkm_bus **);
int gf100_bus_new(struct nvkm_device *, int, struct nvkm_bus **);
#endif

138
drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
View File

@ -77,7 +77,7 @@ static const struct nvkm_device_chip
nv4_chipset = {
.name = "NV04",
.bios = nvkm_bios_new,
// .bus = nv04_bus_new,
.bus = nv04_bus_new,
// .clk = nv04_clk_new,
// .devinit = nv04_devinit_new,
// .fb = nv04_fb_new,
@ -97,7 +97,7 @@ static const struct nvkm_device_chip
nv5_chipset = {
.name = "NV05",
.bios = nvkm_bios_new,
// .bus = nv04_bus_new,
.bus = nv04_bus_new,
// .clk = nv04_clk_new,
// .devinit = nv05_devinit_new,
// .fb = nv04_fb_new,
@ -117,7 +117,7 @@ static const struct nvkm_device_chip
nv10_chipset = {
.name = "NV10",
.bios = nvkm_bios_new,
// .bus = nv04_bus_new,
.bus = nv04_bus_new,
// .clk = nv04_clk_new,
// .devinit = nv10_devinit_new,
// .fb = nv10_fb_new,
@ -136,7 +136,7 @@ static const struct nvkm_device_chip
nv11_chipset = {
.name = "NV11",
.bios = nvkm_bios_new,
// .bus = nv04_bus_new,
.bus = nv04_bus_new,
// .clk = nv04_clk_new,
// .devinit = nv10_devinit_new,
// .fb = nv10_fb_new,
@ -157,7 +157,7 @@ static const struct nvkm_device_chip
nv15_chipset = {
.name = "NV15",
.bios = nvkm_bios_new,
// .bus = nv04_bus_new,
.bus = nv04_bus_new,
// .clk = nv04_clk_new,
// .devinit = nv10_devinit_new,
// .fb = nv10_fb_new,
@ -178,7 +178,7 @@ static const struct nvkm_device_chip
nv17_chipset = {
.name = "NV17",
.bios = nvkm_bios_new,
// .bus = nv04_bus_new,
.bus = nv04_bus_new,
// .clk = nv04_clk_new,
// .devinit = nv10_devinit_new,
// .fb = nv10_fb_new,
@ -199,7 +199,7 @@ static const struct nvkm_device_chip
nv18_chipset = {
.name = "NV18",
.bios = nvkm_bios_new,
// .bus = nv04_bus_new,
.bus = nv04_bus_new,
// .clk = nv04_clk_new,
// .devinit = nv10_devinit_new,
// .fb = nv10_fb_new,
@ -220,7 +220,7 @@ static const struct nvkm_device_chip
nv1a_chipset = {
.name = "nForce",
.bios = nvkm_bios_new,
// .bus = nv04_bus_new,
.bus = nv04_bus_new,
// .clk = nv04_clk_new,
// .devinit = nv1a_devinit_new,
// .fb = nv1a_fb_new,
@ -241,7 +241,7 @@ static const struct nvkm_device_chip
nv1f_chipset = {
.name = "nForce2",
.bios = nvkm_bios_new,
// .bus = nv04_bus_new,
.bus = nv04_bus_new,
// .clk = nv04_clk_new,
// .devinit = nv1a_devinit_new,
// .fb = nv1a_fb_new,
@ -262,7 +262,7 @@ static const struct nvkm_device_chip
nv20_chipset = {
.name = "NV20",
.bios = nvkm_bios_new,
// .bus = nv04_bus_new,
.bus = nv04_bus_new,
// .clk = nv04_clk_new,
// .devinit = nv20_devinit_new,
// .fb = nv20_fb_new,
@ -283,7 +283,7 @@ static const struct nvkm_device_chip
nv25_chipset = {
.name = "NV25",
.bios = nvkm_bios_new,
// .bus = nv04_bus_new,
.bus = nv04_bus_new,
// .clk = nv04_clk_new,
// .devinit = nv20_devinit_new,
// .fb = nv25_fb_new,
@ -304,7 +304,7 @@ static const struct nvkm_device_chip
nv28_chipset = {
.name = "NV28",
.bios = nvkm_bios_new,
// .bus = nv04_bus_new,
.bus = nv04_bus_new,
// .clk = nv04_clk_new,
// .devinit = nv20_devinit_new,
// .fb = nv25_fb_new,
@ -325,7 +325,7 @@ static const struct nvkm_device_chip
nv2a_chipset = {
.name = "NV2A",
.bios = nvkm_bios_new,
// .bus = nv04_bus_new,
.bus = nv04_bus_new,
// .clk = nv04_clk_new,
// .devinit = nv20_devinit_new,
// .fb = nv25_fb_new,
@ -346,7 +346,7 @@ static const struct nvkm_device_chip
nv30_chipset = {
.name = "NV30",
.bios = nvkm_bios_new,
// .bus = nv04_bus_new,
.bus = nv04_bus_new,
// .clk = nv04_clk_new,
// .devinit = nv20_devinit_new,
// .fb = nv30_fb_new,
@ -367,7 +367,7 @@ static const struct nvkm_device_chip
nv31_chipset = {
.name = "NV31",
.bios = nvkm_bios_new,
// .bus = nv31_bus_new,
.bus = nv31_bus_new,
// .clk = nv04_clk_new,
// .devinit = nv20_devinit_new,
// .fb = nv30_fb_new,
@ -389,7 +389,7 @@ static const struct nvkm_device_chip
nv34_chipset = {
.name = "NV34",
.bios = nvkm_bios_new,
// .bus = nv31_bus_new,
.bus = nv31_bus_new,
// .clk = nv04_clk_new,
// .devinit = nv10_devinit_new,
// .fb = nv10_fb_new,
@ -411,7 +411,7 @@ static const struct nvkm_device_chip
nv35_chipset = {
.name = "NV35",
.bios = nvkm_bios_new,
// .bus = nv04_bus_new,
.bus = nv04_bus_new,
// .clk = nv04_clk_new,
// .devinit = nv20_devinit_new,
// .fb = nv35_fb_new,
@ -432,7 +432,7 @@ static const struct nvkm_device_chip
nv36_chipset = {
.name = "NV36",
.bios = nvkm_bios_new,
// .bus = nv31_bus_new,
.bus = nv31_bus_new,
// .clk = nv04_clk_new,
// .devinit = nv20_devinit_new,
// .fb = nv36_fb_new,
@ -454,7 +454,7 @@ static const struct nvkm_device_chip
nv40_chipset = {
.name = "NV40",
.bios = nvkm_bios_new,
// .bus = nv31_bus_new,
.bus = nv31_bus_new,
// .clk = nv40_clk_new,
// .devinit = nv1a_devinit_new,
// .fb = nv40_fb_new,
@ -479,7 +479,7 @@ static const struct nvkm_device_chip
nv41_chipset = {
.name = "NV41",
.bios = nvkm_bios_new,
// .bus = nv31_bus_new,
.bus = nv31_bus_new,
// .clk = nv40_clk_new,
// .devinit = nv1a_devinit_new,
// .fb = nv41_fb_new,
@ -504,7 +504,7 @@ static const struct nvkm_device_chip
nv42_chipset = {
.name = "NV42",
.bios = nvkm_bios_new,
// .bus = nv31_bus_new,
.bus = nv31_bus_new,
// .clk = nv40_clk_new,
// .devinit = nv1a_devinit_new,
// .fb = nv41_fb_new,
@ -529,7 +529,7 @@ static const struct nvkm_device_chip
nv43_chipset = {
.name = "NV43",
.bios = nvkm_bios_new,
// .bus = nv31_bus_new,
.bus = nv31_bus_new,
// .clk = nv40_clk_new,
// .devinit = nv1a_devinit_new,
// .fb = nv41_fb_new,
@ -554,7 +554,7 @@ static const struct nvkm_device_chip
nv44_chipset = {
.name = "NV44",
.bios = nvkm_bios_new,
// .bus = nv31_bus_new,
.bus = nv31_bus_new,
// .clk = nv40_clk_new,
// .devinit = nv1a_devinit_new,
// .fb = nv44_fb_new,
@ -579,7 +579,7 @@ static const struct nvkm_device_chip
nv45_chipset = {
.name = "NV45",
.bios = nvkm_bios_new,
// .bus = nv31_bus_new,
.bus = nv31_bus_new,
// .clk = nv40_clk_new,
// .devinit = nv1a_devinit_new,
// .fb = nv40_fb_new,
@ -604,7 +604,7 @@ static const struct nvkm_device_chip
nv46_chipset = {
.name = "G72",
.bios = nvkm_bios_new,
// .bus = nv31_bus_new,
.bus = nv31_bus_new,
// .clk = nv40_clk_new,
// .devinit = nv1a_devinit_new,
// .fb = nv46_fb_new,
@ -629,7 +629,7 @@ static const struct nvkm_device_chip
nv47_chipset = {
.name = "G70",
.bios = nvkm_bios_new,
// .bus = nv31_bus_new,
.bus = nv31_bus_new,
// .clk = nv40_clk_new,
// .devinit = nv1a_devinit_new,
// .fb = nv47_fb_new,
@ -654,7 +654,7 @@ static const struct nvkm_device_chip
nv49_chipset = {
.name = "G71",
.bios = nvkm_bios_new,
// .bus = nv31_bus_new,
.bus = nv31_bus_new,
// .clk = nv40_clk_new,
// .devinit = nv1a_devinit_new,
// .fb = nv49_fb_new,
@ -679,7 +679,7 @@ static const struct nvkm_device_chip
nv4a_chipset = {
.name = "NV44A",
.bios = nvkm_bios_new,
// .bus = nv31_bus_new,
.bus = nv31_bus_new,
// .clk = nv40_clk_new,
// .devinit = nv1a_devinit_new,
// .fb = nv44_fb_new,
@ -704,7 +704,7 @@ static const struct nvkm_device_chip
nv4b_chipset = {
.name = "G73",
.bios = nvkm_bios_new,
// .bus = nv31_bus_new,
.bus = nv31_bus_new,
// .clk = nv40_clk_new,
// .devinit = nv1a_devinit_new,
// .fb = nv49_fb_new,
@ -729,7 +729,7 @@ static const struct nvkm_device_chip
nv4c_chipset = {
.name = "C61",
.bios = nvkm_bios_new,
// .bus = nv31_bus_new,
.bus = nv31_bus_new,
// .clk = nv40_clk_new,
// .devinit = nv1a_devinit_new,
// .fb = nv46_fb_new,
@ -754,7 +754,7 @@ static const struct nvkm_device_chip
nv4e_chipset = {
.name = "C51",
.bios = nvkm_bios_new,
// .bus = nv31_bus_new,
.bus = nv31_bus_new,
// .clk = nv40_clk_new,
// .devinit = nv1a_devinit_new,
// .fb = nv4e_fb_new,
@ -780,7 +780,7 @@ nv50_chipset = {
.name = "G80",
.bar = nv50_bar_new,
.bios = nvkm_bios_new,
// .bus = nv50_bus_new,
.bus = nv50_bus_new,
// .clk = nv50_clk_new,
// .devinit = nv50_devinit_new,
// .fb = nv50_fb_new,
@ -807,7 +807,7 @@ static const struct nvkm_device_chip
nv63_chipset = {
.name = "C73",
.bios = nvkm_bios_new,
// .bus = nv31_bus_new,
.bus = nv31_bus_new,
// .clk = nv40_clk_new,
// .devinit = nv1a_devinit_new,
// .fb = nv46_fb_new,
@ -832,7 +832,7 @@ static const struct nvkm_device_chip
nv67_chipset = {
.name = "C67",
.bios = nvkm_bios_new,
// .bus = nv31_bus_new,
.bus = nv31_bus_new,
// .clk = nv40_clk_new,
// .devinit = nv1a_devinit_new,
// .fb = nv46_fb_new,
@ -857,7 +857,7 @@ static const struct nvkm_device_chip
nv68_chipset = {
.name = "C68",
.bios = nvkm_bios_new,
// .bus = nv31_bus_new,
.bus = nv31_bus_new,
// .clk = nv40_clk_new,
// .devinit = nv1a_devinit_new,
// .fb = nv46_fb_new,
@ -883,7 +883,7 @@ nv84_chipset = {
.name = "G84",
.bar = g84_bar_new,
.bios = nvkm_bios_new,
// .bus = nv50_bus_new,
.bus = nv50_bus_new,
// .clk = g84_clk_new,
// .devinit = g84_devinit_new,
// .fb = g84_fb_new,
@ -914,7 +914,7 @@ nv86_chipset = {
.name = "G86",
.bar = g84_bar_new,
.bios = nvkm_bios_new,
// .bus = nv50_bus_new,
.bus = nv50_bus_new,
// .clk = g84_clk_new,
// .devinit = g84_devinit_new,
// .fb = g84_fb_new,
@ -945,7 +945,7 @@ nv92_chipset = {
.name = "G92",
.bar = g84_bar_new,
.bios = nvkm_bios_new,
// .bus = nv50_bus_new,
.bus = nv50_bus_new,
// .clk = g84_clk_new,
// .devinit = g84_devinit_new,
// .fb = g84_fb_new,
@ -976,7 +976,7 @@ nv94_chipset = {
.name = "G94",
.bar = g84_bar_new,
.bios = nvkm_bios_new,
// .bus = g94_bus_new,
.bus = g94_bus_new,
// .clk = g84_clk_new,
// .devinit = g84_devinit_new,
// .fb = g84_fb_new,
@ -1014,7 +1014,7 @@ nv96_chipset = {
// .mxm = nv50_mxm_new,
// .devinit = g84_devinit_new,
// .mc = g94_mc_new,
// .bus = g94_bus_new,
.bus = g94_bus_new,
// .timer = nv04_timer_new,
// .fb = g84_fb_new,
// .imem = nv50_instmem_new,
@ -1045,7 +1045,7 @@ nv98_chipset = {
// .mxm = nv50_mxm_new,
// .devinit = g98_devinit_new,
// .mc = g98_mc_new,
// .bus = g94_bus_new,
.bus = g94_bus_new,
// .timer = nv04_timer_new,
// .fb = g84_fb_new,
// .imem = nv50_instmem_new,
@ -1069,7 +1069,7 @@ nva0_chipset = {
.name = "GT200",
.bar = g84_bar_new,
.bios = nvkm_bios_new,
// .bus = g94_bus_new,
.bus = g94_bus_new,
// .clk = g84_clk_new,
// .devinit = g84_devinit_new,
// .fb = g84_fb_new,
@ -1100,7 +1100,7 @@ nva3_chipset = {
.name = "GT215",
.bar = g84_bar_new,
.bios = nvkm_bios_new,
// .bus = g94_bus_new,
.bus = g94_bus_new,
// .clk = gt215_clk_new,
// .devinit = gt215_devinit_new,
// .fb = gt215_fb_new,
@ -1133,7 +1133,7 @@ nva5_chipset = {
.name = "GT216",
.bar = g84_bar_new,
.bios = nvkm_bios_new,
// .bus = g94_bus_new,
.bus = g94_bus_new,
// .clk = gt215_clk_new,
// .devinit = gt215_devinit_new,
// .fb = gt215_fb_new,
@ -1165,7 +1165,7 @@ nva8_chipset = {
.name = "GT218",
.bar = g84_bar_new,
.bios = nvkm_bios_new,
// .bus = g94_bus_new,
.bus = g94_bus_new,
// .clk = gt215_clk_new,
// .devinit = gt215_devinit_new,
// .fb = gt215_fb_new,
@ -1197,7 +1197,7 @@ nvaa_chipset = {
.name = "MCP77/MCP78",
.bar = g84_bar_new,
.bios = nvkm_bios_new,
// .bus = g94_bus_new,
.bus = g94_bus_new,
// .clk = mcp77_clk_new,
// .devinit = g98_devinit_new,
// .fb = mcp77_fb_new,
@ -1228,7 +1228,7 @@ nvac_chipset = {
.name = "MCP79/MCP7A",
.bar = g84_bar_new,
.bios = nvkm_bios_new,
// .bus = g94_bus_new,
.bus = g94_bus_new,
// .clk = mcp77_clk_new,
// .devinit = g98_devinit_new,
// .fb = mcp77_fb_new,
@ -1259,7 +1259,7 @@ nvaf_chipset = {
.name = "MCP89",
.bar = g84_bar_new,
.bios = nvkm_bios_new,
// .bus = g94_bus_new,
.bus = g94_bus_new,
// .clk = gt215_clk_new,
// .devinit = mcp89_devinit_new,
// .fb = mcp89_fb_new,
@ -1291,7 +1291,7 @@ nvc0_chipset = {
.name = "GF100",
.bar = gf100_bar_new,
.bios = nvkm_bios_new,
// .bus = gf100_bus_new,
.bus = gf100_bus_new,
// .clk = gf100_clk_new,
// .devinit = gf100_devinit_new,
// .fb = gf100_fb_new,
@ -1326,7 +1326,7 @@ nvc1_chipset = {
.name = "GF108",
.bar = gf100_bar_new,
.bios = nvkm_bios_new,
// .bus = gf100_bus_new,
.bus = gf100_bus_new,
// .clk = gf100_clk_new,
// .devinit = gf100_devinit_new,
// .fb = gf100_fb_new,
@ -1360,7 +1360,7 @@ nvc3_chipset = {
.name = "GF106",
.bar = gf100_bar_new,
.bios = nvkm_bios_new,
// .bus = gf100_bus_new,
.bus = gf100_bus_new,
// .clk = gf100_clk_new,
// .devinit = gf100_devinit_new,
// .fb = gf100_fb_new,
@ -1394,7 +1394,7 @@ nvc4_chipset = {
.name = "GF104",
.bar = gf100_bar_new,
.bios = nvkm_bios_new,
// .bus = gf100_bus_new,
.bus = gf100_bus_new,
// .clk = gf100_clk_new,
// .devinit = gf100_devinit_new,
// .fb = gf100_fb_new,
@ -1429,7 +1429,7 @@ nvc8_chipset = {
.name = "GF110",
.bar = gf100_bar_new,
.bios = nvkm_bios_new,
// .bus = gf100_bus_new,
.bus = gf100_bus_new,
// .clk = gf100_clk_new,
// .devinit = gf100_devinit_new,
// .fb = gf100_fb_new,
@ -1464,7 +1464,7 @@ nvce_chipset = {
.name = "GF114",
.bar = gf100_bar_new,
.bios = nvkm_bios_new,
// .bus = gf100_bus_new,
.bus = gf100_bus_new,
// .clk = gf100_clk_new,
// .devinit = gf100_devinit_new,
// .fb = gf100_fb_new,
@ -1499,7 +1499,7 @@ nvcf_chipset = {
.name = "GF116",
.bar = gf100_bar_new,
.bios = nvkm_bios_new,
// .bus = gf100_bus_new,
.bus = gf100_bus_new,
// .clk = gf100_clk_new,
// .devinit = gf100_devinit_new,
// .fb = gf100_fb_new,
@ -1533,7 +1533,7 @@ nvd7_chipset = {
.name = "GF117",
.bar = gf100_bar_new,
.bios = nvkm_bios_new,
// .bus = gf100_bus_new,
.bus = gf100_bus_new,
// .clk = gf100_clk_new,
// .devinit = gf100_devinit_new,
// .fb = gf100_fb_new,
@ -1565,7 +1565,7 @@ nvd9_chipset = {
.name = "GF119",
.bar = gf100_bar_new,
.bios = nvkm_bios_new,
// .bus = gf100_bus_new,
.bus = gf100_bus_new,
// .clk = gf100_clk_new,
// .devinit = gf100_devinit_new,
// .fb = gf100_fb_new,
@ -1599,7 +1599,7 @@ nve4_chipset = {
.name = "GK104",
.bar = gf100_bar_new,
.bios = nvkm_bios_new,
// .bus = gf100_bus_new,
.bus = gf100_bus_new,
// .clk = gk104_clk_new,
// .devinit = gf100_devinit_new,
// .fb = gk104_fb_new,
@ -1635,7 +1635,7 @@ nve6_chipset = {
.name = "GK106",
.bar = gf100_bar_new,
.bios = nvkm_bios_new,
// .bus = gf100_bus_new,
.bus = gf100_bus_new,
// .clk = gk104_clk_new,
// .devinit = gf100_devinit_new,
// .fb = gk104_fb_new,
@ -1671,7 +1671,7 @@ nve7_chipset = {
.name = "GK107",
.bar = gf100_bar_new,
.bios = nvkm_bios_new,
// .bus = gf100_bus_new,
.bus = gf100_bus_new,
// .clk = gk104_clk_new,
// .devinit = gf100_devinit_new,
// .fb = gk104_fb_new,
@ -1706,7 +1706,7 @@ static const struct nvkm_device_chip
nvea_chipset = {
.name = "GK20A",
.bar = gk20a_bar_new,
// .bus = gf100_bus_new,
.bus = gf100_bus_new,
// .clk = gk20a_clk_new,
// .fb = gk20a_fb_new,
// .fuse = gf100_fuse_new,
@ -1731,7 +1731,7 @@ nvf0_chipset = {
.name = "GK110",
.bar = gf100_bar_new,
.bios = nvkm_bios_new,
// .bus = gf100_bus_new,
.bus = gf100_bus_new,
// .clk = gk104_clk_new,
// .devinit = gf100_devinit_new,
// .fb = gk104_fb_new,
@ -1767,7 +1767,7 @@ nvf1_chipset = {
.name = "GK110B",
.bar = gf100_bar_new,
.bios = nvkm_bios_new,
// .bus = gf100_bus_new,
.bus = gf100_bus_new,
// .clk = gk104_clk_new,
// .devinit = gf100_devinit_new,
// .fb = gk104_fb_new,
@ -1803,7 +1803,7 @@ nv106_chipset = {
.name = "GK208B",
.bar = gf100_bar_new,
.bios = nvkm_bios_new,
// .bus = gf100_bus_new,
.bus = gf100_bus_new,
// .clk = gk104_clk_new,
// .devinit = gf100_devinit_new,
// .fb = gk104_fb_new,
@ -1838,7 +1838,7 @@ nv108_chipset = {
.name = "GK208",
.bar = gf100_bar_new,
.bios = nvkm_bios_new,
// .bus = gf100_bus_new,
.bus = gf100_bus_new,
// .clk = gk104_clk_new,
// .devinit = gf100_devinit_new,
// .fb = gk104_fb_new,
@ -1873,7 +1873,7 @@ nv117_chipset = {
.name = "GM107",
.bar = gf100_bar_new,
.bios = nvkm_bios_new,
// .bus = gf100_bus_new,
.bus = gf100_bus_new,
// .clk = gk104_clk_new,
// .devinit = gm107_devinit_new,
// .fb = gm107_fb_new,
@ -1903,7 +1903,7 @@ nv124_chipset = {
.name = "GM204",
.bar = gf100_bar_new,
.bios = nvkm_bios_new,
// .bus = gf100_bus_new,
.bus = gf100_bus_new,
// .devinit = gm204_devinit_new,
// .fb = gm107_fb_new,
// .fuse = gm107_fuse_new,
@ -1932,7 +1932,7 @@ nv126_chipset = {
.name = "GM206",
.bar = gf100_bar_new,
.bios = nvkm_bios_new,
// .bus = gf100_bus_new,
.bus = gf100_bus_new,
// .devinit = gm204_devinit_new,
// .fb = gm107_fb_new,
// .fuse = gm107_fuse_new,
@ -1960,7 +1960,7 @@ static const struct nvkm_device_chip
nv12b_chipset = {
.name = "GM20B",
.bar = gk20a_bar_new,
// .bus = gf100_bus_new,
.bus = gf100_bus_new,
// .fb = gk20a_fb_new,
// .fuse = gm107_fuse_new,
// .ibus = gk20a_ibus_new,

9
drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c
View File

@ -36,7 +36,6 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
@ -66,7 +65,6 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
@ -96,7 +94,6 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
@ -125,7 +122,6 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
@ -155,7 +151,6 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
@ -184,7 +179,6 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
@ -213,7 +207,6 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
@ -243,7 +236,6 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
@ -272,7 +264,6 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;

8
drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c
View File

@ -36,7 +36,6 @@ gk104_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
@ -67,7 +66,6 @@ gk104_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
@ -98,7 +96,6 @@ gk104_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
@ -123,7 +120,6 @@ gk104_identify(struct nvkm_device *device)
case 0xea:
device->oclass[NVDEV_SUBDEV_CLK ] = &gk20a_clk_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gk20a_fb_oclass;
@ -149,7 +145,6 @@ gk104_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
@ -180,7 +175,6 @@ gk104_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
@ -211,7 +205,6 @@ gk104_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
@ -241,7 +234,6 @@ gk104_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;

4
drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
View File

@ -36,7 +36,6 @@ gm100_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gm107_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gm107_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass;
@ -77,7 +76,6 @@ gm100_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gm204_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gm107_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass;
@ -115,7 +113,6 @@ gm100_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gm204_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gm107_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass;
@ -144,7 +141,6 @@ gm100_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gm107_fuse_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gk20a_fb_oclass;

2
drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c
View File

@ -32,7 +32,6 @@ nv04_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv04_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv04_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
@ -48,7 +47,6 @@ nv04_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv05_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv04_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;

8
drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c
View File

@ -33,7 +33,6 @@ nv10_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
@ -48,7 +47,6 @@ nv10_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
@ -65,7 +63,6 @@ nv10_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
@ -82,7 +79,6 @@ nv10_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv1a_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
@ -99,7 +95,6 @@ nv10_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
@ -116,7 +111,6 @@ nv10_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
@ -133,7 +127,6 @@ nv10_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv1a_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
@ -150,7 +143,6 @@ nv10_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;

4
drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c
View File

@ -33,7 +33,6 @@ nv20_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv20_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
@ -50,7 +49,6 @@ nv20_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv25_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
@ -67,7 +65,6 @@ nv20_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv25_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
@ -84,7 +81,6 @@ nv20_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv25_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;

5
drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c
View File

@ -33,7 +33,6 @@ nv30_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv30_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
@ -50,7 +49,6 @@ nv30_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv35_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
@ -67,7 +65,6 @@ nv30_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv30_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
@ -85,7 +82,6 @@ nv30_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv36_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
@ -103,7 +99,6 @@ nv30_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;

16
drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c
View File

@ -34,7 +34,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv40_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
@ -55,7 +54,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv41_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
@ -76,7 +74,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv41_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
@ -97,7 +94,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv41_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
@ -118,7 +114,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv40_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
@ -139,7 +134,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv47_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
@ -160,7 +154,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv49_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
@ -181,7 +174,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv49_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
@ -202,7 +194,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv44_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
@ -223,7 +214,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
@ -244,7 +234,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv44_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
@ -265,7 +254,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
@ -286,7 +274,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv4e_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
@ -307,7 +294,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
@ -328,7 +314,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
@ -349,7 +334,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;

14
drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
View File

@ -36,7 +36,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv50_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv50_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
@ -59,7 +58,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = g84_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
@ -85,7 +83,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = g84_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
@ -111,7 +108,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = g84_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
@ -137,7 +133,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = g84_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = g94_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
@ -163,7 +158,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = g84_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = g94_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
@ -189,7 +183,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = g98_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
@ -215,7 +208,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = g84_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
@ -241,7 +233,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = g98_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = mcp77_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
@ -267,7 +258,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = g98_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = mcp77_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
@ -293,7 +283,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gt215_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gt215_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
@ -321,7 +310,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gt215_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gt215_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
@ -348,7 +336,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gt215_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gt215_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
@ -375,7 +362,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = mcp89_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = mcp89_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;

1
drivers/gpu/drm/nouveau/nvkm/subdev/bus/Kbuild
View File

@ -1,3 +1,4 @@
nvkm-y += nvkm/subdev/bus/base.o
nvkm-y += nvkm/subdev/bus/hwsq.o
nvkm-y += nvkm/subdev/bus/nv04.o
nvkm-y += nvkm/subdev/bus/nv31.o

64
drivers/gpu/drm/nouveau/nvkm/subdev/bus/base.c Normal file
View File

@ -0,0 +1,64 @@
/*
* Copyright 2015 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
#include "priv.h"
static void
nvkm_bus_intr(struct nvkm_subdev *subdev)
{
struct nvkm_bus *bus = nvkm_bus(subdev);
bus->func->intr(bus);
}
static int
nvkm_bus_init(struct nvkm_subdev *subdev)
{
struct nvkm_bus *bus = nvkm_bus(subdev);
bus->func->init(bus);
return 0;
}
static void *
nvkm_bus_dtor(struct nvkm_subdev *subdev)
{
return nvkm_bus(subdev);
}
static const struct nvkm_subdev_func
nvkm_bus = {
.dtor = nvkm_bus_dtor,
.init = nvkm_bus_init,
.intr = nvkm_bus_intr,
};
int
nvkm_bus_new_(const struct nvkm_bus_func *func, struct nvkm_device *device,
int index, struct nvkm_bus **pbus)
{
struct nvkm_bus *bus;
if (!(bus = *pbus = kzalloc(sizeof(*bus), GFP_KERNEL)))
return -ENOMEM;
nvkm_subdev_ctor(&nvkm_bus, device, index, 0, &bus->subdev);
bus->func = func;
return 0;
}

22
drivers/gpu/drm/nouveau/nvkm/subdev/bus/g94.c
View File

@ -22,7 +22,7 @@
* Authors: Martin Peres <martin.peres@labri.fr>
* Ben Skeggs
*/
#include "nv04.h"
#include "priv.h"
#include <subdev/timer.h>
@ -49,16 +49,16 @@ g94_bus_hwsq_exec(struct nvkm_bus *bus, u32 *data, u32 size)
return 0;
}
struct nvkm_oclass *
g94_bus_oclass = &(struct nv04_bus_impl) {
.base.handle = NV_SUBDEV(BUS, 0x94),
.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_bus_ctor,
.dtor = _nvkm_bus_dtor,
.init = nv50_bus_init,
.fini = _nvkm_bus_fini,
},
static const struct nvkm_bus_func
g94_bus = {
.init = nv50_bus_init,
.intr = nv50_bus_intr,
.hwsq_exec = g94_bus_hwsq_exec,
.hwsq_size = 128,
}.base;
};
int
g94_bus_new(struct nvkm_device *device, int index, struct nvkm_bus **pbus)
{
return nvkm_bus_new_(&g94_bus, device, index, pbus);
}

37
drivers/gpu/drm/nouveau/nvkm/subdev/bus/gf100.c
View File

@ -22,11 +22,12 @@
* Authors: Martin Peres <martin.peres@labri.fr>
* Ben Skeggs
*/
#include "nv04.h"
#include "priv.h"
static void
gf100_bus_intr(struct nvkm_subdev *subdev)
gf100_bus_intr(struct nvkm_bus *bus)
{
struct nvkm_subdev *subdev = &bus->subdev;
struct nvkm_device *device = subdev->device;
u32 stat = nvkm_rd32(device, 0x001100) & nvkm_rd32(device, 0x001140);
@ -53,30 +54,22 @@ gf100_bus_intr(struct nvkm_subdev *subdev)
}
}
static int
gf100_bus_init(struct nvkm_object *object)
static void
gf100_bus_init(struct nvkm_bus *bus)
{
struct nvkm_bus *bus = (void *)object;
struct nvkm_device *device = bus->subdev.device;
int ret;
ret = nvkm_bus_init(bus);
if (ret)
return ret;
nvkm_wr32(device, 0x001100, 0xffffffff);
nvkm_wr32(device, 0x001140, 0x0000000e);
return 0;
}
struct nvkm_oclass *
gf100_bus_oclass = &(struct nv04_bus_impl) {
.base.handle = NV_SUBDEV(BUS, 0xc0),
.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_bus_ctor,
.dtor = _nvkm_bus_dtor,
.init = gf100_bus_init,
.fini = _nvkm_bus_fini,
},
static const struct nvkm_bus_func
gf100_bus = {
.init = gf100_bus_init,
.intr = gf100_bus_intr,
}.base;
};
int
gf100_bus_new(struct nvkm_device *device, int index, struct nvkm_bus **pbus)
{
return nvkm_bus_new_(&gf100_bus, device, index, pbus);
}

27
drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c
View File

@ -21,10 +21,10 @@
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
#include <subdev/bus.h>
#include "priv.h"
struct nvkm_hwsq {
struct nvkm_bus *bus;
struct nvkm_subdev *subdev;
u32 addr;
u32 data;
struct {
@ -41,13 +41,13 @@ hwsq_cmd(struct nvkm_hwsq *hwsq, int size, u8 data[])
}
int
nvkm_hwsq_init(struct nvkm_bus *bus, struct nvkm_hwsq **phwsq)
nvkm_hwsq_init(struct nvkm_subdev *subdev, struct nvkm_hwsq **phwsq)
{
struct nvkm_hwsq *hwsq;
hwsq = *phwsq = kmalloc(sizeof(*hwsq), GFP_KERNEL);
if (hwsq) {
hwsq->bus = bus;
hwsq->subdev = subdev;
hwsq->addr = ~0;
hwsq->data = ~0;
memset(hwsq->c.data, 0x7f, sizeof(hwsq->c.data));
@ -63,13 +63,14 @@ nvkm_hwsq_fini(struct nvkm_hwsq **phwsq, bool exec)
struct nvkm_hwsq *hwsq = *phwsq;
int ret = 0, i;
if (hwsq) {
struct nvkm_bus *bus = hwsq->bus;
struct nvkm_subdev *subdev = &bus->subdev;
struct nvkm_subdev *subdev = hwsq->subdev;
struct nvkm_bus *bus = subdev->device->bus;
hwsq->c.size = (hwsq->c.size + 4) / 4;
if (hwsq->c.size <= bus->hwsq_size) {
if (hwsq->c.size <= bus->func->hwsq_size) {
if (exec)
ret = bus->hwsq_exec(bus, (u32 *)hwsq->c.data,
hwsq->c.size);
ret = bus->func->hwsq_exec(bus,
(u32 *)hwsq->c.data,
hwsq->c.size);
if (ret)
nvkm_error(subdev, "hwsq exec failed: %d\n", ret);
} else {
@ -89,7 +90,7 @@ nvkm_hwsq_fini(struct nvkm_hwsq **phwsq, bool exec)
void
nvkm_hwsq_wr32(struct nvkm_hwsq *hwsq, u32 addr, u32 data)
{
nvkm_debug(&hwsq->bus->subdev, "R[%06x] = %08x\n", addr, data);
nvkm_debug(hwsq->subdev, "R[%06x] = %08x\n", addr, data);
if (hwsq->data != data) {
if ((data & 0xffff0000) != (hwsq->data & 0xffff0000)) {
@ -114,7 +115,7 @@ nvkm_hwsq_wr32(struct nvkm_hwsq *hwsq, u32 addr, u32 data)
void
nvkm_hwsq_setf(struct nvkm_hwsq *hwsq, u8 flag, int data)
{
nvkm_debug(&hwsq->bus->subdev, " FLAG[%02x] = %d\n", flag, data);
nvkm_debug(hwsq->subdev, " FLAG[%02x] = %d\n", flag, data);
flag += 0x80;
if (data >= 0)
flag += 0x20;
@ -126,7 +127,7 @@ nvkm_hwsq_setf(struct nvkm_hwsq *hwsq, u8 flag, int data)
void
nvkm_hwsq_wait(struct nvkm_hwsq *hwsq, u8 flag, u8 data)
{
nvkm_debug(&hwsq->bus->subdev, " WAIT[%02x] = %d\n", flag, data);
nvkm_debug(hwsq->subdev, " WAIT[%02x] = %d\n", flag, data);
hwsq_cmd(hwsq, 3, (u8[]){ 0x5f, flag, data });
}
@ -139,6 +140,6 @@ nvkm_hwsq_nsec(struct nvkm_hwsq *hwsq, u32 nsec)
shift++;
}
nvkm_debug(&hwsq->bus->subdev, " DELAY = %d ns\n", nsec);
nvkm_debug(hwsq->subdev, " DELAY = %d ns\n", nsec);
hwsq_cmd(hwsq, 1, (u8[]){ 0x00 | (shift << 2) | usec });
}

3
drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h
View File

@ -59,10 +59,9 @@ hwsq_reg(u32 addr)
static inline int
hwsq_init(struct hwsq *ram, struct nvkm_subdev *subdev)
{
struct nvkm_bus *bus = nvkm_bus(subdev);
int ret;
ret = nvkm_hwsq_init(bus, &ram->hwsq);
ret = nvkm_hwsq_init(subdev, &ram->hwsq);
if (ret)
return ret;

51
drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv04.c
View File

@ -22,13 +22,16 @@
* Authors: Martin Peres <martin.peres@labri.fr>
* Ben Skeggs
*/
#include "nv04.h"
#include "priv.h"
#include <subdev/gpio.h>
#include <subdev/gpio.h>
static void
nv04_bus_intr(struct nvkm_subdev *subdev)
nv04_bus_intr(struct nvkm_bus *bus)
{
struct nvkm_subdev *subdev = &bus->subdev;
struct nvkm_device *device = subdev->device;
u32 stat = nvkm_rd32(device, 0x001100) & nvkm_rd32(device, 0x001140);
@ -52,46 +55,22 @@ nv04_bus_intr(struct nvkm_subdev *subdev)
}
}
static int
nv04_bus_init(struct nvkm_object *object)
static void
nv04_bus_init(struct nvkm_bus *bus)
{
struct nvkm_bus *bus = (void *)object;
struct nvkm_device *device = bus->subdev.device;
nvkm_wr32(device, 0x001100, 0xffffffff);
nvkm_wr32(device, 0x001140, 0x00000111);
return nvkm_bus_init(bus);
}
static const struct nvkm_bus_func
nv04_bus = {
.init = nv04_bus_init,
.intr = nv04_bus_intr,
};
int
nv04_bus_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
nv04_bus_new(struct nvkm_device *device, int index, struct nvkm_bus **pbus)
{
struct nv04_bus_impl *impl = (void *)oclass;
struct nvkm_bus *bus;
int ret;
ret = nvkm_bus_create(parent, engine, oclass, &bus);
*pobject = nv_object(bus);
if (ret)
return ret;
nv_subdev(bus)->intr = impl->intr;
bus->hwsq_exec = impl->hwsq_exec;
bus->hwsq_size = impl->hwsq_size;
return 0;
return nvkm_bus_new_(&nv04_bus, device, index, pbus);
}
struct nvkm_oclass *
nv04_bus_oclass = &(struct nv04_bus_impl) {
.base.handle = NV_SUBDEV(BUS, 0x04),
.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_bus_ctor,
.dtor = _nvkm_bus_dtor,
.init = nv04_bus_init,
.fini = _nvkm_bus_fini,
},
.intr = nv04_bus_intr,
}.base;

17
drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv04.h
View File

@ -1,17 +0,0 @@
#ifndef __NVKM_BUS_NV04_H__
#define __NVKM_BUS_NV04_H__
#include <subdev/bus.h>
int nv04_bus_ctor(struct nvkm_object *, struct nvkm_object *,
struct nvkm_oclass *, void *, u32,
struct nvkm_object **);
int nv50_bus_init(struct nvkm_object *);
void nv50_bus_intr(struct nvkm_subdev *);
struct nv04_bus_impl {
struct nvkm_oclass base;
void (*intr)(struct nvkm_subdev *);
int (*hwsq_exec)(struct nvkm_bus *, u32 *, u32);
u32 hwsq_size;
};
#endif

37
drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv31.c
View File

@ -22,14 +22,15 @@
* Authors: Martin Peres <martin.peres@labri.fr>
* Ben Skeggs
*/
#include "nv04.h"
#include "priv.h"
#include <subdev/gpio.h>
#include <subdev/therm.h>
static void
nv31_bus_intr(struct nvkm_subdev *subdev)
nv31_bus_intr(struct nvkm_bus *bus)
{
struct nvkm_subdev *subdev = &bus->subdev;
struct nvkm_device *device = subdev->device;
u32 stat = nvkm_rd32(device, 0x001100) & nvkm_rd32(device, 0x001140);
u32 gpio = nvkm_rd32(device, 0x001104) & nvkm_rd32(device, 0x001144);
@ -66,30 +67,22 @@ nv31_bus_intr(struct nvkm_subdev *subdev)
}
}
static int
nv31_bus_init(struct nvkm_object *object)
static void
nv31_bus_init(struct nvkm_bus *bus)
{
struct nvkm_bus *bus = (void *)object;
struct nvkm_device *device = bus->subdev.device;
int ret;
ret = nvkm_bus_init(bus);
if (ret)
return ret;
nvkm_wr32(device, 0x001100, 0xffffffff);
nvkm_wr32(device, 0x001140, 0x00070008);
return 0;
}
struct nvkm_oclass *
nv31_bus_oclass = &(struct nv04_bus_impl) {
.base.handle = NV_SUBDEV(BUS, 0x31),
.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_bus_ctor,
.dtor = _nvkm_bus_dtor,
.init = nv31_bus_init,
.fini = _nvkm_bus_fini,
},
static const struct nvkm_bus_func
nv31_bus = {
.init = nv31_bus_init,
.intr = nv31_bus_intr,
}.base;
};
int
nv31_bus_new(struct nvkm_device *device, int index, struct nvkm_bus **pbus)
{
return nvkm_bus_new_(&nv31_bus, device, index, pbus);
}

37
drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv50.c
View File

@ -22,7 +22,7 @@
* Authors: Martin Peres <martin.peres@labri.fr>
* Ben Skeggs
*/
#include "nv04.h"
#include "priv.h"
#include <subdev/therm.h>
#include <subdev/timer.h>
@ -50,8 +50,9 @@ nv50_bus_hwsq_exec(struct nvkm_bus *bus, u32 *data, u32 size)
}
void
nv50_bus_intr(struct nvkm_subdev *subdev)
nv50_bus_intr(struct nvkm_bus *bus)
{
struct nvkm_subdev *subdev = &bus->subdev;
struct nvkm_device *device = subdev->device;
u32 stat = nvkm_rd32(device, 0x001100) & nvkm_rd32(device, 0x001140);
@ -81,32 +82,24 @@ nv50_bus_intr(struct nvkm_subdev *subdev)
}
}
int
nv50_bus_init(struct nvkm_object *object)
void
nv50_bus_init(struct nvkm_bus *bus)
{
struct nvkm_bus *bus = (void *)object;
struct nvkm_device *device = bus->subdev.device;
int ret;
ret = nvkm_bus_init(bus);
if (ret)
return ret;
nvkm_wr32(device, 0x001100, 0xffffffff);
nvkm_wr32(device, 0x001140, 0x00010008);
return 0;
}
struct nvkm_oclass *
nv50_bus_oclass = &(struct nv04_bus_impl) {
.base.handle = NV_SUBDEV(BUS, 0x50),
.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_bus_ctor,
.dtor = _nvkm_bus_dtor,
.init = nv50_bus_init,
.fini = _nvkm_bus_fini,
},
static const struct nvkm_bus_func
nv50_bus = {
.init = nv50_bus_init,
.intr = nv50_bus_intr,
.hwsq_exec = nv50_bus_hwsq_exec,
.hwsq_size = 64,
}.base;
};
int
nv50_bus_new(struct nvkm_device *device, int index, struct nvkm_bus **pbus)
{
return nvkm_bus_new_(&nv50_bus, device, index, pbus);
}

18
drivers/gpu/drm/nouveau/nvkm/subdev/bus/priv.h Normal file
View File

@ -0,0 +1,18 @@
#ifndef __NVKM_BUS_PRIV_H__
#define __NVKM_BUS_PRIV_H__
#define nvkm_bus(p) container_of((p), struct nvkm_bus, subdev)
#include <subdev/bus.h>
struct nvkm_bus_func {
void (*init)(struct nvkm_bus *);
void (*intr)(struct nvkm_bus *);
int (*hwsq_exec)(struct nvkm_bus *, u32 *, u32);
u32 hwsq_size;
};
int nvkm_bus_new_(const struct nvkm_bus_func *, struct nvkm_device *, int,
struct nvkm_bus **);
void nv50_bus_init(struct nvkm_bus *);
void nv50_bus_intr(struct nvkm_bus *);
#endif