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drm/i915/icl: Fix DDI/TC port clk_off bits 

DDI/TC clock-off bits are not equally distanced. TC1-3 bits are
from offset 12 & TC4 is at offset 21.
Create a function to choose correct clk-off bit.

v2: Add fixes tag (Lucas)

Fixes: c27e917e2b ("drm/i915/icl: add basic support for the ICL clocks")
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181016023752.9285-1-lucas.demarchi@intel.com
This commit is contained in:
Mahesh Kumar 2018-10-15 19:37:52 -07:00 committed by Rodrigo Vivi
parent 4e53840fdf
commit bb1c7edc6d
2 changed files with 21 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/gpu/drm/i915/i915_reg.h
View File

@ -9319,6 +9319,9 @@ enum skl_power_gate {
#define DPCLKA_CFGCR0_ICL _MMIO(0x164280)
#define DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port) == PORT_F ? 23 : \
(port) + 10))
#define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port) + 10))
#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) == PORT_TC4 ? \
21 : (tc_port) + 12))
#define DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port) ((port) == PORT_F ? 21 : \
(port) * 2)
#define DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port) (3 << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))

21
drivers/gpu/drm/i915/intel_ddi.c
View File

@ -2740,6 +2740,21 @@ uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
return DDI_BUF_TRANS_SELECT(level);
}
static inline
uint32_t icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
enum port port)
{
if (intel_port_is_combophy(dev_priv, port)) {
return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port);
} else if (intel_port_is_tc(dev_priv, port)) {
enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port);
}
return 0;
}
void icl_map_plls_to_ports(struct drm_crtc *crtc,
struct intel_crtc_state *crtc_state,
struct drm_atomic_state *old_state)
@ -2763,7 +2778,7 @@ void icl_map_plls_to_ports(struct drm_crtc *crtc,
mutex_lock(&dev_priv->dpll_lock);
val = I915_READ(DPCLKA_CFGCR0_ICL);
WARN_ON((val & DPCLKA_CFGCR0_DDI_CLK_OFF(port)) == 0);
WARN_ON((val & icl_dpclka_cfgcr0_clk_off(dev_priv, port)) == 0);
if (intel_port_is_combophy(dev_priv, port)) {
val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
@ -2772,7 +2787,7 @@ void icl_map_plls_to_ports(struct drm_crtc *crtc,
POSTING_READ(DPCLKA_CFGCR0_ICL);
}
val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, port);
I915_WRITE(DPCLKA_CFGCR0_ICL, val);
mutex_unlock(&dev_priv->dpll_lock);
@ -2800,7 +2815,7 @@ void icl_unmap_plls_to_ports(struct drm_crtc *crtc,
mutex_lock(&dev_priv->dpll_lock);
I915_WRITE(DPCLKA_CFGCR0_ICL,
I915_READ(DPCLKA_CFGCR0_ICL) |
DPCLKA_CFGCR0_DDI_CLK_OFF(port));
icl_dpclka_cfgcr0_clk_off(dev_priv, port));
mutex_unlock(&dev_priv->dpll_lock);
}
}