arm64: KVM: Add a new vcpu device control group for PMUv3
To configure the virtual PMUv3 overflow interrupt number, we use the vcpu kvm_device ioctl, encapsulating the KVM_ARM_VCPU_PMU_V3_IRQ attribute within the KVM_ARM_VCPU_PMU_V3_CTRL group. After configuring the PMUv3, call the vcpu ioctl with attribute KVM_ARM_VCPU_PMU_V3_INIT to initialize the PMUv3. Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Acked-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Andrew Jones <drjones@redhat.com> Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
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@ -6,3 +6,28 @@ KVM_GET_DEVICE_ATTR, and KVM_HAS_DEVICE_ATTR. The interface uses the same struct
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kvm_device_attr as other devices, but targets VCPU-wide settings and controls.
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The groups and attributes per virtual cpu, if any, are architecture specific.
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1. GROUP: KVM_ARM_VCPU_PMU_V3_CTRL
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Architectures: ARM64
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1.1. ATTRIBUTE: KVM_ARM_VCPU_PMU_V3_IRQ
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Parameters: in kvm_device_attr.addr the address for PMU overflow interrupt is a
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pointer to an int
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Returns: -EBUSY: The PMU overflow interrupt is already set
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-ENXIO: The overflow interrupt not set when attempting to get it
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-ENODEV: PMUv3 not supported
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-EINVAL: Invalid PMU overflow interrupt number supplied
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A value describing the PMUv3 (Performance Monitor Unit v3) overflow interrupt
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number for this vcpu. This interrupt could be a PPI or SPI, but the interrupt
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type must be same for each vcpu. As a PPI, the interrupt number is the same for
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all vcpus, while as an SPI it must be a separate number per vcpu.
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1.2 ATTRIBUTE: KVM_ARM_VCPU_PMU_V3_INIT
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Parameters: no additional parameter in kvm_device_attr.addr
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Returns: -ENODEV: PMUv3 not supported
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-ENXIO: PMUv3 not properly configured as required prior to calling this
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attribute
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-EBUSY: PMUv3 already initialized
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Request the initialization of the PMUv3.
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@ -287,5 +287,20 @@ static inline void kvm_arm_init_debug(void) {}
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static inline void kvm_arm_setup_debug(struct kvm_vcpu *vcpu) {}
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static inline void kvm_arm_clear_debug(struct kvm_vcpu *vcpu) {}
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static inline void kvm_arm_reset_debug_ptr(struct kvm_vcpu *vcpu) {}
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static inline int kvm_arm_vcpu_arch_set_attr(struct kvm_vcpu *vcpu,
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struct kvm_device_attr *attr)
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{
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return -ENXIO;
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}
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static inline int kvm_arm_vcpu_arch_get_attr(struct kvm_vcpu *vcpu,
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struct kvm_device_attr *attr)
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{
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return -ENXIO;
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}
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static inline int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu,
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struct kvm_device_attr *attr)
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{
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return -ENXIO;
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}
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#endif /* __ARM_KVM_HOST_H__ */
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@ -835,6 +835,7 @@ static int kvm_arm_vcpu_set_attr(struct kvm_vcpu *vcpu,
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switch (attr->group) {
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default:
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ret = kvm_arm_vcpu_arch_set_attr(vcpu, attr);
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break;
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}
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@ -848,6 +849,7 @@ static int kvm_arm_vcpu_get_attr(struct kvm_vcpu *vcpu,
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switch (attr->group) {
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default:
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ret = kvm_arm_vcpu_arch_get_attr(vcpu, attr);
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break;
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}
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@ -861,6 +863,7 @@ static int kvm_arm_vcpu_has_attr(struct kvm_vcpu *vcpu,
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switch (attr->group) {
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default:
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ret = kvm_arm_vcpu_arch_has_attr(vcpu, attr);
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break;
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}
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@ -361,6 +361,12 @@ void kvm_arm_init_debug(void);
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void kvm_arm_setup_debug(struct kvm_vcpu *vcpu);
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void kvm_arm_clear_debug(struct kvm_vcpu *vcpu);
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void kvm_arm_reset_debug_ptr(struct kvm_vcpu *vcpu);
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int kvm_arm_vcpu_arch_set_attr(struct kvm_vcpu *vcpu,
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struct kvm_device_attr *attr);
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int kvm_arm_vcpu_arch_get_attr(struct kvm_vcpu *vcpu,
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struct kvm_device_attr *attr);
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int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu,
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struct kvm_device_attr *attr);
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/* #define kvm_call_hyp(f, ...) __kvm_call_hyp(kvm_ksym_ref(f), ##__VA_ARGS__) */
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@ -205,6 +205,11 @@ struct kvm_arch_memory_slot {
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#define KVM_DEV_ARM_VGIC_GRP_CTRL 4
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#define KVM_DEV_ARM_VGIC_CTRL_INIT 0
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/* Device Control API on vcpu fd */
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#define KVM_ARM_VCPU_PMU_V3_CTRL 0
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#define KVM_ARM_VCPU_PMU_V3_IRQ 0
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#define KVM_ARM_VCPU_PMU_V3_INIT 1
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/* KVM_IRQ_LINE irq field index values */
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#define KVM_ARM_IRQ_TYPE_SHIFT 24
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#define KVM_ARM_IRQ_TYPE_MASK 0xff
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@ -380,3 +380,54 @@ int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
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}
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return 0;
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}
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int kvm_arm_vcpu_arch_set_attr(struct kvm_vcpu *vcpu,
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struct kvm_device_attr *attr)
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{
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int ret;
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switch (attr->group) {
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case KVM_ARM_VCPU_PMU_V3_CTRL:
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ret = kvm_arm_pmu_v3_set_attr(vcpu, attr);
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break;
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default:
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ret = -ENXIO;
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break;
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}
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return ret;
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}
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int kvm_arm_vcpu_arch_get_attr(struct kvm_vcpu *vcpu,
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struct kvm_device_attr *attr)
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{
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int ret;
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switch (attr->group) {
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case KVM_ARM_VCPU_PMU_V3_CTRL:
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ret = kvm_arm_pmu_v3_get_attr(vcpu, attr);
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break;
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default:
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ret = -ENXIO;
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break;
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}
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return ret;
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}
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int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu,
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struct kvm_device_attr *attr)
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{
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int ret;
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switch (attr->group) {
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case KVM_ARM_VCPU_PMU_V3_CTRL:
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ret = kvm_arm_pmu_v3_has_attr(vcpu, attr);
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break;
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default:
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ret = -ENXIO;
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break;
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}
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return ret;
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}
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@ -39,6 +39,7 @@ struct kvm_pmu {
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};
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#define kvm_arm_pmu_v3_ready(v) ((v)->arch.pmu.ready)
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#define kvm_arm_pmu_irq_initialized(v) ((v)->arch.pmu.irq_num >= VGIC_NR_SGIS)
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u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u64 select_idx);
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void kvm_pmu_set_counter_value(struct kvm_vcpu *vcpu, u64 select_idx, u64 val);
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u64 kvm_pmu_valid_counter_mask(struct kvm_vcpu *vcpu);
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@ -54,11 +55,18 @@ void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val);
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void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u64 data,
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u64 select_idx);
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bool kvm_arm_support_pmu_v3(void);
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int kvm_arm_pmu_v3_set_attr(struct kvm_vcpu *vcpu,
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struct kvm_device_attr *attr);
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int kvm_arm_pmu_v3_get_attr(struct kvm_vcpu *vcpu,
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struct kvm_device_attr *attr);
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int kvm_arm_pmu_v3_has_attr(struct kvm_vcpu *vcpu,
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struct kvm_device_attr *attr);
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#else
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struct kvm_pmu {
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};
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#define kvm_arm_pmu_v3_ready(v) (false)
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#define kvm_arm_pmu_irq_initialized(v) (false)
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static inline u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu,
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u64 select_idx)
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{
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@ -82,6 +90,21 @@ static inline void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val) {}
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static inline void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu,
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u64 data, u64 select_idx) {}
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static inline bool kvm_arm_support_pmu_v3(void) { return false; }
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static inline int kvm_arm_pmu_v3_set_attr(struct kvm_vcpu *vcpu,
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struct kvm_device_attr *attr)
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{
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return -ENXIO;
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}
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static inline int kvm_arm_pmu_v3_get_attr(struct kvm_vcpu *vcpu,
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struct kvm_device_attr *attr)
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{
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return -ENXIO;
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}
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static inline int kvm_arm_pmu_v3_has_attr(struct kvm_vcpu *vcpu,
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struct kvm_device_attr *attr)
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{
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return -ENXIO;
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}
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#endif
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#endif
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@ -19,6 +19,7 @@
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#include <linux/kvm.h>
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#include <linux/kvm_host.h>
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#include <linux/perf_event.h>
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#include <linux/uaccess.h>
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#include <asm/kvm_emulate.h>
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#include <kvm/arm_pmu.h>
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#include <kvm/arm_vgic.h>
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*/
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return (perf_num_counters() > 0);
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}
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static int kvm_arm_pmu_v3_init(struct kvm_vcpu *vcpu)
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{
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if (!kvm_arm_support_pmu_v3())
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return -ENODEV;
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if (!test_bit(KVM_ARM_VCPU_PMU_V3, vcpu->arch.features) ||
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!kvm_arm_pmu_irq_initialized(vcpu))
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return -ENXIO;
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if (kvm_arm_pmu_v3_ready(vcpu))
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return -EBUSY;
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kvm_pmu_vcpu_reset(vcpu);
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vcpu->arch.pmu.ready = true;
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return 0;
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}
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static bool irq_is_valid(struct kvm *kvm, int irq, bool is_ppi)
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{
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int i;
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struct kvm_vcpu *vcpu;
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kvm_for_each_vcpu(i, vcpu, kvm) {
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if (!kvm_arm_pmu_irq_initialized(vcpu))
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continue;
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if (is_ppi) {
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if (vcpu->arch.pmu.irq_num != irq)
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return false;
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} else {
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if (vcpu->arch.pmu.irq_num == irq)
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return false;
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}
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}
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return true;
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}
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int kvm_arm_pmu_v3_set_attr(struct kvm_vcpu *vcpu, struct kvm_device_attr *attr)
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{
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switch (attr->attr) {
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case KVM_ARM_VCPU_PMU_V3_IRQ: {
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int __user *uaddr = (int __user *)(long)attr->addr;
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int irq;
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if (!test_bit(KVM_ARM_VCPU_PMU_V3, vcpu->arch.features))
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return -ENODEV;
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if (get_user(irq, uaddr))
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return -EFAULT;
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/*
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* The PMU overflow interrupt could be a PPI or SPI, but for one
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* VM the interrupt type must be same for each vcpu. As a PPI,
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* the interrupt number is the same for all vcpus, while as an
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* SPI it must be a separate number per vcpu.
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*/
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if (irq < VGIC_NR_SGIS || irq >= vcpu->kvm->arch.vgic.nr_irqs ||
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!irq_is_valid(vcpu->kvm, irq, irq < VGIC_NR_PRIVATE_IRQS))
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return -EINVAL;
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if (kvm_arm_pmu_irq_initialized(vcpu))
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return -EBUSY;
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kvm_debug("Set kvm ARM PMU irq: %d\n", irq);
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vcpu->arch.pmu.irq_num = irq;
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return 0;
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}
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case KVM_ARM_VCPU_PMU_V3_INIT:
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return kvm_arm_pmu_v3_init(vcpu);
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}
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return -ENXIO;
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}
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int kvm_arm_pmu_v3_get_attr(struct kvm_vcpu *vcpu, struct kvm_device_attr *attr)
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{
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switch (attr->attr) {
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case KVM_ARM_VCPU_PMU_V3_IRQ: {
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int __user *uaddr = (int __user *)(long)attr->addr;
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int irq;
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if (!test_bit(KVM_ARM_VCPU_PMU_V3, vcpu->arch.features))
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return -ENODEV;
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if (!kvm_arm_pmu_irq_initialized(vcpu))
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return -ENXIO;
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irq = vcpu->arch.pmu.irq_num;
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return put_user(irq, uaddr);
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}
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}
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return -ENXIO;
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}
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int kvm_arm_pmu_v3_has_attr(struct kvm_vcpu *vcpu, struct kvm_device_attr *attr)
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{
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switch (attr->attr) {
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case KVM_ARM_VCPU_PMU_V3_IRQ:
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case KVM_ARM_VCPU_PMU_V3_INIT:
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if (kvm_arm_support_pmu_v3() &&
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test_bit(KVM_ARM_VCPU_PMU_V3, vcpu->arch.features))
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return 0;
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}
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return -ENXIO;
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}
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