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Merge branch 'net-mdio-remove-support-for-building-c45-muxed-addresses' 

Michael Walle says:

====================
net: mdio: Remove support for building C45 muxed addresses

I've picked this older series from Andrew up and rebased it onto
the latest net-next.

With all drivers which support c45 now being converted to a seperate c22
and c45 access op, we can now remove the old MII_ADDR_C45 flag.
====================

Link: https://lore.kernel.org/r/20230119130700.440601-1-michael@walle.cc
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Jakub Kicinski 2023-01-20 18:12:47 -08:00
parent bc170f96c0 99d5fe9c7f
commit bad5532ecf
16 changed files with 4 additions and 108 deletions
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6
drivers/net/dsa/microchip/ksz_common.c
View File

@ -1777,9 +1777,6 @@ static int ksz_sw_mdio_read(struct mii_bus *bus, int addr, int regnum)
u16 val;
int ret;
if (regnum & MII_ADDR_C45)
return -EOPNOTSUPP;
ret = dev->dev_ops->r_phy(dev, addr, regnum, &val);
if (ret < 0)
return ret;
@ -1792,9 +1789,6 @@ static int ksz_sw_mdio_write(struct mii_bus *bus, int addr, int regnum,
{
struct ksz_device *dev = bus->priv;
if (regnum & MII_ADDR_C45)
return -EOPNOTSUPP;
return dev->dev_ops->w_phy(dev, addr, regnum, val);
}

6
drivers/net/dsa/rzn1_a5psw.c
View File

@ -781,9 +781,6 @@ static int a5psw_mdio_read(struct mii_bus *bus, int phy_id, int phy_reg)
u32 cmd, status;
int ret;
if (phy_reg & MII_ADDR_C45)
return -EOPNOTSUPP;
cmd = A5PSW_MDIO_COMMAND_READ;
cmd |= FIELD_PREP(A5PSW_MDIO_COMMAND_REG_ADDR, phy_reg);
cmd |= FIELD_PREP(A5PSW_MDIO_COMMAND_PHY_ADDR, phy_id);
@ -809,9 +806,6 @@ static int a5psw_mdio_write(struct mii_bus *bus, int phy_id, int phy_reg,
struct a5psw *a5psw = bus->priv;
u32 cmd;
if (phy_reg & MII_ADDR_C45)
return -EOPNOTSUPP;
cmd = FIELD_PREP(A5PSW_MDIO_COMMAND_REG_ADDR, phy_reg);
cmd |= FIELD_PREP(A5PSW_MDIO_COMMAND_PHY_ADDR, phy_id);

6
drivers/net/dsa/sja1105/sja1105_mdio.c
View File

@ -235,9 +235,6 @@ static int sja1105_base_tx_mdio_read(struct mii_bus *bus, int phy, int reg)
u32 tmp;
int rc;
if (reg & MII_ADDR_C45)
return -EOPNOTSUPP;
rc = sja1105_xfer_u32(priv, SPI_READ, regs->mdio_100base_tx + reg,
&tmp, NULL);
if (rc < 0)
@ -254,9 +251,6 @@ static int sja1105_base_tx_mdio_write(struct mii_bus *bus, int phy, int reg,
const struct sja1105_regs *regs = priv->info->regs;
u32 tmp = val;
if (reg & MII_ADDR_C45)
return -EOPNOTSUPP;
return sja1105_xfer_u32(priv, SPI_WRITE, regs->mdio_100base_tx + reg,
&tmp, NULL);
}

6
drivers/net/ethernet/actions/owl-emac.c
View File

@ -1275,9 +1275,6 @@ static int owl_emac_mdio_read(struct mii_bus *bus, int addr, int regnum)
u32 data, tmp;
int ret;
if (regnum & MII_ADDR_C45)
return -EOPNOTSUPP;
data = OWL_EMAC_BIT_MAC_CSR10_SB;
data |= OWL_EMAC_VAL_MAC_CSR10_OPCODE_RD << OWL_EMAC_OFF_MAC_CSR10_OPCODE;
@ -1305,9 +1302,6 @@ owl_emac_mdio_write(struct mii_bus *bus, int addr, int regnum, u16 val)
struct owl_emac_priv *priv = bus->priv;
u32 data, tmp;
if (regnum & MII_ADDR_C45)
return -EOPNOTSUPP;
data = OWL_EMAC_BIT_MAC_CSR10_SB;
data |= OWL_EMAC_VAL_MAC_CSR10_OPCODE_WR << OWL_EMAC_OFF_MAC_CSR10_OPCODE;

6
drivers/net/ethernet/engleder/tsnep_main.c
View File

@ -130,9 +130,6 @@ static int tsnep_mdiobus_read(struct mii_bus *bus, int addr, int regnum)
u32 md;
int retval;
if (regnum & MII_ADDR_C45)
return -EOPNOTSUPP;
md = ECM_MD_READ;
if (!adapter->suppress_preamble)
md |= ECM_MD_PREAMBLE;
@ -154,9 +151,6 @@ static int tsnep_mdiobus_write(struct mii_bus *bus, int addr, int regnum,
u32 md;
int retval;
if (regnum & MII_ADDR_C45)
return -EOPNOTSUPP;
md = ECM_MD_WRITE;
if (!adapter->suppress_preamble)
md |= ECM_MD_PREAMBLE;

6
drivers/net/ethernet/marvell/mvmdio.c
View File

@ -146,9 +146,6 @@ static int orion_mdio_smi_read(struct mii_bus *bus, int mii_id,
u32 val;
int ret;
if (regnum & MII_ADDR_C45)
return -EOPNOTSUPP;
ret = orion_mdio_wait_ready(&orion_mdio_smi_ops, bus);
if (ret < 0)
return ret;
@ -177,9 +174,6 @@ static int orion_mdio_smi_write(struct mii_bus *bus, int mii_id,
struct orion_mdio_dev *dev = bus->priv;
int ret;
if (regnum & MII_ADDR_C45)
return -EOPNOTSUPP;
ret = orion_mdio_wait_ready(&orion_mdio_smi_ops, bus);
if (ret < 0)
return ret;

6
drivers/net/ethernet/mediatek/mtk_star_emac.c
View File

@ -1378,9 +1378,6 @@ static int mtk_star_mdio_read(struct mii_bus *mii, int phy_id, int regnum)
unsigned int val, data;
int ret;
if (regnum & MII_ADDR_C45)
return -EOPNOTSUPP;
mtk_star_mdio_rwok_clear(priv);
val = (regnum << MTK_STAR_OFF_PHY_CTRL0_PREG);
@ -1407,9 +1404,6 @@ static int mtk_star_mdio_write(struct mii_bus *mii, int phy_id,
struct mtk_star_priv *priv = mii->priv;
unsigned int val;
if (regnum & MII_ADDR_C45)
return -EOPNOTSUPP;
mtk_star_mdio_rwok_clear(priv);
val = data;

6
drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_mdio.c
View File

@ -213,9 +213,6 @@ static int mlxbf_gige_mdio_read(struct mii_bus *bus, int phy_add, int phy_reg)
int ret;
u32 val;
if (phy_reg & MII_ADDR_C45)
return -EOPNOTSUPP;
/* Send mdio read request */
cmd = mlxbf_gige_mdio_create_cmd(priv->mdio_gw, 0, phy_add, phy_reg,
MLXBF_GIGE_MDIO_CL22_READ);
@ -249,9 +246,6 @@ static int mlxbf_gige_mdio_write(struct mii_bus *bus, int phy_add,
u32 cmd;
int ret;
if (phy_reg & MII_ADDR_C45)
return -EOPNOTSUPP;
/* Send mdio write request */
cmd = mlxbf_gige_mdio_create_cmd(priv->mdio_gw, val, phy_add, phy_reg,
MLXBF_GIGE_MDIO_CL22_WRITE);

6
drivers/net/ethernet/sunplus/spl2sw_mdio.c
View File

@ -61,9 +61,6 @@ static int spl2sw_mii_read(struct mii_bus *bus, int addr, int regnum)
{
struct spl2sw_common *comm = bus->priv;
if (regnum & MII_ADDR_C45)
return -EOPNOTSUPP;
return spl2sw_mdio_access(comm, SPL2SW_MDIO_READ_CMD, addr, regnum, 0);
}
@ -72,9 +69,6 @@ static int spl2sw_mii_write(struct mii_bus *bus, int addr, int regnum, u16 val)
struct spl2sw_common *comm = bus->priv;
int ret;
if (regnum & MII_ADDR_C45)
return -EOPNOTSUPP;
ret = spl2sw_mdio_access(comm, SPL2SW_MDIO_WRITE_CMD, addr, regnum, val);
if (ret < 0)
return ret;

4
drivers/net/ethernet/wangxun/ngbe/ngbe_mdio.c
View File

@ -92,7 +92,7 @@ static int ngbe_phy_read_reg_mdi_c45(struct mii_bus *bus, int phy_addr, int devn
wr32(wx, NGBE_MDIO_CLAUSE_SELECT, 0x0);
/* setup and write the address cycle command */
command = NGBE_MSCA_RA(mdiobus_c45_regad(regnum)) |
command = NGBE_MSCA_RA(regnum) |
NGBE_MSCA_PA(phy_addr) |
NGBE_MSCA_DA(devnum);
wr32(wx, NGBE_MSCA, command);
@ -121,7 +121,7 @@ static int ngbe_phy_write_reg_mdi_c45(struct mii_bus *bus, int phy_addr,
wr32(wx, NGBE_MDIO_CLAUSE_SELECT, 0x0);
/* setup and write the address cycle command */
command = NGBE_MSCA_RA(mdiobus_c45_regad(regnum)) |
command = NGBE_MSCA_RA(regnum) |
NGBE_MSCA_PA(phy_addr) |
NGBE_MSCA_DA(devnum);
wr32(wx, NGBE_MSCA, command);

6
drivers/net/mdio/mdio-i2c.c
View File

@ -297,9 +297,6 @@ static int i2c_mii_read_rollball(struct mii_bus *bus, int phy_id, int reg)
int bus_addr, ret;
u16 val;
if (!(reg & MII_ADDR_C45))
return -EOPNOTSUPP;
bus_addr = i2c_mii_phy_addr(phy_id);
if (bus_addr != ROLLBALL_PHY_I2C_ADDR)
return 0xffff;
@ -331,9 +328,6 @@ static int i2c_mii_write_rollball(struct mii_bus *bus, int phy_id, int reg,
int bus_addr, ret;
u8 buf[6];
if (!(reg & MII_ADDR_C45))
return -EOPNOTSUPP;
bus_addr = i2c_mii_phy_addr(phy_id);
if (bus_addr != ROLLBALL_PHY_I2C_ADDR)
return 0;

8
drivers/net/mdio/mdio-ipq8064.c
View File

@ -57,10 +57,6 @@ ipq8064_mdio_read(struct mii_bus *bus, int phy_addr, int reg_offset)
u32 ret_val;
int err;
/* Reject clause 45 */
if (reg_offset & MII_ADDR_C45)
return -EOPNOTSUPP;
miiaddr |= ((phy_addr << MII_ADDR_SHIFT) & MII_ADDR_MASK) |
((reg_offset << MII_REG_SHIFT) & MII_REG_MASK);
@ -81,10 +77,6 @@ ipq8064_mdio_write(struct mii_bus *bus, int phy_addr, int reg_offset, u16 data)
u32 miiaddr = MII_WRITE | MII_BUSY | MII_CLKRANGE_250_300M;
struct ipq8064_mdio *priv = bus->priv;
/* Reject clause 45 */
if (reg_offset & MII_ADDR_C45)
return -EOPNOTSUPP;
regmap_write(priv->base, MII_DATA_REG_ADDR, data);
miiaddr |= ((phy_addr << MII_ADDR_SHIFT) & MII_ADDR_MASK) |

6
drivers/net/mdio/mdio-mscc-miim.c
View File

@ -108,9 +108,6 @@ static int mscc_miim_read(struct mii_bus *bus, int mii_id, int regnum)
u32 val;
int ret;
if (regnum & MII_ADDR_C45)
return -EOPNOTSUPP;
ret = mscc_miim_wait_pending(bus);
if (ret)
goto out;
@ -154,9 +151,6 @@ static int mscc_miim_write(struct mii_bus *bus, int mii_id,
struct mscc_miim_dev *miim = bus->priv;
int ret;
if (regnum & MII_ADDR_C45)
return -EOPNOTSUPP;
ret = mscc_miim_wait_pending(bus);
if (ret < 0)
goto out;

6
drivers/net/mdio/mdio-mvusb.c
View File

@ -34,9 +34,6 @@ static int mvusb_mdio_read(struct mii_bus *mdio, int dev, int reg)
struct mvusb_mdio *mvusb = mdio->priv;
int err, alen;
if (dev & MII_ADDR_C45)
return -EOPNOTSUPP;
mvusb->buf[MVUSB_CMD_ADDR] = cpu_to_le16(0xa400 | (dev << 5) | reg);
err = usb_bulk_msg(mvusb->udev, usb_sndbulkpipe(mvusb->udev, 2),
@ -57,9 +54,6 @@ static int mvusb_mdio_write(struct mii_bus *mdio, int dev, int reg, u16 val)
struct mvusb_mdio *mvusb = mdio->priv;
int alen;
if (dev & MII_ADDR_C45)
return -EOPNOTSUPP;
mvusb->buf[MVUSB_CMD_ADDR] = cpu_to_le16(0x8000 | (dev << 5) | reg);
mvusb->buf[MVUSB_CMD_VAL] = cpu_to_le16(val);

10
drivers/net/phy/mdio_bus.c
View File

@ -917,11 +917,6 @@ int __mdiobus_modify_changed(struct mii_bus *bus, int addr, u32 regnum,
}
EXPORT_SYMBOL_GPL(__mdiobus_modify_changed);
static u32 mdiobus_c45_addr(int devad, u16 regnum)
{
return MII_ADDR_C45 | devad << MII_DEVADDR_C45_SHIFT | regnum;
}
/**
* __mdiobus_c45_read - Unlocked version of the mdiobus_c45_read function
* @bus: the mii_bus struct
@ -942,7 +937,7 @@ int __mdiobus_c45_read(struct mii_bus *bus, int addr, int devad, u32 regnum)
if (bus->read_c45)
retval = bus->read_c45(bus, addr, devad, regnum);
else
retval = bus->read(bus, addr, mdiobus_c45_addr(devad, regnum));
retval = -EOPNOTSUPP;
trace_mdio_access(bus, 1, addr, regnum, retval, retval);
mdiobus_stats_acct(&bus->stats[addr], true, retval);
@ -973,8 +968,7 @@ int __mdiobus_c45_write(struct mii_bus *bus, int addr, int devad, u32 regnum,
if (bus->write_c45)
err = bus->write_c45(bus, addr, devad, regnum, val);
else
err = bus->write(bus, addr, mdiobus_c45_addr(devad, regnum),
val);
err = -EOPNOTSUPP;
trace_mdio_access(bus, 0, addr, regnum, val, err);
mdiobus_stats_acct(&bus->stats[addr], false, err);

18
include/linux/mdio.h
View File

@ -10,14 +10,6 @@
#include <linux/bitfield.h>
#include <linux/mod_devicetable.h>
/* Or MII_ADDR_C45 into regnum for read/write on mii_bus to enable the 21 bit
* IEEE 802.3ae clause 45 addressing mode used by 10GIGE phy chips.
*/
#define MII_ADDR_C45 (1<<30)
#define MII_DEVADDR_C45_SHIFT 16
#define MII_DEVADDR_C45_MASK GENMASK(20, 16)
#define MII_REGADDR_C45_MASK GENMASK(15, 0)
struct gpio_desc;
struct mii_bus;
struct reset_control;
@ -463,16 +455,6 @@ static inline int mdiodev_modify_changed(struct mdio_device *mdiodev,
mask, set);
}
static inline u16 mdiobus_c45_regad(u32 regnum)
{
return FIELD_GET(MII_REGADDR_C45_MASK, regnum);
}
static inline u16 mdiobus_c45_devad(u32 regnum)
{
return FIELD_GET(MII_DEVADDR_C45_MASK, regnum);
}
static inline int mdiodev_c45_modify(struct mdio_device *mdiodev, int devad,
u32 regnum, u16 mask, u16 set)
{