be2net: do not call be_set/get_fw_log_level() on Skyhawk-R

Skyhawk-R FW does not support SET/GET_EXT_FAT_CAPABILITIES cmds via which
FW logging level can be controlled. Also, the hack used in BE3 to control
FW logging level via the ethtool interface is not needed in Skyhawk-R.

This patch also cleans up this code by moving be_set/get_fw_log_level()
routines to be_cmds.c where they belong.

Signed-off-by: Vasundhara Volam <vasundhara.volam@emulex.com>

remove new line
Signed-off-by: Sathya Perla <sathya.perla@emulex.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Vasundhara Volam 2014-01-15 13:23:34 +05:30 committed by David S. Miller
parent 542963b7d7
commit baaa08d148
4 changed files with 82 additions and 97 deletions

View File

@ -3084,6 +3084,76 @@ err:
return status;
}
int be_cmd_set_fw_log_level(struct be_adapter *adapter, u32 level)
{
struct be_dma_mem extfat_cmd;
struct be_fat_conf_params *cfgs;
int status;
int i, j;
memset(&extfat_cmd, 0, sizeof(struct be_dma_mem));
extfat_cmd.size = sizeof(struct be_cmd_resp_get_ext_fat_caps);
extfat_cmd.va = pci_alloc_consistent(adapter->pdev, extfat_cmd.size,
&extfat_cmd.dma);
if (!extfat_cmd.va)
return -ENOMEM;
status = be_cmd_get_ext_fat_capabilites(adapter, &extfat_cmd);
if (status)
goto err;
cfgs = (struct be_fat_conf_params *)
(extfat_cmd.va + sizeof(struct be_cmd_resp_hdr));
for (i = 0; i < le32_to_cpu(cfgs->num_modules); i++) {
u32 num_modes = le32_to_cpu(cfgs->module[i].num_modes);
for (j = 0; j < num_modes; j++) {
if (cfgs->module[i].trace_lvl[j].mode == MODE_UART)
cfgs->module[i].trace_lvl[j].dbg_lvl =
cpu_to_le32(level);
}
}
status = be_cmd_set_ext_fat_capabilites(adapter, &extfat_cmd, cfgs);
err:
pci_free_consistent(adapter->pdev, extfat_cmd.size, extfat_cmd.va,
extfat_cmd.dma);
return status;
}
int be_cmd_get_fw_log_level(struct be_adapter *adapter)
{
struct be_dma_mem extfat_cmd;
struct be_fat_conf_params *cfgs;
int status, j;
int level = 0;
memset(&extfat_cmd, 0, sizeof(struct be_dma_mem));
extfat_cmd.size = sizeof(struct be_cmd_resp_get_ext_fat_caps);
extfat_cmd.va = pci_alloc_consistent(adapter->pdev, extfat_cmd.size,
&extfat_cmd.dma);
if (!extfat_cmd.va) {
dev_err(&adapter->pdev->dev, "%s: Memory allocation failure\n",
__func__);
goto err;
}
status = be_cmd_get_ext_fat_capabilites(adapter, &extfat_cmd);
if (!status) {
cfgs = (struct be_fat_conf_params *)(extfat_cmd.va +
sizeof(struct be_cmd_resp_hdr));
for (j = 0; j < le32_to_cpu(cfgs->module[0].num_modes); j++) {
if (cfgs->module[0].trace_lvl[j].mode == MODE_UART)
level = cfgs->module[0].trace_lvl[j].dbg_lvl;
}
}
pci_free_consistent(adapter->pdev, extfat_cmd.size, extfat_cmd.va,
extfat_cmd.dma);
err:
return level;
}
int be_cmd_get_ext_fat_capabilites(struct be_adapter *adapter,
struct be_dma_mem *cmd)
{

View File

@ -2060,6 +2060,8 @@ int be_cmd_set_hsw_config(struct be_adapter *adapter, u16 pvid, u32 domain,
int be_cmd_get_hsw_config(struct be_adapter *adapter, u16 *pvid, u32 domain,
u16 intf_id, u8 *mode);
int be_cmd_get_acpi_wol_cap(struct be_adapter *adapter);
int be_cmd_set_fw_log_level(struct be_adapter *adapter, u32 level);
int be_cmd_get_fw_log_level(struct be_adapter *adapter);
int be_cmd_get_ext_fat_capabilites(struct be_adapter *adapter,
struct be_dma_mem *cmd);
int be_cmd_set_ext_fat_capabilites(struct be_adapter *adapter,

View File

@ -904,73 +904,21 @@ static u32 be_get_msg_level(struct net_device *netdev)
{
struct be_adapter *adapter = netdev_priv(netdev);
if (lancer_chip(adapter)) {
dev_err(&adapter->pdev->dev, "Operation not supported\n");
return -EOPNOTSUPP;
}
return adapter->msg_enable;
}
static void be_set_fw_log_level(struct be_adapter *adapter, u32 level)
{
struct be_dma_mem extfat_cmd;
struct be_fat_conf_params *cfgs;
int status;
int i, j;
memset(&extfat_cmd, 0, sizeof(struct be_dma_mem));
extfat_cmd.size = sizeof(struct be_cmd_resp_get_ext_fat_caps);
extfat_cmd.va = pci_alloc_consistent(adapter->pdev, extfat_cmd.size,
&extfat_cmd.dma);
if (!extfat_cmd.va) {
dev_err(&adapter->pdev->dev, "%s: Memory allocation failure\n",
__func__);
goto err;
}
status = be_cmd_get_ext_fat_capabilites(adapter, &extfat_cmd);
if (!status) {
cfgs = (struct be_fat_conf_params *)(extfat_cmd.va +
sizeof(struct be_cmd_resp_hdr));
for (i = 0; i < le32_to_cpu(cfgs->num_modules); i++) {
u32 num_modes = le32_to_cpu(cfgs->module[i].num_modes);
for (j = 0; j < num_modes; j++) {
if (cfgs->module[i].trace_lvl[j].mode ==
MODE_UART)
cfgs->module[i].trace_lvl[j].dbg_lvl =
cpu_to_le32(level);
}
}
status = be_cmd_set_ext_fat_capabilites(adapter, &extfat_cmd,
cfgs);
if (status)
dev_err(&adapter->pdev->dev,
"Message level set failed\n");
} else {
dev_err(&adapter->pdev->dev, "Message level get failed\n");
}
pci_free_consistent(adapter->pdev, extfat_cmd.size, extfat_cmd.va,
extfat_cmd.dma);
err:
return;
}
static void be_set_msg_level(struct net_device *netdev, u32 level)
{
struct be_adapter *adapter = netdev_priv(netdev);
if (lancer_chip(adapter)) {
dev_err(&adapter->pdev->dev, "Operation not supported\n");
return;
}
if (adapter->msg_enable == level)
return;
if ((level & NETIF_MSG_HW) != (adapter->msg_enable & NETIF_MSG_HW))
be_set_fw_log_level(adapter, level & NETIF_MSG_HW ?
FW_LOG_LEVEL_DEFAULT : FW_LOG_LEVEL_FATAL);
if (BEx_chip(adapter))
be_cmd_set_fw_log_level(adapter, level & NETIF_MSG_HW ?
FW_LOG_LEVEL_DEFAULT :
FW_LOG_LEVEL_FATAL);
adapter->msg_enable = level;
return;

View File

@ -4302,47 +4302,9 @@ bool be_is_wol_supported(struct be_adapter *adapter)
!be_is_wol_excluded(adapter)) ? true : false;
}
u32 be_get_fw_log_level(struct be_adapter *adapter)
{
struct be_dma_mem extfat_cmd;
struct be_fat_conf_params *cfgs;
int status;
u32 level = 0;
int j;
if (lancer_chip(adapter))
return 0;
memset(&extfat_cmd, 0, sizeof(struct be_dma_mem));
extfat_cmd.size = sizeof(struct be_cmd_resp_get_ext_fat_caps);
extfat_cmd.va = pci_alloc_consistent(adapter->pdev, extfat_cmd.size,
&extfat_cmd.dma);
if (!extfat_cmd.va) {
dev_err(&adapter->pdev->dev, "%s: Memory allocation failure\n",
__func__);
goto err;
}
status = be_cmd_get_ext_fat_capabilites(adapter, &extfat_cmd);
if (!status) {
cfgs = (struct be_fat_conf_params *)(extfat_cmd.va +
sizeof(struct be_cmd_resp_hdr));
for (j = 0; j < le32_to_cpu(cfgs->module[0].num_modes); j++) {
if (cfgs->module[0].trace_lvl[j].mode == MODE_UART)
level = cfgs->module[0].trace_lvl[j].dbg_lvl;
}
}
pci_free_consistent(adapter->pdev, extfat_cmd.size, extfat_cmd.va,
extfat_cmd.dma);
err:
return level;
}
static int be_get_initial_config(struct be_adapter *adapter)
{
int status;
u32 level;
int status, level;
status = be_cmd_get_cntl_attributes(adapter);
if (status)
@ -4362,8 +4324,11 @@ static int be_get_initial_config(struct be_adapter *adapter)
/* Must be a power of 2 or else MODULO will BUG_ON */
adapter->be_get_temp_freq = 64;
level = be_get_fw_log_level(adapter);
adapter->msg_enable = level <= FW_LOG_LEVEL_DEFAULT ? NETIF_MSG_HW : 0;
if (BEx_chip(adapter)) {
level = be_cmd_get_fw_log_level(adapter);
adapter->msg_enable =
level <= FW_LOG_LEVEL_DEFAULT ? NETIF_MSG_HW : 0;
}
adapter->cfg_num_qs = netif_get_num_default_rss_queues();
return 0;