net: ena: add MAX_QUEUES_EXT get feature admin command
Add a new admin command to support different queue size for Tx/Rx queues (the change also support different SQ/CQ sizes) Signed-off-by: Arthur Kiyanovski <akiyano@amazon.com> Signed-off-by: Sameeh Jubran <sameehj@amazon.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Arthur Kiyanovski
David S. Miller
parent
f2dec9a276
commit
ba8ef506fb
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@ -64,6 +64,7 @@ enum ena_admin_aq_feature_id {
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ENA_ADMIN_LLQ = 4,
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ENA_ADMIN_EXTRA_PROPERTIES_STRINGS = 5,
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ENA_ADMIN_EXTRA_PROPERTIES_FLAGS = 6,
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ENA_ADMIN_MAX_QUEUES_EXT = 7,
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ENA_ADMIN_RSS_HASH_FUNCTION = 10,
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ENA_ADMIN_STATELESS_OFFLOAD_CONFIG = 11,
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ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG = 12,
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@ -425,7 +426,13 @@ struct ena_admin_get_set_feature_common_desc {
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/* as appears in ena_admin_aq_feature_id */
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u8 feature_id;
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u16 reserved16;
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/* The driver specifies the max feature version it supports and the
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* device responds with the currently supported feature version. The
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* field is zero based
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*/
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u8 feature_version;
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u8 reserved8;
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};
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struct ena_admin_device_attr_feature_desc {
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@ -535,6 +542,34 @@ struct ena_admin_feature_llq_desc {
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u32 max_tx_burst_size;
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};
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struct ena_admin_queue_ext_feature_fields {
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u32 max_tx_sq_num;
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u32 max_tx_cq_num;
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u32 max_rx_sq_num;
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u32 max_rx_cq_num;
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u32 max_tx_sq_depth;
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u32 max_tx_cq_depth;
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u32 max_rx_sq_depth;
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u32 max_rx_cq_depth;
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u32 max_tx_header_size;
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/* Maximum Descriptors number, including meta descriptor, allowed for
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* a single Tx packet
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*/
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u16 max_per_packet_tx_descs;
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/* Maximum Descriptors number allowed for a single Rx packet */
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u16 max_per_packet_rx_descs;
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};
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struct ena_admin_queue_feature_desc {
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u32 max_sq_num;
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@ -849,6 +884,19 @@ struct ena_admin_get_feat_cmd {
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u32 raw[11];
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};
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struct ena_admin_queue_ext_feature_desc {
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/* version */
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u8 version;
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u8 reserved1[3];
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union {
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struct ena_admin_queue_ext_feature_fields max_queue_ext;
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u32 raw[10];
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};
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};
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struct ena_admin_get_feat_resp {
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struct ena_admin_acq_common_desc acq_common_desc;
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@ -861,6 +909,8 @@ struct ena_admin_get_feat_resp {
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struct ena_admin_queue_feature_desc max_queue;
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struct ena_admin_queue_ext_feature_desc max_queue_ext;
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struct ena_admin_feature_aenq_desc aenq;
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struct ena_admin_get_feature_link_desc link;
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@ -929,7 +979,9 @@ struct ena_admin_aenq_common_desc {
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u16 syndrom;
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/* 0 : phase */
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/* 0 : phase
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* 7:1 : reserved - MBZ
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*/
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u8 flags;
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u8 reserved1[3];
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@ -978,7 +978,8 @@ static int ena_com_get_feature_ex(struct ena_com_dev *ena_dev,
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struct ena_admin_get_feat_resp *get_resp,
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enum ena_admin_aq_feature_id feature_id,
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dma_addr_t control_buf_dma_addr,
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u32 control_buff_size)
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u32 control_buff_size,
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u8 feature_ver)
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{
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struct ena_com_admin_queue *admin_queue;
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struct ena_admin_get_feat_cmd get_cmd;
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@ -1009,7 +1010,7 @@ static int ena_com_get_feature_ex(struct ena_com_dev *ena_dev,
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}
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get_cmd.control_buffer.length = control_buff_size;
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get_cmd.feat_common.feature_version = feature_ver;
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get_cmd.feat_common.feature_id = feature_id;
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ret = ena_com_execute_admin_command(admin_queue,
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@ -1029,13 +1030,15 @@ static int ena_com_get_feature_ex(struct ena_com_dev *ena_dev,
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static int ena_com_get_feature(struct ena_com_dev *ena_dev,
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struct ena_admin_get_feat_resp *get_resp,
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enum ena_admin_aq_feature_id feature_id)
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enum ena_admin_aq_feature_id feature_id,
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u8 feature_ver)
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{
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return ena_com_get_feature_ex(ena_dev,
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get_resp,
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feature_id,
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0,
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0);
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0,
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feature_ver);
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}
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static int ena_com_hash_key_allocate(struct ena_com_dev *ena_dev)
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@ -1095,7 +1098,7 @@ static int ena_com_indirect_table_allocate(struct ena_com_dev *ena_dev,
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int ret;
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ret = ena_com_get_feature(ena_dev, &get_resp,
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ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG);
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ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG, 0);
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if (unlikely(ret))
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return ret;
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@ -1515,7 +1518,7 @@ int ena_com_set_aenq_config(struct ena_com_dev *ena_dev, u32 groups_flag)
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struct ena_admin_get_feat_resp get_resp;
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int ret;
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ret = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_AENQ_CONFIG);
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ret = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_AENQ_CONFIG, 0);
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if (ret) {
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pr_info("Can't get aenq configuration\n");
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return ret;
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@ -1890,7 +1893,7 @@ void ena_com_destroy_io_queue(struct ena_com_dev *ena_dev, u16 qid)
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int ena_com_get_link_params(struct ena_com_dev *ena_dev,
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struct ena_admin_get_feat_resp *resp)
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{
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return ena_com_get_feature(ena_dev, resp, ENA_ADMIN_LINK_CONFIG);
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return ena_com_get_feature(ena_dev, resp, ENA_ADMIN_LINK_CONFIG, 0);
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}
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int ena_com_extra_properties_strings_init(struct ena_com_dev *ena_dev)
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@ -1916,7 +1919,7 @@ int ena_com_extra_properties_strings_init(struct ena_com_dev *ena_dev)
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rc = ena_com_get_feature_ex(ena_dev, &resp,
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ENA_ADMIN_EXTRA_PROPERTIES_STRINGS,
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extra_properties_strings->dma_addr,
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extra_properties_strings->size);
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extra_properties_strings->size, 0);
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if (rc) {
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pr_debug("Failed to get extra properties strings\n");
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goto err;
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@ -1946,7 +1949,7 @@ int ena_com_get_extra_properties_flags(struct ena_com_dev *ena_dev,
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struct ena_admin_get_feat_resp *resp)
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{
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return ena_com_get_feature(ena_dev, resp,
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ENA_ADMIN_EXTRA_PROPERTIES_FLAGS);
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ENA_ADMIN_EXTRA_PROPERTIES_FLAGS, 0);
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}
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int ena_com_get_dev_attr_feat(struct ena_com_dev *ena_dev,
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@ -1956,7 +1959,7 @@ int ena_com_get_dev_attr_feat(struct ena_com_dev *ena_dev,
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int rc;
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rc = ena_com_get_feature(ena_dev, &get_resp,
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ENA_ADMIN_DEVICE_ATTRIBUTES);
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ENA_ADMIN_DEVICE_ATTRIBUTES, 0);
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if (rc)
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return rc;
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@ -1964,17 +1967,34 @@ int ena_com_get_dev_attr_feat(struct ena_com_dev *ena_dev,
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sizeof(get_resp.u.dev_attr));
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ena_dev->supported_features = get_resp.u.dev_attr.supported_features;
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rc = ena_com_get_feature(ena_dev, &get_resp,
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ENA_ADMIN_MAX_QUEUES_NUM);
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if (rc)
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return rc;
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if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
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rc = ena_com_get_feature(ena_dev, &get_resp,
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ENA_ADMIN_MAX_QUEUES_EXT,
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ENA_FEATURE_MAX_QUEUE_EXT_VER);
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if (rc)
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return rc;
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memcpy(&get_feat_ctx->max_queues, &get_resp.u.max_queue,
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sizeof(get_resp.u.max_queue));
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ena_dev->tx_max_header_size = get_resp.u.max_queue.max_header_size;
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if (get_resp.u.max_queue_ext.version != ENA_FEATURE_MAX_QUEUE_EXT_VER)
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return -EINVAL;
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memcpy(&get_feat_ctx->max_queue_ext, &get_resp.u.max_queue_ext,
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sizeof(get_resp.u.max_queue_ext));
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ena_dev->tx_max_header_size =
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get_resp.u.max_queue_ext.max_queue_ext.max_tx_header_size;
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} else {
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rc = ena_com_get_feature(ena_dev, &get_resp,
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ENA_ADMIN_MAX_QUEUES_NUM, 0);
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memcpy(&get_feat_ctx->max_queues, &get_resp.u.max_queue,
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sizeof(get_resp.u.max_queue));
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ena_dev->tx_max_header_size =
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get_resp.u.max_queue.max_header_size;
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if (rc)
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return rc;
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}
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rc = ena_com_get_feature(ena_dev, &get_resp,
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ENA_ADMIN_AENQ_CONFIG);
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ENA_ADMIN_AENQ_CONFIG, 0);
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if (rc)
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return rc;
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@ -1982,7 +2002,7 @@ int ena_com_get_dev_attr_feat(struct ena_com_dev *ena_dev,
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sizeof(get_resp.u.aenq));
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rc = ena_com_get_feature(ena_dev, &get_resp,
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ENA_ADMIN_STATELESS_OFFLOAD_CONFIG);
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ENA_ADMIN_STATELESS_OFFLOAD_CONFIG, 0);
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if (rc)
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return rc;
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@ -1992,7 +2012,7 @@ int ena_com_get_dev_attr_feat(struct ena_com_dev *ena_dev,
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/* Driver hints isn't mandatory admin command. So in case the
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* command isn't supported set driver hints to 0
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*/
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rc = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_HW_HINTS);
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rc = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_HW_HINTS, 0);
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if (!rc)
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memcpy(&get_feat_ctx->hw_hints, &get_resp.u.hw_hints,
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@ -2003,7 +2023,7 @@ int ena_com_get_dev_attr_feat(struct ena_com_dev *ena_dev,
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else
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return rc;
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rc = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_LLQ);
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rc = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_LLQ, 0);
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if (!rc)
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memcpy(&get_feat_ctx->llq, &get_resp.u.llq,
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sizeof(get_resp.u.llq));
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@ -2240,7 +2260,7 @@ int ena_com_get_offload_settings(struct ena_com_dev *ena_dev,
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struct ena_admin_get_feat_resp resp;
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ret = ena_com_get_feature(ena_dev, &resp,
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ENA_ADMIN_STATELESS_OFFLOAD_CONFIG);
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ENA_ADMIN_STATELESS_OFFLOAD_CONFIG, 0);
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if (unlikely(ret)) {
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pr_err("Failed to get offload capabilities %d\n", ret);
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return ret;
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@ -2269,7 +2289,7 @@ int ena_com_set_hash_function(struct ena_com_dev *ena_dev)
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/* Validate hash function is supported */
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ret = ena_com_get_feature(ena_dev, &get_resp,
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ENA_ADMIN_RSS_HASH_FUNCTION);
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ENA_ADMIN_RSS_HASH_FUNCTION, 0);
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if (unlikely(ret))
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return ret;
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@ -2329,7 +2349,7 @@ int ena_com_fill_hash_function(struct ena_com_dev *ena_dev,
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rc = ena_com_get_feature_ex(ena_dev, &get_resp,
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ENA_ADMIN_RSS_HASH_FUNCTION,
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rss->hash_key_dma_addr,
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sizeof(*rss->hash_key));
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sizeof(*rss->hash_key), 0);
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if (unlikely(rc))
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return rc;
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@ -2381,7 +2401,7 @@ int ena_com_get_hash_function(struct ena_com_dev *ena_dev,
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rc = ena_com_get_feature_ex(ena_dev, &get_resp,
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ENA_ADMIN_RSS_HASH_FUNCTION,
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rss->hash_key_dma_addr,
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sizeof(*rss->hash_key));
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sizeof(*rss->hash_key), 0);
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if (unlikely(rc))
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return rc;
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@ -2406,7 +2426,7 @@ int ena_com_get_hash_ctrl(struct ena_com_dev *ena_dev,
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rc = ena_com_get_feature_ex(ena_dev, &get_resp,
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ENA_ADMIN_RSS_HASH_INPUT,
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rss->hash_ctrl_dma_addr,
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sizeof(*rss->hash_ctrl));
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sizeof(*rss->hash_ctrl), 0);
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if (unlikely(rc))
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return rc;
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@ -2642,7 +2662,7 @@ int ena_com_indirect_table_get(struct ena_com_dev *ena_dev, u32 *ind_tbl)
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rc = ena_com_get_feature_ex(ena_dev, &get_resp,
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ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG,
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rss->rss_ind_tbl_dma_addr,
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tbl_size);
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tbl_size, 0);
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if (unlikely(rc))
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return rc;
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@ -2857,7 +2877,7 @@ int ena_com_init_interrupt_moderation(struct ena_com_dev *ena_dev)
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int rc;
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rc = ena_com_get_feature(ena_dev, &get_resp,
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ENA_ADMIN_INTERRUPT_MODERATION);
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ENA_ADMIN_INTERRUPT_MODERATION, 0);
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if (rc) {
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if (rc == -EOPNOTSUPP) {
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@ -101,6 +101,8 @@
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#define ENA_HW_HINTS_NO_TIMEOUT 0xFFFF
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#define ENA_FEATURE_MAX_QUEUE_EXT_VER 1
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enum ena_intr_moder_level {
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ENA_INTR_MODER_LOWEST = 0,
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ENA_INTR_MODER_LOW,
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@ -389,6 +391,7 @@ struct ena_com_dev {
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struct ena_com_dev_get_features_ctx {
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struct ena_admin_queue_feature_desc max_queues;
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struct ena_admin_queue_ext_feature_desc max_queue_ext;
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struct ena_admin_device_attr_feature_desc dev_attr;
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struct ena_admin_feature_aenq_desc aenq;
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struct ena_admin_feature_offload_desc offload;
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