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drm/msm/dpu: add missing flush and fetch bits for DMA4/DMA5 planes 

Note that with this, DMA4/DMA5 are still non-functional, but at least
display *something* in modetest instead of nothing or underflow.

Fixes: efcd010772 ("drm/msm/dpu: add support for SM8550")
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD
Patchwork: https://patchwork.freedesktop.org/patch/545548/
Link: https://lore.kernel.org/r/20230704160106.26055-1-jonathan@marek.ca
Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
This commit is contained in:
Jonathan Marek 2023-07-04 12:01:04 -04:00 committed by Abhinav Kumar
parent a85c238c5c
commit ba7a94ea73
1 changed files with 7 additions and 1 deletions
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8
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
View File

@ -51,7 +51,7 @@
static const u32 fetch_tbl[SSPP_MAX] = {CTL_INVALID_BIT, 16, 17, 18, 19,
CTL_INVALID_BIT, CTL_INVALID_BIT, CTL_INVALID_BIT, CTL_INVALID_BIT, 0,
1, 2, 3, CTL_INVALID_BIT, CTL_INVALID_BIT};
1, 2, 3, 4, 5};
static int _mixer_stages(const struct dpu_lm_cfg *mixer, int count,
enum dpu_lm lm)
@ -198,6 +198,12 @@ static void dpu_hw_ctl_update_pending_flush_sspp(struct dpu_hw_ctl *ctx,
case SSPP_DMA3:
ctx->pending_flush_mask |= BIT(25);
break;
case SSPP_DMA4:
ctx->pending_flush_mask |= BIT(13);
break;
case SSPP_DMA5:
ctx->pending_flush_mask |= BIT(14);
break;
case SSPP_CURSOR0:
ctx->pending_flush_mask |= BIT(22);
break;