dt-bindings: pinctrl: Add bindings for Actions Semi S700 SoC
Add pinctrl and pio bindings for Actions Semi S700 SoC. Signed-off-by: Parthiban Nallathambi <pn@denx.de> Signed-off-by: Saravanan Sekar <sravanhome@gmail.com> Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Saravanan Sekar
Linus Walleij
parent
f3f7af952a
commit
ba54e3005d
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Actions Semi S700 Pin Controller
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This binding describes the pin controller found in the S700 SoC.
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Required Properties:
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- compatible: Should be "actions,s700-pinctrl"
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- reg: Should contain the register base address and size of
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the pin controller.
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- clocks: phandle of the clock feeding the pin controller
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- gpio-controller: Marks the device node as a GPIO controller.
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- gpio-ranges: Specifies the mapping between gpio controller and
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pin-controller pins.
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- #gpio-cells: Should be two. The first cell is the gpio pin number
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and the second cell is used for optional parameters.
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- interrupt-controller: Marks the device node as an interrupt controller.
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- #interrupt-cells: Specifies the number of cells needed to encode an
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interrupt. Shall be set to 2. The first cell
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defines the interrupt number, the second encodes
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the trigger flags described in
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bindings/interrupt-controller/interrupts.txt
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- interrupts: The interrupt outputs from the controller. There is one GPIO
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interrupt per GPIO bank. The number of interrupts listed depends
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on the number of GPIO banks on the SoC. The interrupts must be
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ordered by bank, starting with bank 0.
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Please refer to pinctrl-bindings.txt in this directory for details of the
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common pinctrl bindings used by client devices, including the meaning of the
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phrase "pin configuration node".
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The pin configuration nodes act as a container for an arbitrary number of
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subnodes. Each of these subnodes represents some desired configuration for a
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pin, a group, or a list of pins or groups. This configuration can include the
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mux function to select on those group(s), and various pin configuration
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parameters, such as pull-up, drive strength, etc.
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PIN CONFIGURATION NODES:
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The name of each subnode is not important; all subnodes should be enumerated
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and processed purely based on their content.
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Each subnode only affects those parameters that are explicitly listed. In
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other words, a subnode that lists a mux function but no pin configuration
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parameters implies no information about any pin configuration parameters.
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Similarly, a pin subnode that describes a pullup parameter implies no
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information about e.g. the mux function.
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Pinmux functions are available only for the pin groups while pinconf
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parameters are available for both pin groups and individual pins.
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The following generic properties as defined in pinctrl-bindings.txt are valid
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to specify in a pin configuration subnode:
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Required Properties:
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- pins: An array of strings, each string containing the name of a pin.
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These pins are used for selecting the pull control and schmitt
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trigger parameters. The following are the list of pins
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available:
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eth_txd0, eth_txd1, eth_txd2, eth_txd3, eth_txen, eth_rxer,
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eth_crs_dv, eth_rxd1, eth_rxd0, eth_rxd2, eth_rxd3, eth_ref_clk,
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eth_mdc, eth_mdio, sirq0, sirq1, sirq2, i2s_d0, i2s_bclk0,
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i2s_lrclk0, i2s_mclk0, i2s_d1, i2s_bclk1, i2s_lrclk1, i2s_mclk1,
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pcm1_in, pcm1_clk, pcm1_sync, pcm1_out, ks_in0, ks_in1, ks_in2,
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ks_in3, ks_out0, ks_out1, ks_out2, lvds_oep, lvds_oen, lvds_odp,
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lvds_odn, lvds_ocp, lvds_ocn, lvds_obp, lvds_obn, lvds_oap,
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lvds_oan, lvds_eep, lvds_een, lvds_edp, lvds_edn, lvds_ecp,
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lvds_ecn, lvds_ebp, lvds_ebn, lvds_eap, lvds_ean, lcd0_d18,
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lcd0_d2, dsi_dp3, dsi_dn3, dsi_dp1, dsi_dn1, dsi_cp, dsi_cn,
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dsi_dp0, dsi_dn0, dsi_dp2, dsi_dn2, sd0_d0, sd0_d1, sd0_d2,
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sd0_d3, sd1_d0, sd1_d1, sd1_d2, sd1_d3, sd0_cmd, sd0_clk,
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sd1_cmd, sd1_clk, spi0_ss, spi0_miso, uart0_rx, uart0_tx,
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uart2_rx, uart2_tx, uart2_rtsb, uart2_ctsb, uart3_rx, uart3_tx,
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uart3_rtsb, uart3_ctsb, i2c0_sclk, i2c0_sdata, i2c1_sclk,
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i2c1_sdata, i2c2_sdata, csi_dn0, csi_dp0, csi_dn1, csi_dp1,
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csi_cn, csi_cp, csi_dn2, csi_dp2, csi_dn3, csi_dp3,
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sensor0_pclk, sensor0_ckout, dnand_d0, dnand_d1, dnand_d2,
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dnand_d3, dnand_d4, dnand_d5, dnand_d6, dnand_d7, dnand_wrb,
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dnand_rdb, dnand_rdbn, dnand_dqs, dnand_dqsn, dnand_rb0,
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dnand_ale, dnand_cle, dnand_ceb0, dnand_ceb1, dnand_ceb2,
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dnand_ceb3, porb, clko_25m, bsel, pkg0, pkg1, pkg2, pkg3
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- groups: An array of strings, each string containing the name of a pin
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group. These pin groups are used for selecting the pinmux
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functions.
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rgmii_txd23_mfp, rgmii_rxd2_mfp, rgmii_rxd3_mfp, lcd0_d18_mfp,
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rgmii_txd01_mfp, rgmii_txd0_mfp, rgmii_txd1_mfp, rgmii_txen_mfp,
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rgmii_rxen_mfp, rgmii_rxd1_mfp, rgmii_rxd0_mfp, rgmii_ref_clk_mfp,
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i2s_d0_mfp, i2s_pcm1_mfp, i2s0_pcm0_mfp, i2s1_pcm0_mfp,
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i2s_d1_mfp, ks_in2_mfp, ks_in1_mfp, ks_in0_mfp, ks_in3_mfp,
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ks_out0_mfp, ks_out1_mfp, ks_out2_mfp, lvds_o_pn_mfp, dsi_dn0_mfp,
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dsi_dp2_mfp, lcd0_d2_mfp, dsi_dp3_mfp, dsi_dn3_mfp, dsi_dp0_mfp,
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lvds_ee_pn_mfp, uart2_rx_tx_mfp, spi0_i2c_pcm_mfp, dsi_dnp1_cp_d2_mfp,
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dsi_dnp1_cp_d17_mfp, lvds_e_pn_mfp, dsi_dn2_mfp, uart2_rtsb_mfp,
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uart2_ctsb_mfp, uart3_rtsb_mfp, uart3_ctsb_mfp, sd0_d0_mfp, sd0_d1_mfp,
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sd0_d2_d3_mfp, sd1_d0_d3_mfp, sd0_cmd_mfp, sd0_clk_mfp, sd1_cmd_mfp,
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uart0_rx_mfp, clko_25m_mfp, csi_cn_cp_mfp, sens0_ckout_mfp, uart0_tx_mfp,
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i2c0_mfp, csi_dn_dp_mfp, sen0_pclk_mfp, pcm1_in_mfp, pcm1_clk_mfp,
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pcm1_sync_mfp, pcm1_out_mfp, dnand_data_wr_mfp, dnand_acle_ce0_mfp,
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nand_ceb2_mfp, nand_ceb3_mfp
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These pin groups are used for selecting the drive strength
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parameters.
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sirq_drv, rgmii_txd23_drv, rgmii_rxd23_drv, rgmii_txd01_txen_drv,
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rgmii_rxer_drv, rgmii_crs_drv, rgmii_rxd10_drv, rgmii_ref_clk_drv,
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smi_mdc_mdio_drv, i2s_d0_drv, i2s_bclk0_drv, i2s3_drv, i2s13_drv,
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pcm1_drv, ks_in_drv, ks_out_drv, lvds_all_drv, lcd_d18_d2_drv,
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dsi_all_drv, sd0_d0_d3_drv, sd0_cmd_drv, sd0_clk_drv, spi0_all_drv,
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uart0_rx_drv, uart0_tx_drv, uart2_all_drv, i2c0_all_drv, i2c12_all_drv,
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sens0_pclk_drv, sens0_ckout_drv, uart3_all_drv
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- function: An array of strings, each string containing the name of the
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pinmux functions. These functions can only be selected by
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the corresponding pin groups. The following are the list of
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pinmux functions available:
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nor, eth_rgmii, eth_sgmii, spi0, spi1, spi2, spi3, seNs0, sens1,
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uart0, uart1, uart2, uart3, uart4, uart5, uart6, i2s0, i2s1,
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pcm1, pcm0, ks, jtag, pwm0, pwm1, pwm2, pwm3, pwm4, pwm5, p0,
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sd0, sd1, sd2, i2c0, i2c1, i2c2, i2c3, dsi, lvds, usb30,
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clko_25m, mipi_csi, nand, spdif, sirq0, sirq1, sirq2, bt, lcd0
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Optional Properties:
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- bias-pull-down: No arguments. The specified pins should be configured as
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pull down.
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- bias-pull-up: No arguments. The specified pins should be configured as
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pull up.
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- input-schmitt-enable: No arguments: Enable schmitt trigger for the specified
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pins
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- input-schmitt-disable: No arguments: Disable schmitt trigger for the specified
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pins
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- drive-strength: Integer. Selects the drive strength for the specified
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pins in mA.
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Valid values are:
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<2>
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<4>
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<8>
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<12>
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Example:
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pinctrl: pinctrl@e01b0000 {
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compatible = "actions,s700-pinctrl";
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reg = <0x0 0xe01b0000 0x0 0x1000>;
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clocks = <&cmu CLK_GPIO>;
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gpio-controller;
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gpio-ranges = <&pinctrl 0 0 136>;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
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uart3-default: uart3-default {
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pinmux {
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groups = "uart3_rtsb_mfp", "uart3_ctsb_mfp";
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function = "uart3";
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};
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pinconf {
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groups = "uart3_all_drv";
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drive-strength = <2>;
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};
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};
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};
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