drm/amdkfd: correct sienna_cichlid SDMA RLC register offset error
1.correct KFD SDMA RLC queue register offset error. (all sdma rlc register offset is base on SDMA0.RLC0_RLC0_RB_CNTL) 2.HQD_N_REGS (19+6+7+12) 12: the 2 more resgisters than navi1x (SDMAx_RLCy_MIDCMD_DATA{9,10}) the patch also can be fixed NULL pointer issue when read /sys/kernel/debug/kfd/hqds on sienna_cichlid chip. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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@ -156,16 +156,16 @@ static uint32_t get_sdma_rlc_reg_offset(struct amdgpu_device *adev,
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mmSDMA0_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL;
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mmSDMA0_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL;
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break;
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break;
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case 1:
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case 1:
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sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA1, 0,
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sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0,
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mmSDMA1_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL;
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mmSDMA1_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL;
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break;
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break;
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case 2:
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case 2:
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sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA2, 0,
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sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0,
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mmSDMA2_RLC0_RB_CNTL) - mmSDMA2_RLC0_RB_CNTL;
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mmSDMA2_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL;
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break;
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break;
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case 3:
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case 3:
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sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA3, 0,
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sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0,
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mmSDMA3_RLC0_RB_CNTL) - mmSDMA2_RLC0_RB_CNTL;
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mmSDMA3_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL;
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break;
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break;
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}
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}
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@ -450,7 +450,7 @@ static int hqd_sdma_dump_v10_3(struct kgd_dev *kgd,
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engine_id, queue_id);
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engine_id, queue_id);
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uint32_t i = 0, reg;
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uint32_t i = 0, reg;
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#undef HQD_N_REGS
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#undef HQD_N_REGS
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#define HQD_N_REGS (19+6+7+10)
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#define HQD_N_REGS (19+6+7+12)
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*dump = kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL);
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*dump = kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL);
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if (*dump == NULL)
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if (*dump == NULL)
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