SoC: fixes for 5.18, part 1
The introduction of vmap-stack on 32-bit arm caused a regression on a few omap3/omap4 machines that pass a stack variable into a firmware interface. The early pre-ACPI AMD Seattle machines have been broken for a while, Ard Biesheuvel has a series to bring them back for now. A few machines with multiple DMA channels used on a device have the channels in the wrong order according to the binding, which causes a harmless warning. Reversing the order is easier than fixing the tools to suppress the warning. -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmJGyNIACgkQmmx57+YA GNmThA//XLo6KAsI6/9LaiXFyTOLcaHRTlomRfgdhjTHe4jOMhBQ9SaxLcl3ocQa bqk3uG8CDQC240vCWw8kM+2UDWCwu4Z2lpJMM/Rmyz6H5vxk0s5ZdNeEDMogv6Gl /kzrmNuGdgYKifVNRh7oGpPSaP2vzcyzFetz0mcoZODDdvHjX9ci/6PeXnjhpXXd EkbKh9AlgAeqet0elLj3Vf/MxcwA7d7nLP5OcslPL0cfhrDi/+H/p0isKmXIl/S0 d/Lp5f5yXtyOtzqBh1VDJQ4u6+YwesxoWGRyjCmnEFl2MCOY8zTlxCa5q+InWV9s q2+wEWulGrk3SeI8LmUezNSdGs8UAlA659OtF0LWFKH79oLf4ug/qni2bTeNgPev CAhbyZJSeKk4JEdsFE2uhIPKKrDLmlwLQ6cY+Qz+EUDGfz1/wGaqyMk75IzMLW1q A72xEXoiMCTfN0faN2WiwglfUNjiR+JJIqTd0G+FOyNFjuKUyHU0xt+fTXnACoee VTxOTN13BfEGcWKSRRHt81/5jovSAK+0niV0InSZwcsH818LgPX+JsC3Z0DpdM5e Uq7ox9p7Gj1Y48SjQe09RmdGf+Jks17IHXMgDxt0lxTP1k/qhtDicKG+8p8Iwpu6 N2UwkcJPhDsFeZNQJvFLUrzHcU1QSF/CFGi2mTmRXTN62d+ssMo= =aPjb -----END PGP SIGNATURE----- Merge tag 'soc-fixes-5.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARM SoC fixes from Arnd BergmannL "The introduction of vmap-stack on 32-bit arm caused a regression on a few omap3/omap4 machines that pass a stack variable into a firmware interface. The early pre-ACPI AMD Seattle machines have been broken for a while, Ard Biesheuvel has a series to bring them back for now. A few machines with multiple DMA channels used on a device have the channels in the wrong order according to the binding, which causes a harmless warning. Reversing the order is easier than fixing the tools to suppress the warning" * tag 'soc-fixes-5.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: arm64: dts: ls1046a: Update i2c node dma properties arm64: dts: ls1043a: Update i2c dma properties ARM: dts: spear1340: Update serial node properties ARM: dts: spear13xx: Update SPI dma properties ARM: OMAP2+: Fix regression for smc calls for vmap stack dt: amd-seattle: add a description of the CPUs and caches dt: amd-seattle: disable IPMI controller and some GPIO blocks on B0 dt: amd-seattle: add description of the SATA/CCP SMMUs dt: amd-seattle: add a description of the PCIe SMMU dt: amd-seattle: fix PCIe legacy interrupt routing dt: amd-seattle: upgrade AMD Seattle XGBE to new SMMU binding dt: amd-seattle: remove Overdrive revision A0 support dt: amd-seattle: remove Husky platform
This commit is contained in:
Linus Torvalds
commit
ba2d6201a9
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|
@ -134,9 +134,9 @@
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reg = <0xb4100000 0x1000>;
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interrupts = <0 105 0x4>;
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status = "disabled";
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dmas = <&dwdma0 12 0 1>,
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<&dwdma0 13 1 0>;
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dma-names = "tx", "rx";
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dmas = <&dwdma0 13 0 1>,
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<&dwdma0 12 1 0>;
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dma-names = "rx", "tx";
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};
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thermal@e07008c4 {
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|
|
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@ -284,9 +284,9 @@
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#size-cells = <0>;
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interrupts = <0 31 0x4>;
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status = "disabled";
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dmas = <&dwdma0 4 0 0>,
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<&dwdma0 5 0 0>;
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dma-names = "tx", "rx";
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dmas = <&dwdma0 5 0 0>,
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<&dwdma0 4 0 0>;
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dma-names = "rx", "tx";
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};
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rtc@e0580000 {
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@ -59,8 +59,13 @@ static void __init omap_optee_init_check(void)
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u32 omap_secure_dispatcher(u32 idx, u32 flag, u32 nargs, u32 arg1, u32 arg2,
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u32 arg3, u32 arg4)
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{
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static u32 buf[NR_CPUS][5];
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u32 *param;
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int cpu;
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u32 ret;
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u32 param[5];
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cpu = get_cpu();
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param = buf[cpu];
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param[0] = nargs;
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param[1] = arg1;
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@ -76,6 +81,8 @@ u32 omap_secure_dispatcher(u32 idx, u32 flag, u32 nargs, u32 arg1, u32 arg2,
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outer_clean_range(__pa(param), __pa(param + 5));
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ret = omap_smc2(idx, flag, __pa(param));
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put_cpu();
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return ret;
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}
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@ -119,8 +126,8 @@ phys_addr_t omap_secure_ram_mempool_base(void)
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#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
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u32 omap3_save_secure_ram(void __iomem *addr, int size)
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{
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static u32 param[5];
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u32 ret;
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u32 param[5];
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if (size != OMAP3_SAVE_SECURE_RAM_SZ)
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return OMAP3_SAVE_SECURE_RAM_SZ;
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@ -153,8 +160,8 @@ u32 omap3_save_secure_ram(void __iomem *addr, int size)
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u32 rx51_secure_dispatcher(u32 idx, u32 process, u32 flag, u32 nargs,
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u32 arg1, u32 arg2, u32 arg3, u32 arg4)
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{
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static u32 param[5];
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u32 ret;
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u32 param[5];
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param[0] = nargs+1; /* RX-51 needs number of arguments + 1 */
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param[1] = arg1;
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@ -1,4 +1,2 @@
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# SPDX-License-Identifier: GPL-2.0
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dtb-$(CONFIG_ARCH_SEATTLE) += amd-overdrive.dtb \
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amd-overdrive-rev-b0.dtb amd-overdrive-rev-b1.dtb \
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husky.dtb
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dtb-$(CONFIG_ARCH_SEATTLE) += amd-overdrive-rev-b0.dtb amd-overdrive-rev-b1.dtb
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@ -9,6 +9,7 @@
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/dts-v1/;
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/include/ "amd-seattle-soc.dtsi"
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/include/ "amd-seattle-cpus.dtsi"
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/ {
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model = "AMD Seattle (Rev.B0) Development Board (Overdrive)";
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@ -36,14 +37,6 @@
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status = "ok";
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};
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&gpio2 {
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status = "ok";
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};
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&gpio3 {
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status = "ok";
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};
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&gpio4 {
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status = "ok";
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};
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@ -79,10 +72,6 @@
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};
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};
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&ipmi_kcs {
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status = "ok";
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};
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&smb0 {
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/include/ "amd-seattle-xgbe-b.dtsi"
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};
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|
|
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@ -9,6 +9,7 @@
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/dts-v1/;
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/include/ "amd-seattle-soc.dtsi"
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/include/ "amd-seattle-cpus.dtsi"
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/ {
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model = "AMD Seattle (Rev.B1) Development Board (Overdrive)";
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|
|
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@ -1,66 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* DTS file for AMD Seattle Overdrive Development Board
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*
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* Copyright (C) 2014 Advanced Micro Devices, Inc.
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*/
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/dts-v1/;
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/include/ "amd-seattle-soc.dtsi"
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/ {
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model = "AMD Seattle Development Board (Overdrive)";
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compatible = "amd,seattle-overdrive", "amd,seattle";
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|
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chosen {
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stdout-path = &serial0;
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};
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};
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|
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&ccp0 {
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status = "ok";
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};
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&gpio0 {
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status = "ok";
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};
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&gpio1 {
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status = "ok";
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};
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|
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&i2c0 {
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status = "ok";
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};
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&pcie0 {
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status = "ok";
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};
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&spi0 {
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status = "ok";
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};
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&spi1 {
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status = "ok";
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sdcard0: sdcard@0 {
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compatible = "mmc-spi-slot";
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reg = <0>;
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spi-max-frequency = <20000000>;
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voltage-ranges = <3200 3400>;
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gpios = <&gpio0 7 0>;
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interrupt-parent = <&gpio0>;
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interrupts = <7 3>;
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pl022,hierarchy = <0>;
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pl022,interface = <0>;
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pl022,com-mode = <0x0>;
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pl022,rx-level-trig = <0>;
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pl022,tx-level-trig = <0>;
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};
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};
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&v2m0 {
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arm,msi-base-spi = <64>;
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arm,msi-num-spis = <256>;
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};
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@ -0,0 +1,224 @@
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// SPDX-License-Identifier: GPL-2.0
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/ {
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cpus {
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#address-cells = <0x1>;
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#size-cells = <0x0>;
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&CPU0>;
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};
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core1 {
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cpu = <&CPU1>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&CPU2>;
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};
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core1 {
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cpu = <&CPU3>;
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};
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};
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cluster2 {
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core0 {
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cpu = <&CPU4>;
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};
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core1 {
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cpu = <&CPU5>;
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};
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};
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cluster3 {
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core0 {
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cpu = <&CPU6>;
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};
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core1 {
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cpu = <&CPU7>;
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};
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};
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};
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x0>;
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enable-method = "psci";
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i-cache-size = <0xC000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>;
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l2-cache = <&L2_0>;
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|
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};
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CPU1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x1>;
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enable-method = "psci";
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|
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i-cache-size = <0xC000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>;
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l2-cache = <&L2_0>;
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};
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|
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CPU2: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x100>;
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enable-method = "psci";
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|
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i-cache-size = <0xC000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>;
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l2-cache = <&L2_1>;
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};
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CPU3: cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x101>;
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enable-method = "psci";
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i-cache-size = <0xC000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>;
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l2-cache = <&L2_1>;
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};
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CPU4: cpu@200 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x200>;
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enable-method = "psci";
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|
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i-cache-size = <0xC000>;
|
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i-cache-line-size = <64>;
|
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i-cache-sets = <256>;
|
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>;
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l2-cache = <&L2_2>;
|
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};
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|
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CPU5: cpu@201 {
|
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device_type = "cpu";
|
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compatible = "arm,cortex-a57";
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reg = <0x201>;
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enable-method = "psci";
|
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|
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i-cache-size = <0xC000>;
|
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i-cache-line-size = <64>;
|
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i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
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d-cache-line-size = <64>;
|
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d-cache-sets = <256>;
|
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l2-cache = <&L2_2>;
|
||||
};
|
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|
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CPU6: cpu@300 {
|
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device_type = "cpu";
|
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compatible = "arm,cortex-a57";
|
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reg = <0x300>;
|
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enable-method = "psci";
|
||||
|
||||
i-cache-size = <0xC000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
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d-cache-sets = <256>;
|
||||
l2-cache = <&L2_3>;
|
||||
};
|
||||
|
||||
CPU7: cpu@301 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x301>;
|
||||
enable-method = "psci";
|
||||
|
||||
i-cache-size = <0xC000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <256>;
|
||||
l2-cache = <&L2_3>;
|
||||
};
|
||||
};
|
||||
|
||||
L2_0: l2-cache0 {
|
||||
cache-size = <0x100000>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <1024>;
|
||||
cache-unified;
|
||||
next-level-cache = <&L3>;
|
||||
};
|
||||
|
||||
L2_1: l2-cache1 {
|
||||
cache-size = <0x100000>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <1024>;
|
||||
cache-unified;
|
||||
next-level-cache = <&L3>;
|
||||
};
|
||||
|
||||
L2_2: l2-cache2 {
|
||||
cache-size = <0x100000>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <1024>;
|
||||
cache-unified;
|
||||
next-level-cache = <&L3>;
|
||||
};
|
||||
|
||||
L2_3: l2-cache3 {
|
||||
cache-size = <0x100000>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <1024>;
|
||||
cache-unified;
|
||||
next-level-cache = <&L3>;
|
||||
};
|
||||
|
||||
L3: l3-cache {
|
||||
cache-level = <3>;
|
||||
cache-size = <0x800000>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <8192>;
|
||||
cache-unified;
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,cortex-a57-pmu";
|
||||
interrupts = <0x0 0x7 0x4>,
|
||||
<0x0 0x8 0x4>,
|
||||
<0x0 0x9 0x4>,
|
||||
<0x0 0xa 0x4>,
|
||||
<0x0 0xb 0x4>,
|
||||
<0x0 0xc 0x4>,
|
||||
<0x0 0xd 0x4>,
|
||||
<0x0 0xe 0x4>;
|
||||
interrupt-affinity = <&CPU0>,
|
||||
<&CPU1>,
|
||||
<&CPU2>,
|
||||
<&CPU3>,
|
||||
<&CPU4>,
|
||||
<&CPU5>,
|
||||
<&CPU6>,
|
||||
<&CPU7>;
|
||||
};
|
||||
};
|
||||
|
|
@ -38,18 +38,6 @@
|
|||
<1 10 0xff04>;
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,armv8-pmuv3";
|
||||
interrupts = <0 7 4>,
|
||||
<0 8 4>,
|
||||
<0 9 4>,
|
||||
<0 10 4>,
|
||||
<0 11 4>,
|
||||
<0 12 4>,
|
||||
<0 13 4>,
|
||||
<0 14 4>;
|
||||
};
|
||||
|
||||
smb0: smb {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
|
|
@ -70,6 +58,7 @@
|
|||
reg = <0 0xe0300000 0 0xf0000>;
|
||||
interrupts = <0 355 4>;
|
||||
clocks = <&sataclk_333mhz>;
|
||||
iommus = <&sata0_smmu 0x0 0x1f>;
|
||||
dma-coherent;
|
||||
};
|
||||
|
||||
|
|
@ -80,6 +69,27 @@
|
|||
reg = <0 0xe0d00000 0 0xf0000>;
|
||||
interrupts = <0 354 4>;
|
||||
clocks = <&sataclk_333mhz>;
|
||||
iommus = <&sata1_smmu 0x0e>,
|
||||
<&sata1_smmu 0x0f>,
|
||||
<&sata1_smmu 0x1e>;
|
||||
dma-coherent;
|
||||
};
|
||||
|
||||
sata0_smmu: iommu@e0200000 {
|
||||
compatible = "arm,mmu-401";
|
||||
reg = <0 0xe0200000 0 0x10000>;
|
||||
#global-interrupts = <1>;
|
||||
interrupts = <0 332 4>, <0 332 4>;
|
||||
#iommu-cells = <2>;
|
||||
dma-coherent;
|
||||
};
|
||||
|
||||
sata1_smmu: iommu@e0c00000 {
|
||||
compatible = "arm,mmu-401";
|
||||
reg = <0 0xe0c00000 0 0x10000>;
|
||||
#global-interrupts = <1>;
|
||||
interrupts = <0 331 4>, <0 331 4>;
|
||||
#iommu-cells = <1>;
|
||||
dma-coherent;
|
||||
};
|
||||
|
||||
|
|
@ -201,6 +211,10 @@
|
|||
reg = <0 0xe0100000 0 0x10000>;
|
||||
interrupts = <0 3 4>;
|
||||
dma-coherent;
|
||||
iommus = <&sata1_smmu 0x00>,
|
||||
<&sata1_smmu 0x02>,
|
||||
<&sata1_smmu 0x40>,
|
||||
<&sata1_smmu 0x42>;
|
||||
};
|
||||
|
||||
pcie0: pcie@f0000000 {
|
||||
|
|
@ -213,12 +227,22 @@
|
|||
msi-parent = <&v2m0>;
|
||||
reg = <0 0xf0000000 0 0x10000000>;
|
||||
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||
interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
|
||||
interrupt-map =
|
||||
<0x1000 0x0 0x0 0x1 &gic0 0x0 0x0 0x0 0x120 0x1>,
|
||||
<0x1000 0x0 0x0 0x2 &gic0 0x0 0x0 0x0 0x121 0x1>,
|
||||
<0x1000 0x0 0x0 0x3 &gic0 0x0 0x0 0x0 0x122 0x1>,
|
||||
<0x1000 0x0 0x0 0x4 &gic0 0x0 0x0 0x0 0x123 0x1>;
|
||||
<0x1100 0x0 0x0 0x1 &gic0 0x0 0x0 0x0 0x120 0x1>,
|
||||
<0x1100 0x0 0x0 0x2 &gic0 0x0 0x0 0x0 0x121 0x1>,
|
||||
<0x1100 0x0 0x0 0x3 &gic0 0x0 0x0 0x0 0x122 0x1>,
|
||||
<0x1100 0x0 0x0 0x4 &gic0 0x0 0x0 0x0 0x123 0x1>,
|
||||
|
||||
<0x1200 0x0 0x0 0x1 &gic0 0x0 0x0 0x0 0x124 0x1>,
|
||||
<0x1200 0x0 0x0 0x2 &gic0 0x0 0x0 0x0 0x125 0x1>,
|
||||
<0x1200 0x0 0x0 0x3 &gic0 0x0 0x0 0x0 0x126 0x1>,
|
||||
<0x1200 0x0 0x0 0x4 &gic0 0x0 0x0 0x0 0x127 0x1>,
|
||||
|
||||
<0x1300 0x0 0x0 0x1 &gic0 0x0 0x0 0x0 0x128 0x1>,
|
||||
<0x1300 0x0 0x0 0x2 &gic0 0x0 0x0 0x0 0x129 0x1>,
|
||||
<0x1300 0x0 0x0 0x3 &gic0 0x0 0x0 0x0 0x12a 0x1>,
|
||||
<0x1300 0x0 0x0 0x4 &gic0 0x0 0x0 0x0 0x12b 0x1>;
|
||||
|
||||
dma-coherent;
|
||||
dma-ranges = <0x43000000 0x0 0x0 0x0 0x0 0x100 0x0>;
|
||||
|
|
@ -227,8 +251,18 @@
|
|||
<0x01000000 0x00 0x00000000 0x00 0xefff0000 0x00 0x00010000>,
|
||||
/* 32-bit MMIO (size=2G) */
|
||||
<0x02000000 0x00 0x40000000 0x00 0x40000000 0x00 0x80000000>,
|
||||
/* 64-bit MMIO (size= 124G) */
|
||||
/* 64-bit MMIO (size= 508G) */
|
||||
<0x03000000 0x01 0x00000000 0x01 0x00000000 0x7f 0x00000000>;
|
||||
iommu-map = <0x0 &pcie_smmu 0x0 0x10000>;
|
||||
};
|
||||
|
||||
pcie_smmu: iommu@e0a00000 {
|
||||
compatible = "arm,mmu-401";
|
||||
reg = <0 0xe0a00000 0 0x10000>;
|
||||
#global-interrupts = <1>;
|
||||
interrupts = <0 333 4>, <0 333 4>;
|
||||
#iommu-cells = <1>;
|
||||
dma-coherent;
|
||||
};
|
||||
|
||||
/* Perf CCN504 PMU */
|
||||
|
|
|
|||
|
|
@ -55,7 +55,7 @@
|
|||
clocks = <&xgmacclk0_dma_250mhz>, <&xgmacclk0_ptp_250mhz>;
|
||||
clock-names = "dma_clk", "ptp_clk";
|
||||
phy-mode = "xgmii";
|
||||
#stream-id-cells = <16>;
|
||||
iommus = <&xgmac0_smmu 0x00 0x17>; /* 0-7, 16-23 */
|
||||
dma-coherent;
|
||||
};
|
||||
|
||||
|
|
@ -81,11 +81,11 @@
|
|||
clocks = <&xgmacclk1_dma_250mhz>, <&xgmacclk1_ptp_250mhz>;
|
||||
clock-names = "dma_clk", "ptp_clk";
|
||||
phy-mode = "xgmii";
|
||||
#stream-id-cells = <16>;
|
||||
iommus = <&xgmac1_smmu 0x00 0x17>; /* 0-7, 16-23 */
|
||||
dma-coherent;
|
||||
};
|
||||
|
||||
xgmac0_smmu: smmu@e0600000 {
|
||||
xgmac0_smmu: iommu@e0600000 {
|
||||
compatible = "arm,mmu-401";
|
||||
reg = <0 0xe0600000 0 0x10000>;
|
||||
#global-interrupts = <1>;
|
||||
|
|
@ -94,14 +94,11 @@
|
|||
*/
|
||||
<0 336 4>,
|
||||
<0 336 4>;
|
||||
|
||||
mmu-masters = <&xgmac0
|
||||
0 1 2 3 4 5 6 7
|
||||
16 17 18 19 20 21 22 23
|
||||
>;
|
||||
#iommu-cells = <2>;
|
||||
dma-coherent;
|
||||
};
|
||||
|
||||
xgmac1_smmu: smmu@e0800000 {
|
||||
xgmac1_smmu: iommu@e0800000 {
|
||||
compatible = "arm,mmu-401";
|
||||
reg = <0 0xe0800000 0 0x10000>;
|
||||
#global-interrupts = <1>;
|
||||
|
|
@ -110,9 +107,6 @@
|
|||
*/
|
||||
<0 335 4>,
|
||||
<0 335 4>;
|
||||
|
||||
mmu-masters = <&xgmac1
|
||||
0 1 2 3 4 5 6 7
|
||||
16 17 18 19 20 21 22 23
|
||||
>;
|
||||
#iommu-cells = <2>;
|
||||
dma-coherent;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1,84 +0,0 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* DTS file for AMD/Linaro 96Boards Enterprise Edition Server (Husky) Board
|
||||
* Note: Based-on AMD Seattle Rev.B0
|
||||
*
|
||||
* Copyright (C) 2015 Advanced Micro Devices, Inc.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "amd-seattle-soc.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Linaro 96Boards Enterprise Edition Server (Husky) Board";
|
||||
compatible = "amd,seattle-overdrive", "amd,seattle";
|
||||
|
||||
chosen {
|
||||
stdout-path = &serial0;
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-0.2";
|
||||
method = "smc";
|
||||
};
|
||||
};
|
||||
|
||||
&ccp0 {
|
||||
status = "ok";
|
||||
amd,zlib-support = <1>;
|
||||
};
|
||||
|
||||
/**
|
||||
* NOTE: In Rev.B, gpio0 is reserved.
|
||||
*/
|
||||
&gpio1 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&gpio2 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&gpio3 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&gpio4 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&pcie0 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&spi1 {
|
||||
status = "ok";
|
||||
sdcard0: sdcard@0 {
|
||||
compatible = "mmc-spi-slot";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <20000000>;
|
||||
voltage-ranges = <3200 3400>;
|
||||
pl022,hierarchy = <0>;
|
||||
pl022,interface = <0>;
|
||||
pl022,com-mode = <0x0>;
|
||||
pl022,rx-level-trig = <0>;
|
||||
pl022,tx-level-trig = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&smb0 {
|
||||
/include/ "amd-seattle-xgbe-b.dtsi"
|
||||
};
|
||||
|
|
@ -536,9 +536,9 @@
|
|||
clock-names = "i2c";
|
||||
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
|
||||
QORIQ_CLK_PLL_DIV(1)>;
|
||||
dmas = <&edma0 1 39>,
|
||||
<&edma0 1 38>;
|
||||
dma-names = "tx", "rx";
|
||||
dmas = <&edma0 1 38>,
|
||||
<&edma0 1 39>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -499,9 +499,9 @@
|
|||
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
|
||||
QORIQ_CLK_PLL_DIV(2)>;
|
||||
dmas = <&edma0 1 39>,
|
||||
<&edma0 1 38>;
|
||||
dma-names = "tx", "rx";
|
||||
dmas = <&edma0 1 38>,
|
||||
<&edma0 1 39>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue