ASoC: Implement BCLK rate selection for WM8580
Drive a minimal supported number of clocks required for the current bit format in master mode. In slave mode this setting has no effect. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
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@ -486,14 +486,18 @@ static int wm8580_paif_hw_params(struct snd_pcm_substream *substream,
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/* bit size */
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switch (params_format(params)) {
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case SNDRV_PCM_FORMAT_S16_LE:
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paifa |= 0x8;
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break;
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case SNDRV_PCM_FORMAT_S20_3LE:
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paifa |= 0x10;
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paifb |= WM8580_AIF_LENGTH_20;
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break;
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case SNDRV_PCM_FORMAT_S24_LE:
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paifa |= 0x10;
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paifb |= WM8580_AIF_LENGTH_24;
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break;
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case SNDRV_PCM_FORMAT_S32_LE:
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paifa |= 0x10;
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paifb |= WM8580_AIF_LENGTH_24;
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break;
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default:
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@ -515,7 +519,8 @@ static int wm8580_paif_hw_params(struct snd_pcm_substream *substream,
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wm8580_sysclk_ratios[i], wm8580->sysclk[dai->driver->id]);
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snd_soc_update_bits(codec, WM8580_PAIF1 + dai->driver->id,
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WM8580_AIF_RATE_MASK, paifa);
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WM8580_AIF_RATE_MASK | WM8580_AIF_BCLKSEL_MASK,
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paifa);
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snd_soc_update_bits(codec, WM8580_PAIF3 + dai->driver->id,
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WM8580_AIF_LENGTH_MASK, paifb);
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return 0;
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