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- mt8173: add reset for dsi0 to mmsys 

- move dt-bindings reset controller includes to correct folder
 - split PCIe node to use new format for mt2712 and mt7622
 - mt8183: add audio node to chromebook devices
 - mt8192: add clock controller node
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Merge tag 'v5.15-next-dts64' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into arm/dt

Biggest change is, that we have now support for a reset controller inside the
mmsys. This goes inhand with changes to the driver, that you will find in the
soc pull request.

Mediatek PCI device tree binding described the root port in a wrong. The IP
actaully implements several root complex with everyone having a single root port.

We need to fix the DT in an incompatible way to describe the HW as it is. This
also fixes a problem that no IRQ bigger then 32 could be handled.

The only public available HW that is affected by this is the BananaPi R64. I'm
not aware that there is a big user base using the upstream kernel. In this
boards PCI is only used for extension cards, so I don't expect any boot problems.

- mt8173: add reset for dsi0 to mmsys
- move dt-bindings reset controller includes to correct folder
- split PCIe node to use new format for mt2712 and mt7622
- mt8183: add audio node to chromebook devices
- mt8192: add clock controller node

* tag 'v5.15-next-dts64' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux:
  arm64: dts: mt8183: Add the mmsys reset bit to reset the dsi0
  arm64: dts: mt8173: Add the mmsys reset bit to reset the dsi0
  dt-bindings: display: mediatek: add dsi reset optional property
  dt-bindings: mediatek: Add #reset-cells to mmsys system controller
  arm64: dts: mediatek: Move reset controller constants into common location
  arm64: dts: mediatek: Split PCIe node for MT2712 and MT7622
  arm64: dts: mt8183: add kukui platform audio node
  arm64: dts: mt8183: add audio node
  arm64: dts: mediatek: Add mt8192 clock controllers

Link: https://lore.kernel.org/r/1a3d63a3-c020-3319-26f6-a2ec338cc42e@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2021-10-19 22:34:11 +02:00
parent 96c7f32d17 4bdb00edbd
commit ba232d398a
35 changed files with 640 additions and 123 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
View File

@ -43,6 +43,9 @@ properties:
"#clock-cells":
const: 1
'#reset-cells':
const: 1
required:
- compatible
- reg
@ -56,4 +59,5 @@ examples:
compatible = "mediatek,mt8173-mmsys", "syscon";
reg = <0x14000000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};

6
Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
View File

@ -19,6 +19,11 @@ Required properties:
Documentation/devicetree/bindings/graph.txt. This port should be connected
to the input port of an attached DSI panel or DSI-to-eDP encoder chip.
Optional properties:
- resets: list of phandle + reset specifier pair, as described in [1].
[1] Documentation/devicetree/bindings/reset/reset.txt
MIPI TX Configuration Module
============================
@ -45,6 +50,7 @@ dsi0: dsi@1401b000 {
clocks = <&mmsys MM_DSI0_ENGINE>, <&mmsys MM_DSI0_DIGITAL>,
<&mipi_tx0>;
clock-names = "engine", "digital", "hs";
resets = <&mmsys MT8173_MMSYS_SW0_RST_B_DISP_DSI0>;
phys = <&mipi_tx0>;
phy-names = "dphy";

97
arch/arm64/boot/dts/mediatek/mt2712e.dtsi
View File

@ -915,64 +915,67 @@
};
};
pcie: pcie@11700000 {
pcie1: pcie@112ff000 {
compatible = "mediatek,mt2712-pcie";
device_type = "pci";
reg = <0 0x11700000 0 0x1000>,
<0 0x112ff000 0 0x1000>;
reg-names = "port0", "port1";
reg = <0 0x112ff000 0 0x1000>;
reg-names = "port1";
linux,pci-domain = <1>;
#address-cells = <3>;
#size-cells = <2>;
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,
<&topckgen CLK_TOP_PE2_MAC_P1_SEL>,
<&pericfg CLK_PERI_PCIE0>,
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pcie_irq";
clocks = <&topckgen CLK_TOP_PE2_MAC_P1_SEL>,
<&pericfg CLK_PERI_PCIE1>;
clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1";
phys = <&u3port0 PHY_TYPE_PCIE>, <&u3port1 PHY_TYPE_PCIE>;
phy-names = "pcie-phy0", "pcie-phy1";
clock-names = "sys_ck1", "ahb_ck1";
phys = <&u3port1 PHY_TYPE_PCIE>;
phy-names = "pcie-phy1";
bus-range = <0x00 0xff>;
ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
ranges = <0x82000000 0 0x11400000 0x0 0x11400000 0 0x300000>;
status = "disabled";
pcie0: pcie@0,0 {
device_type = "pci";
status = "disabled";
reg = <0x0000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie_intc1 0>,
<0 0 0 2 &pcie_intc1 1>,
<0 0 0 3 &pcie_intc1 2>,
<0 0 0 4 &pcie_intc1 3>;
pcie_intc1: interrupt-controller {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie_intc0 0>,
<0 0 0 2 &pcie_intc0 1>,
<0 0 0 3 &pcie_intc0 2>,
<0 0 0 4 &pcie_intc0 3>;
pcie_intc0: interrupt-controller {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
};
};
pcie1: pcie@1,0 {
device_type = "pci";
status = "disabled";
reg = <0x0800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
pcie0: pcie@11700000 {
compatible = "mediatek,mt2712-pcie";
device_type = "pci";
reg = <0 0x11700000 0 0x1000>;
reg-names = "port0";
linux,pci-domain = <0>;
#address-cells = <3>;
#size-cells = <2>;
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pcie_irq";
clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,
<&pericfg CLK_PERI_PCIE0>;
clock-names = "sys_ck0", "ahb_ck0";
phys = <&u3port0 PHY_TYPE_PCIE>;
phy-names = "pcie-phy0";
bus-range = <0x00 0xff>;
ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
status = "disabled";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie_intc0 0>,
<0 0 0 2 &pcie_intc0 1>,
<0 0 0 3 &pcie_intc0 2>,
<0 0 0 4 &pcie_intc0 3>;
pcie_intc0: interrupt-controller {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie_intc1 0>,
<0 0 0 2 &pcie_intc1 1>,
<0 0 0 3 &pcie_intc1 2>,
<0 0 0 4 &pcie_intc1 3>;
pcie_intc1: interrupt-controller {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
};
};

1
arch/arm64/boot/dts/mediatek/mt6358.dtsi
View File

@ -13,6 +13,7 @@
mt6358codec: mt6358codec {
compatible = "mediatek,mt6358-sound";
mediatek,dmic-mode = <0>; /* two-wires */
};
mt6358regulator: mt6358regulator {

16
arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
View File

@ -257,18 +257,16 @@
};
};
&pcie {
&pcie0 {
pinctrl-names = "default";
pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;
pinctrl-0 = <&pcie0_pins>;
status = "okay";
};
pcie@0,0 {
status = "okay";
};
pcie@1,0 {
status = "okay";
};
&pcie1 {
pinctrl-names = "default";
pinctrl-0 = <&pcie1_pins>;
status = "okay";
};
&pio {

6
arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
View File

@ -234,14 +234,10 @@
};
};
&pcie {
&pcie0 {
pinctrl-names = "default";
pinctrl-0 = <&pcie0_pins>;
status = "okay";
pcie@0,0 {
status = "okay";
};
};
&pio {

112
arch/arm64/boot/dts/mediatek/mt7622.dtsi
View File

@ -781,75 +781,83 @@
#reset-cells = <1>;
};
pcie: pcie@1a140000 {
pciecfg: pciecfg@1a140000 {
compatible = "mediatek,generic-pciecfg", "syscon";
reg = <0 0x1a140000 0 0x1000>;
};
pcie0: pcie@1a143000 {
compatible = "mediatek,mt7622-pcie";
device_type = "pci";
reg = <0 0x1a140000 0 0x1000>,
<0 0x1a143000 0 0x1000>,
<0 0x1a145000 0 0x1000>;
reg-names = "subsys", "port0", "port1";
reg = <0 0x1a143000 0 0x1000>;
reg-names = "port0";
linux,pci-domain = <0>;
#address-cells = <3>;
#size-cells = <2>;
interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "pcie_irq";
clocks = <&pciesys CLK_PCIE_P0_MAC_EN>,
<&pciesys CLK_PCIE_P1_MAC_EN>,
<&pciesys CLK_PCIE_P0_AHB_EN>,
<&pciesys CLK_PCIE_P0_AHB_EN>,
<&pciesys CLK_PCIE_P0_AUX_EN>,
<&pciesys CLK_PCIE_P1_AUX_EN>,
<&pciesys CLK_PCIE_P0_AXI_EN>,
<&pciesys CLK_PCIE_P1_AXI_EN>,
<&pciesys CLK_PCIE_P0_OBFF_EN>,
<&pciesys CLK_PCIE_P1_OBFF_EN>,
<&pciesys CLK_PCIE_P0_PIPE_EN>,
<&pciesys CLK_PCIE_P1_PIPE_EN>;
clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1",
"aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1",
"obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1";
<&pciesys CLK_PCIE_P0_PIPE_EN>;
clock-names = "sys_ck0", "ahb_ck0", "aux_ck0",
"axi_ck0", "obff_ck0", "pipe_ck0";
power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
bus-range = <0x00 0xff>;
ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>;
status = "disabled";
pcie0: pcie@0,0 {
reg = <0x0000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie_intc0 0>,
<0 0 0 2 &pcie_intc0 1>,
<0 0 0 3 &pcie_intc0 2>,
<0 0 0 4 &pcie_intc0 3>;
pcie_intc0: interrupt-controller {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
ranges;
status = "disabled";
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie_intc0 0>,
<0 0 0 2 &pcie_intc0 1>,
<0 0 0 3 &pcie_intc0 2>,
<0 0 0 4 &pcie_intc0 3>;
pcie_intc0: interrupt-controller {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
};
};
pcie1: pcie@1,0 {
reg = <0x0800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
pcie1: pcie@1a145000 {
compatible = "mediatek,mt7622-pcie";
device_type = "pci";
reg = <0 0x1a145000 0 0x1000>;
reg-names = "port1";
linux,pci-domain = <1>;
#address-cells = <3>;
#size-cells = <2>;
interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "pcie_irq";
clocks = <&pciesys CLK_PCIE_P1_MAC_EN>,
/* designer has connect RC1 with p0_ahb clock */
<&pciesys CLK_PCIE_P0_AHB_EN>,
<&pciesys CLK_PCIE_P1_AUX_EN>,
<&pciesys CLK_PCIE_P1_AXI_EN>,
<&pciesys CLK_PCIE_P1_OBFF_EN>,
<&pciesys CLK_PCIE_P1_PIPE_EN>;
clock-names = "sys_ck1", "ahb_ck1", "aux_ck1",
"axi_ck1", "obff_ck1", "pipe_ck1";
power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
bus-range = <0x00 0xff>;
ranges = <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>;
status = "disabled";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie_intc1 0>,
<0 0 0 2 &pcie_intc1 1>,
<0 0 0 3 &pcie_intc1 2>,
<0 0 0 4 &pcie_intc1 3>;
pcie_intc1: interrupt-controller {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
ranges;
status = "disabled";
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie_intc1 0>,
<0 0 0 2 &pcie_intc1 1>,
<0 0 0 3 &pcie_intc1 2>,
<0 0 0 4 &pcie_intc1 3>;
pcie_intc1: interrupt-controller {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
};
};

2
arch/arm64/boot/dts/mediatek/mt8173.dtsi
View File

@ -996,6 +996,7 @@
assigned-clocks = <&topckgen CLK_TOP_MM_SEL>;
assigned-clock-rates = <400000000>;
#clock-cells = <1>;
#reset-cells = <1>;
mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
<&gce 1 CMDQ_THR_PRIO_HIGHEST>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
@ -1222,6 +1223,7 @@
<&mmsys CLK_MM_DSI0_DIGITAL>,
<&mipi_tx0>;
clock-names = "engine", "digital", "hs";
resets = <&mmsys MT8173_MMSYS_SW0_RST_B_DISP_DSI0>;
phys = <&mipi_tx0>;
phy-names = "dphy";
status = "disabled";

13
arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-da7219-max98357a.dtsi Normal file
View File

@ -0,0 +1,13 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Google Kukui (and derivatives) da7219-max98357a sound card.
*
* Copyright 2019 Google LLC.
*/
#include "mt8183-kukui-audio-da7219.dtsi"
#include "mt8183-kukui-audio-max98357a.dtsi"
&sound {
compatible = "mediatek,mt8183_da7219_max98357";
};

13
arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-da7219-rt1015p.dtsi Normal file
View File

@ -0,0 +1,13 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Google Kukui (and derivatives) da7219-rt1015p sound card.
*
* Copyright 2020 Google LLC.
*/
#include "mt8183-kukui-audio-da7219.dtsi"
#include "mt8183-kukui-audio-rt1015p.dtsi"
&sound {
compatible = "mediatek,mt8183_da7219_rt1015p";
};

54
arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-da7219.dtsi Normal file
View File

@ -0,0 +1,54 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Google Kukui (and derivatives) audio fragment for da7219.
*
* Copyright 2020 Google LLC.
*/
&i2c5 {
da7219: da7219@1a {
pinctrl-names = "default";
pinctrl-0 = <&da7219_pins>;
compatible = "dlg,da7219";
reg = <0x1a>;
interrupt-parent = <&pio>;
interrupts = <165 IRQ_TYPE_LEVEL_LOW 165 0>;
dlg,micbias-lvl = <2600>;
dlg,mic-amp-in-sel = "diff";
VDD-supply = <&pp1800_alw>;
VDDMIC-supply = <&pp3300_alw>;
VDDIO-supply = <&pp1800_alw>;
status = "okay";
da7219_aad {
dlg,adc-1bit-rpt = <1>;
dlg,btn-avg = <4>;
dlg,btn-cfg = <50>;
dlg,mic-det-thr = <500>;
dlg,jack-ins-deb = <20>;
dlg,jack-det-rate = "32ms_64ms";
dlg,jack-rem-deb = <1>;
dlg,a-d-btn-thr = <0xa>;
dlg,d-b-btn-thr = <0x16>;
dlg,b-c-btn-thr = <0x21>;
dlg,c-mic-btn-thr = <0x3E>;
};
};
};
&pio {
da7219_pins: da7219_pins {
pins1 {
pinmux = <PINMUX_GPIO165__FUNC_GPIO165>;
input-enable;
bias-pull-up;
};
};
};
&sound {
mediatek,headset-codec = <&da7219>;
};

13
arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-max98357a.dtsi Normal file
View File

@ -0,0 +1,13 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Google Kukui (and derivatives) audio fragment for max98357a.
*
* Copyright 2020 Google LLC.
*/
/ {
max98357a: max98357a {
compatible = "maxim,max98357a";
sdmode-gpios = <&pio 175 0>;
};
};

13
arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-rt1015p.dtsi Normal file
View File

@ -0,0 +1,13 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Google Kukui (and derivatives) audio fragment for rt1015p.
*
* Copyright 2020 Google LLC.
*/
/ {
rt1015p: rt1015p {
compatible = "realtek,rt1015p";
sdb-gpios = <&pio 175 0>;
};
};

13
arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-ts3a227e-max98357a.dtsi Normal file
View File

@ -0,0 +1,13 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Google Kukui (and derivatives) ts3a227e-max98357a sound card.
*
* Copyright 2020 Google LLC.
*/
#include "mt8183-kukui-audio-max98357a.dtsi"
#include "mt8183-kukui-audio-ts3a227e.dtsi"
&sound {
compatible = "mediatek,mt8183_mt6358_ts3a227_max98357";
};

13
arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-ts3a227e-rt1015p.dtsi Normal file
View File

@ -0,0 +1,13 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Google Kukui (and derivatives) mt6358-ts3a227-rt1015p sound card.
*
* Copyright 2021 Google LLC.
*/
#include "mt8183-kukui-audio-ts3a227e.dtsi"
#include "mt8183-kukui-audio-rt1015p.dtsi"
&sound {
compatible = "mediatek,mt8183_mt6358_ts3a227_rt1015p";
};

32
arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-ts3a227e.dtsi Normal file
View File

@ -0,0 +1,32 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Google Kukui (and derivatives) audio fragment for ts3a227e.
*
* Copyright 2019 Google LLC.
*/
&i2c5 {
ts3a227e: ts3a227e@3b {
pinctrl-names = "default";
pinctrl-0 = <&ts3a227e_pins>;
compatible = "ti,ts3a227e";
reg = <0x3b>;
interrupt-parent = <&pio>;
interrupts = <157 IRQ_TYPE_LEVEL_LOW>;
status = "okay";
};
};
&pio {
ts3a227e_pins: ts3a227e_pins {
pins1 {
pinmux = <PINMUX_GPIO157__FUNC_GPIO157>;
input-enable;
bias-pull-up;
};
};
};
&sound {
mediatek,headset-codec = <&ts3a227e>;
};

1
arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-burnet.dts
View File

@ -5,6 +5,7 @@
/dts-v1/;
#include "mt8183-kukui-jacuzzi.dtsi"
#include "mt8183-kukui-audio-ts3a227e-max98357a.dtsi"
/ {
model = "Google burnet board";

1
arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dts
View File

@ -5,6 +5,7 @@
/dts-v1/;
#include "mt8183-kukui-jacuzzi.dtsi"
#include "mt8183-kukui-audio-da7219-max98357a.dtsi"
/ {
model = "Google damu board";

1
arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel.dtsi
View File

@ -5,6 +5,7 @@
/dts-v1/;
#include "mt8183-kukui-jacuzzi.dtsi"
#include "mt8183-kukui-audio-da7219-rt1015p.dtsi"
&mt6358codec {
mediatek,dmic-mode = <1>; /* one-wire */

1
arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dts
View File

@ -5,6 +5,7 @@
/dts-v1/;
#include "mt8183-kukui-jacuzzi-juniper.dtsi"
#include "mt8183-kukui-audio-ts3a227e-max98357a.dtsi"
/ {
model = "Google juniper sku16 board";

1
arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kappa.dts
View File

@ -5,6 +5,7 @@
/dts-v1/;
#include "mt8183-kukui-jacuzzi.dtsi"
#include "mt8183-kukui-audio-ts3a227e-max98357a.dtsi"
/ {
model = "Google kappa board";

1
arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kenzo.dts
View File

@ -5,6 +5,7 @@
/dts-v1/;
#include "mt8183-kukui-jacuzzi-juniper.dtsi"
#include "mt8183-kukui-audio-ts3a227e-max98357a.dtsi"
/ {
model = "Google kenzo sku17 board";

1
arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku0.dts
View File

@ -5,6 +5,7 @@
/dts-v1/;
#include "mt8183-kukui-jacuzzi-willow.dtsi"
#include "mt8183-kukui-audio-da7219-max98357a.dtsi"
/ {
model = "Google willow board sku0";

1
arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku1.dts
View File

@ -5,6 +5,7 @@
/dts-v1/;
#include "mt8183-kukui-jacuzzi-willow.dtsi"
#include "mt8183-kukui-audio-ts3a227e-max98357a.dtsi"
/ {
model = "Google willow board sku1";

1
arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dts
View File

@ -5,6 +5,7 @@
/dts-v1/;
#include "mt8183-kukui-kakadu.dtsi"
#include "mt8183-kukui-audio-da7219-rt1015p.dtsi"
/ {
model = "MediaTek kakadu board";

1
arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama.dtsi
View File

@ -5,6 +5,7 @@
/dts-v1/;
#include "mt8183-kukui.dtsi"
#include "mt8183-kukui-audio-ts3a227e-max98357a.dtsi"
/ {
ppvarn_lcd: ppvarn-lcd {

5
arch/arm64/boot/dts/mediatek/mt8183-kukui-krane.dtsi
View File

@ -4,6 +4,7 @@
*/
#include "mt8183-kukui.dtsi"
#include "mt8183-kukui-audio-max98357a.dtsi"
/ {
ppvarn_lcd: ppvarn-lcd {
@ -345,3 +346,7 @@
&qca_wifi {
qcom,ath10k-calibration-variant = "LE_Krane";
};
&sound {
compatible = "mediatek,mt8183_mt6358_ts3a227_max98357";
};

67
arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
View File

@ -115,12 +115,18 @@
};
};
max98357a: codec0 {
compatible = "maxim,max98357a";
sdmode-gpios = <&pio 175 0>;
sound: mt8183-sound {
mediatek,platform = <&afe>;
pinctrl-names = "default",
"aud_tdm_out_on",
"aud_tdm_out_off";
pinctrl-0 = <&aud_pins_default>;
pinctrl-1 = <&aud_pins_tdm_out_on>;
pinctrl-2 = <&aud_pins_tdm_out_off>;
status = "okay";
};
btsco: codec1 {
btsco: bt-sco {
compatible = "linux,bt-sco";
};
@ -215,6 +221,11 @@
};
};
&afe {
i2s3-share = "I2S2";
i2s0-share = "I2S5";
};
&auxadc {
status = "okay";
};
@ -402,6 +413,54 @@
};
&pio {
aud_pins_default: audiopins {
pins_bus {
pinmux = <PINMUX_GPIO97__FUNC_I2S2_MCK>,
<PINMUX_GPIO98__FUNC_I2S2_BCK>,
<PINMUX_GPIO101__FUNC_I2S2_LRCK>,
<PINMUX_GPIO102__FUNC_I2S2_DI>,
<PINMUX_GPIO3__FUNC_I2S3_DO>, /*i2s to da7219/max98357*/
<PINMUX_GPIO89__FUNC_I2S5_BCK>,
<PINMUX_GPIO90__FUNC_I2S5_LRCK>,
<PINMUX_GPIO91__FUNC_I2S5_DO>,
<PINMUX_GPIO174__FUNC_I2S0_DI>, /*i2s to wifi/bt*/
<PINMUX_GPIO136__FUNC_AUD_CLK_MOSI>,
<PINMUX_GPIO137__FUNC_AUD_SYNC_MOSI>,
<PINMUX_GPIO138__FUNC_AUD_DAT_MOSI0>,
<PINMUX_GPIO139__FUNC_AUD_DAT_MOSI1>,
<PINMUX_GPIO140__FUNC_AUD_CLK_MISO>,
<PINMUX_GPIO141__FUNC_AUD_SYNC_MISO>,
<PINMUX_GPIO142__FUNC_AUD_DAT_MISO0>,
<PINMUX_GPIO143__FUNC_AUD_DAT_MISO1>; /*mtkaif3.0*/
};
};
aud_pins_tdm_out_on: audiotdmouton {
pins_bus {
pinmux = <PINMUX_GPIO169__FUNC_TDM_BCK_2ND>,
<PINMUX_GPIO170__FUNC_TDM_LRCK_2ND>,
<PINMUX_GPIO171__FUNC_TDM_DATA0_2ND>,
<PINMUX_GPIO172__FUNC_TDM_DATA1_2ND>,
<PINMUX_GPIO173__FUNC_TDM_DATA2_2ND>,
<PINMUX_GPIO10__FUNC_TDM_DATA3>; /*8ch-i2s to it6505*/
drive-strength = <MTK_DRIVE_6mA>;
};
};
aud_pins_tdm_out_off: audiotdmoutoff {
pins_bus {
pinmux = <PINMUX_GPIO169__FUNC_GPIO169>,
<PINMUX_GPIO170__FUNC_GPIO170>,
<PINMUX_GPIO171__FUNC_GPIO171>,
<PINMUX_GPIO172__FUNC_GPIO172>,
<PINMUX_GPIO173__FUNC_GPIO173>,
<PINMUX_GPIO10__FUNC_GPIO10>;
input-enable;
bias-pull-down;
drive-strength = <MTK_DRIVE_2mA>;
};
};
bt_pins: bt-pins {
pins_bt_en {
pinmux = <PINMUX_GPIO120__FUNC_GPIO120>;

99
arch/arm64/boot/dts/mediatek/mt8183.dtsi
View File

@ -11,7 +11,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/memory/mt8183-larb-port.h>
#include <dt-bindings/power/mt8183-power.h>
#include <dt-bindings/reset-controller/mt8183-resets.h>
#include <dt-bindings/reset/mt8183-resets.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/thermal/thermal.h>
#include <dt-bindings/pinctrl/mt8183-pinfunc.h>
@ -1115,10 +1115,102 @@
};
};
audiosys: syscon@11220000 {
audiosys: audio-controller@11220000 {
compatible = "mediatek,mt8183-audiosys", "syscon";
reg = <0 0x11220000 0 0x1000>;
#clock-cells = <1>;
afe: mt8183-afe-pcm {
compatible = "mediatek,mt8183-audio";
interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_LOW>;
resets = <&watchdog MT8183_TOPRGU_AUDIO_SW_RST>;
reset-names = "audiosys";
power-domains =
<&spm MT8183_POWER_DOMAIN_AUDIO>;
clocks = <&audiosys CLK_AUDIO_AFE>,
<&audiosys CLK_AUDIO_DAC>,
<&audiosys CLK_AUDIO_DAC_PREDIS>,
<&audiosys CLK_AUDIO_ADC>,
<&audiosys CLK_AUDIO_PDN_ADDA6_ADC>,
<&audiosys CLK_AUDIO_22M>,
<&audiosys CLK_AUDIO_24M>,
<&audiosys CLK_AUDIO_APLL_TUNER>,
<&audiosys CLK_AUDIO_APLL2_TUNER>,
<&audiosys CLK_AUDIO_I2S1>,
<&audiosys CLK_AUDIO_I2S2>,
<&audiosys CLK_AUDIO_I2S3>,
<&audiosys CLK_AUDIO_I2S4>,
<&audiosys CLK_AUDIO_TDM>,
<&audiosys CLK_AUDIO_TML>,
<&infracfg CLK_INFRA_AUDIO>,
<&infracfg CLK_INFRA_AUDIO_26M_BCLK>,
<&topckgen CLK_TOP_MUX_AUDIO>,
<&topckgen CLK_TOP_MUX_AUD_INTBUS>,
<&topckgen CLK_TOP_SYSPLL_D2_D4>,
<&topckgen CLK_TOP_MUX_AUD_1>,
<&topckgen CLK_TOP_APLL1_CK>,
<&topckgen CLK_TOP_MUX_AUD_2>,
<&topckgen CLK_TOP_APLL2_CK>,
<&topckgen CLK_TOP_MUX_AUD_ENG1>,
<&topckgen CLK_TOP_APLL1_D8>,
<&topckgen CLK_TOP_MUX_AUD_ENG2>,
<&topckgen CLK_TOP_APLL2_D8>,
<&topckgen CLK_TOP_MUX_APLL_I2S0>,
<&topckgen CLK_TOP_MUX_APLL_I2S1>,
<&topckgen CLK_TOP_MUX_APLL_I2S2>,
<&topckgen CLK_TOP_MUX_APLL_I2S3>,
<&topckgen CLK_TOP_MUX_APLL_I2S4>,
<&topckgen CLK_TOP_MUX_APLL_I2S5>,
<&topckgen CLK_TOP_APLL12_DIV0>,
<&topckgen CLK_TOP_APLL12_DIV1>,
<&topckgen CLK_TOP_APLL12_DIV2>,
<&topckgen CLK_TOP_APLL12_DIV3>,
<&topckgen CLK_TOP_APLL12_DIV4>,
<&topckgen CLK_TOP_APLL12_DIVB>,
/*<&topckgen CLK_TOP_APLL12_DIV5>,*/
<&clk26m>;
clock-names = "aud_afe_clk",
"aud_dac_clk",
"aud_dac_predis_clk",
"aud_adc_clk",
"aud_adc_adda6_clk",
"aud_apll22m_clk",
"aud_apll24m_clk",
"aud_apll1_tuner_clk",
"aud_apll2_tuner_clk",
"aud_i2s1_bclk_sw",
"aud_i2s2_bclk_sw",
"aud_i2s3_bclk_sw",
"aud_i2s4_bclk_sw",
"aud_tdm_clk",
"aud_tml_clk",
"aud_infra_clk",
"mtkaif_26m_clk",
"top_mux_audio",
"top_mux_aud_intbus",
"top_syspll_d2_d4",
"top_mux_aud_1",
"top_apll1_ck",
"top_mux_aud_2",
"top_apll2_ck",
"top_mux_aud_eng1",
"top_apll1_d8",
"top_mux_aud_eng2",
"top_apll2_d8",
"top_i2s0_m_sel",
"top_i2s1_m_sel",
"top_i2s2_m_sel",
"top_i2s3_m_sel",
"top_i2s4_m_sel",
"top_i2s5_m_sel",
"top_apll12_div0",
"top_apll12_div1",
"top_apll12_div2",
"top_apll12_div3",
"top_apll12_div4",
"top_apll12_divb",
/*"top_apll12_div5",*/
"top_clk26m_clk";
};
};
mmc0: mmc@11230000 {
@ -1227,6 +1319,7 @@
compatible = "mediatek,mt8183-mmsys", "syscon";
reg = <0 0x14000000 0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
<&gce 1 CMDQ_THR_PRIO_HIGHEST>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
@ -1341,11 +1434,11 @@
reg = <0 0x14014000 0 0x1000>;
interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
mediatek,syscon-dsi = <&mmsys 0x140>;
clocks = <&mmsys CLK_MM_DSI0_MM>,
<&mmsys CLK_MM_DSI0_IF>,
<&mipi_tx0>;
clock-names = "engine", "digital", "hs";
resets = <&mmsys MT8183_MMSYS_SW0_RST_B_DISP_DSI0>;
phys = <&mipi_tx0>;
phy-names = "dphy";
};

163
arch/arm64/boot/dts/mediatek/mt8192.dtsi
View File

@ -5,6 +5,7 @@
*/
/dts-v1/;
#include <dt-bindings/clock/mt8192-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/mt8192-pinfunc.h>
@ -257,6 +258,24 @@
};
};
topckgen: syscon@10000000 {
compatible = "mediatek,mt8192-topckgen", "syscon";
reg = <0 0x10000000 0 0x1000>;
#clock-cells = <1>;
};
infracfg: syscon@10001000 {
compatible = "mediatek,mt8192-infracfg", "syscon";
reg = <0 0x10001000 0 0x1000>;
#clock-cells = <1>;
};
pericfg: syscon@10003000 {
compatible = "mediatek,mt8192-pericfg", "syscon";
reg = <0 0x10003000 0 0x1000>;
#clock-cells = <1>;
};
pio: pinctrl@10005000 {
compatible = "mediatek,mt8192-pinctrl";
reg = <0 0x10005000 0 0x1000>,
@ -282,6 +301,12 @@
#interrupt-cells = <2>;
};
apmixedsys: syscon@1000c000 {
compatible = "mediatek,mt8192-apmixedsys", "syscon";
reg = <0 0x1000c000 0 0x1000>;
#clock-cells = <1>;
};
systimer: timer@10017000 {
compatible = "mediatek,mt8192-timer",
"mediatek,mt6765-timer";
@ -291,6 +316,12 @@
clock-names = "clk13m";
};
scp_adsp: clock-controller@10720000 {
compatible = "mediatek,mt8192-scp_adsp";
reg = <0 0x10720000 0 0x1000>;
#clock-cells = <1>;
};
uart0: serial@11002000 {
compatible = "mediatek,mt8192-uart",
"mediatek,mt6577-uart";
@ -311,6 +342,12 @@
status = "disabled";
};
imp_iic_wrap_c: clock-controller@11007000 {
compatible = "mediatek,mt8192-imp_iic_wrap_c";
reg = <0 0x11007000 0 0x1000>;
#clock-cells = <1>;
};
spi0: spi@1100a000 {
compatible = "mediatek,mt8192-spi",
"mediatek,mt6765-spi";
@ -436,6 +473,12 @@
status = "disable";
};
audsys: clock-controller@11210000 {
compatible = "mediatek,mt8192-audsys", "syscon";
reg = <0 0x11210000 0 0x1000>;
#clock-cells = <1>;
};
i2c3: i2c3@11cb0000 {
compatible = "mediatek,mt8192-i2c";
reg = <0 0x11cb0000 0 0x1000>,
@ -449,6 +492,12 @@
status = "disabled";
};
imp_iic_wrap_e: clock-controller@11cb1000 {
compatible = "mediatek,mt8192-imp_iic_wrap_e";
reg = <0 0x11cb1000 0 0x1000>;
#clock-cells = <1>;
};
i2c7: i2c7@11d00000 {
compatible = "mediatek,mt8192-i2c";
reg = <0 0x11d00000 0 0x1000>,
@ -488,6 +537,12 @@
status = "disabled";
};
imp_iic_wrap_s: clock-controller@11d03000 {
compatible = "mediatek,mt8192-imp_iic_wrap_s";
reg = <0 0x11d03000 0 0x1000>;
#clock-cells = <1>;
};
i2c1: i2c1@11d20000 {
compatible = "mediatek,mt8192-i2c";
reg = <0 0x11d20000 0 0x1000>,
@ -527,6 +582,12 @@
status = "disabled";
};
imp_iic_wrap_ws: clock-controller@11d23000 {
compatible = "mediatek,mt8192-imp_iic_wrap_ws";
reg = <0 0x11d23000 0 0x1000>;
#clock-cells = <1>;
};
i2c5: i2c5@11e00000 {
compatible = "mediatek,mt8192-i2c";
reg = <0 0x11e00000 0 0x1000>,
@ -540,6 +601,12 @@
status = "disabled";
};
imp_iic_wrap_w: clock-controller@11e01000 {
compatible = "mediatek,mt8192-imp_iic_wrap_w";
reg = <0 0x11e01000 0 0x1000>;
#clock-cells = <1>;
};
i2c0: i2c0@11f00000 {
compatible = "mediatek,mt8192-i2c";
reg = <0 0x11f00000 0 0x1000>,
@ -565,5 +632,101 @@
#size-cells = <0>;
status = "disabled";
};
imp_iic_wrap_n: clock-controller@11f02000 {
compatible = "mediatek,mt8192-imp_iic_wrap_n";
reg = <0 0x11f02000 0 0x1000>;
#clock-cells = <1>;
};
msdc_top: clock-controller@11f10000 {
compatible = "mediatek,mt8192-msdc_top";
reg = <0 0x11f10000 0 0x1000>;
#clock-cells = <1>;
};
msdc: clock-controller@11f60000 {
compatible = "mediatek,mt8192-msdc";
reg = <0 0x11f60000 0 0x1000>;
#clock-cells = <1>;
};
mfgcfg: clock-controller@13fbf000 {
compatible = "mediatek,mt8192-mfgcfg";
reg = <0 0x13fbf000 0 0x1000>;
#clock-cells = <1>;
};
mmsys: syscon@14000000 {
compatible = "mediatek,mt8192-mmsys", "syscon";
reg = <0 0x14000000 0 0x1000>;
#clock-cells = <1>;
};
imgsys: clock-controller@15020000 {
compatible = "mediatek,mt8192-imgsys";
reg = <0 0x15020000 0 0x1000>;
#clock-cells = <1>;
};
imgsys2: clock-controller@15820000 {
compatible = "mediatek,mt8192-imgsys2";
reg = <0 0x15820000 0 0x1000>;
#clock-cells = <1>;
};
vdecsys_soc: clock-controller@1600f000 {
compatible = "mediatek,mt8192-vdecsys_soc";
reg = <0 0x1600f000 0 0x1000>;
#clock-cells = <1>;
};
vdecsys: clock-controller@1602f000 {
compatible = "mediatek,mt8192-vdecsys";
reg = <0 0x1602f000 0 0x1000>;
#clock-cells = <1>;
};
vencsys: clock-controller@17000000 {
compatible = "mediatek,mt8192-vencsys";
reg = <0 0x17000000 0 0x1000>;
#clock-cells = <1>;
};
camsys: clock-controller@1a000000 {
compatible = "mediatek,mt8192-camsys";
reg = <0 0x1a000000 0 0x1000>;
#clock-cells = <1>;
};
camsys_rawa: clock-controller@1a04f000 {
compatible = "mediatek,mt8192-camsys_rawa";
reg = <0 0x1a04f000 0 0x1000>;
#clock-cells = <1>;
};
camsys_rawb: clock-controller@1a06f000 {
compatible = "mediatek,mt8192-camsys_rawb";
reg = <0 0x1a06f000 0 0x1000>;
#clock-cells = <1>;
};
camsys_rawc: clock-controller@1a08f000 {
compatible = "mediatek,mt8192-camsys_rawc";
reg = <0 0x1a08f000 0 0x1000>;
#clock-cells = <1>;
};
ipesys: clock-controller@1b000000 {
compatible = "mediatek,mt8192-ipesys";
reg = <0 0x1b000000 0 0x1000>;
#clock-cells = <1>;
};
mdpsys: clock-controller@1f000000 {
compatible = "mediatek,mt8192-mdpsys";
reg = <0 0x1f000000 0 0x1000>;
#clock-cells = <1>;
};
};
};

6
drivers/watchdog/mtk_wdt.c
View File

@ -9,9 +9,9 @@
* Based on sunxi_wdt.c
*/
#include <dt-bindings/reset-controller/mt2712-resets.h>
#include <dt-bindings/reset-controller/mt8183-resets.h>
#include <dt-bindings/reset-controller/mt8192-resets.h>
#include <dt-bindings/reset/mt2712-resets.h>
#include <dt-bindings/reset/mt8183-resets.h>
#include <dt-bindings/reset/mt8192-resets.h>
#include <dt-bindings/reset/mt8195-resets.h>
#include <linux/delay.h>
#include <linux/err.h>

0
include/dt-bindings/reset-controller/mt2712-resets.h → include/dt-bindings/reset/mt2712-resets.h
View File

2
include/dt-bindings/reset/mt8173-resets.h
View File

@ -27,6 +27,8 @@
#define MT8173_INFRA_GCE_FAXI_RST 40
#define MT8173_INFRA_MMIOMMURST 47
/* MMSYS resets */
#define MT8173_MMSYS_SW0_RST_B_DISP_DSI0 25
/* PERICFG resets */
#define MT8173_PERI_UART0_SW_RST 0

3
include/dt-bindings/reset-controller/mt8183-resets.h → include/dt-bindings/reset/mt8183-resets.h
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@ -80,6 +80,9 @@
#define MT8183_INFRACFG_SW_RST_NUM 128
/* MMSYS resets */
#define MT8183_MMSYS_SW0_RST_B_DISP_DSI0 25
#define MT8183_TOPRGU_MM_SW_RST 1
#define MT8183_TOPRGU_MFG_SW_RST 2
#define MT8183_TOPRGU_VENC_SW_RST 3

0
include/dt-bindings/reset-controller/mt8192-resets.h → include/dt-bindings/reset/mt8192-resets.h
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