drm/amd/display: clean up DML for DCN2x
[why] Previous "less risky" implemenation of 3 tiered fallback is no longer necessary since DMLv2 has gone through proper validation. v2 can now be used as the default and 1 level of fallback can be removed [how] remove previous workaround implemenation Signed-off-by: Jun Lei <Jun.Lei@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -121,7 +121,6 @@ struct dc_caps {
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struct dc_bug_wa {
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bool no_connect_phy_config;
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bool dedcn20_305_wa;
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struct display_mode_lib alternate_dml;
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bool skip_clock_update;
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};
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#endif
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@ -2612,7 +2612,7 @@ bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context,
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goto restore_dml_state;
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}
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// Fallback #1: Try to only support G6 temperature read latency
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// Fallback: Try to only support G6 temperature read latency
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context->bw_ctx.dml.soc.dram_clock_change_latency_us = context->bw_ctx.dml.soc.dummy_pstate_latency_us;
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voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false);
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@ -2623,19 +2623,7 @@ bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context,
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goto restore_dml_state;
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}
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// Fallback #2: Retry with "new" DCN20 to support G6 temperature read latency
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memcpy (&context->bw_ctx.dml, &dc->work_arounds.alternate_dml, sizeof (struct display_mode_lib));
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context->bw_ctx.dml.soc.dram_clock_change_latency_us = context->bw_ctx.dml.soc.dummy_pstate_latency_us;
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voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false);
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dummy_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support;
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if (voltage_supported && dummy_pstate_supported) {
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context->bw_ctx.bw.dcn.clk.p_state_change_support = false;
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goto restore_dml_state;
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}
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// ERROR: fallback #2 is supposed to always work.
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// ERROR: fallback is supposed to always work.
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ASSERT(false);
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restore_dml_state:
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@ -3240,8 +3228,7 @@ static bool construct(
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goto create_fail;
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}
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dml_init_instance(&dc->dml, &dcn2_0_soc, &dcn2_0_ip, DML_PROJECT_NAVI10);
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dml_init_instance(&dc->work_arounds.alternate_dml, &dcn2_0_soc, &dcn2_0_ip, DML_PROJECT_NAVI10v2);
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dml_init_instance(&dc->dml, &dcn2_0_soc, &dcn2_0_ip, DML_PROJECT_NAVI10v2);
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if (!dc->debug.disable_pplib_wm_range) {
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struct pp_smu_wm_range_sets ranges = {0};
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