drm/nv50/disp: synchronise display right after init
This has the effect of ensuring the encoders which were active before we loaded get disconnected properly before we start reprogramming them. Also removing a bit of cargo-cult from the initial evo pushbuf. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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@ -627,7 +627,7 @@ nv50_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode,
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}
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}
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ret = RING_SPACE(evo, 17);
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ret = RING_SPACE(evo, 19);
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if (ret)
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return ret;
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@ -653,6 +653,9 @@ nv50_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode,
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BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, UNK082C), 1);
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OUT_RING (evo, 0);
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/* required to make display sync channel not hate life */
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BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, UNK900), 1);
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OUT_RING (evo, 0x00000311);
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/* This is the actual resolution of the mode. */
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BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, REAL_RES), 1);
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@ -210,31 +210,14 @@ nv50_display_init(struct drm_device *dev)
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nv_wr32(dev, NV50_PDISPLAY_OBJECTS, (evo->ramin->vinst >> 8) | 9);
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ret = RING_SPACE(evo, 15);
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ret = RING_SPACE(evo, 3);
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if (ret)
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return ret;
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BEGIN_RING(evo, 0, NV50_EVO_UNK84, 2);
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OUT_RING (evo, NV50_EVO_UNK84_NOTIFY_DISABLED);
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OUT_RING (evo, NvEvoSync);
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BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, FB_DMA), 1);
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OUT_RING(evo, NV50_EVO_CRTC_FB_DMA_HANDLE_NONE);
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BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, UNK0800), 1);
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OUT_RING(evo, 0);
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BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, DISPLAY_START), 1);
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OUT_RING(evo, 0);
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BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, UNK082C), 1);
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OUT_RING(evo, 0);
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/* required to make display sync channels not hate life */
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BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, UNK900), 1);
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OUT_RING (evo, 0x00000311);
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BEGIN_RING(evo, 0, NV50_EVO_CRTC(1, UNK900), 1);
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OUT_RING (evo, 0x00000311);
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FIRE_RING(evo);
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if (!nv_wait(dev, 0x640004, 0xffffffff, evo->dma.put << 2))
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NV_ERROR(dev, "evo pushbuf stalled\n");
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return 0;
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return nv50_display_sync(dev);
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}
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static int nv50_display_disable(struct drm_device *dev)
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@ -754,7 +737,7 @@ nv50_display_unk20_handler(struct drm_device *dev)
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if (crtc >= 0) {
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pclk = nv_rd32(dev, NV50_PDISPLAY_CRTC_P(crtc, CLOCK));
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pclk &= 0x003fffff;
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if (pclk)
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nv50_crtc_set_clock(dev, crtc, pclk);
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tmp = nv_rd32(dev, NV50_PDISPLAY_CRTC_CLK_CTRL2(crtc));
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