drm/i915: add intel_display_power_enabled
This should replace intel_using_power_well. The idea is that we're adding the requested power domain as an argument, so this might enable the code to look less platform-specific and also allows us to easily add new domains in case we need. v2: Add more domains to enum intel_display_power_domain v3: Even more domains requested Requested-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -88,6 +88,24 @@ enum port {
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};
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#define port_name(p) ((p) + 'A')
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enum intel_display_power_domain {
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POWER_DOMAIN_PIPE_A,
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POWER_DOMAIN_PIPE_B,
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POWER_DOMAIN_PIPE_C,
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POWER_DOMAIN_PIPE_A_PANEL_FITTER,
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POWER_DOMAIN_PIPE_B_PANEL_FITTER,
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POWER_DOMAIN_PIPE_C_PANEL_FITTER,
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POWER_DOMAIN_TRANSCODER_A,
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POWER_DOMAIN_TRANSCODER_B,
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POWER_DOMAIN_TRANSCODER_C,
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POWER_DOMAIN_TRANSCODER_EDP = POWER_DOMAIN_TRANSCODER_A + 0xF,
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};
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#define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
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#define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
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((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
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#define POWER_DOMAIN_TRANSCODER(tran) ((tran) + POWER_DOMAIN_TRANSCODER_A)
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enum hpd_pin {
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HPD_NONE = 0,
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HPD_PORT_A = HPD_NONE, /* PORT_A is internal */
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@ -1110,8 +1110,8 @@ void assert_pipe(struct drm_i915_private *dev_priv,
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if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
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state = true;
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if (!intel_using_power_well(dev_priv->dev) &&
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cpu_transcoder != TRANSCODER_EDP) {
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if (!intel_display_power_enabled(dev_priv->dev,
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POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
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cur_state = false;
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} else {
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reg = PIPECONF(cpu_transcoder);
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@ -3532,7 +3532,8 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
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/* XXX: Once we have proper panel fitter state tracking implemented with
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* hardware state read/check support we should switch to only disable
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* the panel fitter when we know it's used. */
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if (intel_using_power_well(dev)) {
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if (intel_display_power_enabled(dev,
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POWER_DOMAIN_PIPE_PANEL_FITTER(pipe))) {
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I915_WRITE(PF_CTL(pipe), 0);
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I915_WRITE(PF_WIN_SZ(pipe), 0);
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}
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@ -6039,8 +6040,8 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
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enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
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uint32_t tmp;
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if (!intel_using_power_well(dev_priv->dev) &&
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cpu_transcoder != TRANSCODER_EDP)
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if (!intel_display_power_enabled(dev,
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POWER_DOMAIN_TRANSCODER(cpu_transcoder)))
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return false;
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tmp = I915_READ(PIPECONF(cpu_transcoder));
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@ -754,7 +754,8 @@ extern void intel_update_fbc(struct drm_device *dev);
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extern void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
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extern void intel_gpu_ips_teardown(void);
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extern bool intel_using_power_well(struct drm_device *dev);
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extern bool intel_display_power_enabled(struct drm_device *dev,
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enum intel_display_power_domain domain);
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extern void intel_init_power_well(struct drm_device *dev);
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extern void intel_set_power_well(struct drm_device *dev, bool enable);
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extern void intel_enable_gt_powersave(struct drm_device *dev);
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@ -4344,15 +4344,31 @@ void intel_init_clock_gating(struct drm_device *dev)
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* enable it, so check if it's enabled and also check if we've requested it to
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* be enabled.
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*/
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bool intel_using_power_well(struct drm_device *dev)
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bool intel_display_power_enabled(struct drm_device *dev,
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enum intel_display_power_domain domain)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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if (IS_HASWELL(dev))
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if (!HAS_POWER_WELL(dev))
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return true;
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switch (domain) {
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case POWER_DOMAIN_PIPE_A:
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case POWER_DOMAIN_TRANSCODER_EDP:
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return true;
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case POWER_DOMAIN_PIPE_B:
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case POWER_DOMAIN_PIPE_C:
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case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
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case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
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case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
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case POWER_DOMAIN_TRANSCODER_A:
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case POWER_DOMAIN_TRANSCODER_B:
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case POWER_DOMAIN_TRANSCODER_C:
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return I915_READ(HSW_PWR_WELL_DRIVER) ==
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(HSW_PWR_WELL_ENABLE | HSW_PWR_WELL_STATE);
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else
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return true;
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default:
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BUG();
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}
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}
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void intel_set_power_well(struct drm_device *dev, bool enable)
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