X-Gene DTS changes queued for v4.4
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This commit is contained in:
Arnd Bergmann
commit
b8faca6af8
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@ -0,0 +1,17 @@
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APM X-GENE SoC series SCU Registers
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This system clock unit contain various register that control block resets,
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clock enable/disables, clock divisors and other deepsleep registers.
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Properties:
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- compatible : should contain two values. First value must be:
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- "apm,xgene-scu"
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second value must be always "syscon".
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- reg : offset and length of the register set.
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Example :
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scu: system-clk-controller@17000000 {
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compatible = "apm,xgene-scu","syscon";
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reg = <0x0 0x17000000 0x0 0x400>;
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};
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@ -7,6 +7,7 @@ representation in the device tree should be done as under:-
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Required properties:
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- compatible : should be one of
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"apm,potenza-pmu"
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"arm,armv8-pmuv3"
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"arm,cortex-a17-pmu"
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"arm,cortex-a15-pmu"
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@ -788,6 +788,11 @@ S: Maintained
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F: drivers/net/appletalk/
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F: net/appletalk/
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APPLIED MICRO (APM) X-GENE DEVICE TREE SUPPORT
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M: Duc Dang <dhdang@apm.com>
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S: Supported
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F: arch/arm64/boot/dts/apm/
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APPLIED MICRO (APM) X-GENE SOC ETHERNET DRIVER
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M: Iyappan Subramanian <isubramanian@apm.com>
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M: Keyur Chudgar <kchudgar@apm.com>
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@ -1,4 +1,5 @@
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dtb-$(CONFIG_ARCH_XGENE) += apm-mustang.dtb
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dtb-$(CONFIG_ARCH_XGENE) += apm-merlin.dtb
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always := $(dtb-y)
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subdir-y := $(dts-dirs)
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@ -0,0 +1,72 @@
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/*
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* dts file for AppliedMicro (APM) Merlin Board
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*
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* Copyright (C) 2015, Applied Micro Circuits Corporation
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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/dts-v1/;
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/include/ "apm-shadowcat.dtsi"
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/ {
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model = "APM X-Gene Merlin board";
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compatible = "apm,merlin", "apm,xgene-shadowcat";
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chosen { };
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memory {
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device_type = "memory";
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reg = < 0x1 0x00000000 0x0 0x80000000 >;
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};
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gpio-keys {
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compatible = "gpio-keys";
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button@1 {
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label = "POWER";
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linux,code = <116>;
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linux,input-type = <0x1>;
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interrupts = <0x0 0x28 0x1>;
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};
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};
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poweroff_mbox: poweroff_mbox@10548000 {
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compatible = "syscon";
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reg = <0x0 0x10548000 0x0 0x30>;
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};
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poweroff: poweroff@10548010 {
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compatible = "syscon-poweroff";
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regmap = <&poweroff_mbox>;
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offset = <0x10>;
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mask = <0x1>;
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};
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};
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&serial0 {
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status = "ok";
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};
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&sata1 {
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status = "ok";
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};
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&sata2 {
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status = "ok";
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};
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&sata3 {
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status = "ok";
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};
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&sgenet0 {
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status = "ok";
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};
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&xgenet1 {
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status = "ok";
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};
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@ -33,6 +33,18 @@
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interrupts = <0x0 0x2d 0x1>;
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};
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};
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poweroff_mbox: poweroff_mbox@10548000 {
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compatible = "syscon";
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reg = <0x0 0x10548000 0x0 0x30>;
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};
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poweroff: poweroff@10548010 {
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compatible = "syscon-poweroff";
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regmap = <&poweroff_mbox>;
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offset = <0x10>;
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mask = <0x1>;
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};
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};
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&pcie0clk {
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@ -0,0 +1,271 @@
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/*
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* dts file for AppliedMicro (APM) X-Gene Shadowcat SOC
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*
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* Copyright (C) 2015, Applied Micro Circuits Corporation
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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/ {
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compatible = "apm,xgene-shadowcat";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu@000 {
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device_type = "cpu";
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compatible = "apm,strega", "arm,armv8";
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reg = <0x0 0x000>;
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enable-method = "spin-table";
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cpu-release-addr = <0x1 0x0000fff8>;
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};
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cpu@001 {
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device_type = "cpu";
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compatible = "apm,strega", "arm,armv8";
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reg = <0x0 0x001>;
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enable-method = "spin-table";
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cpu-release-addr = <0x1 0x0000fff8>;
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};
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cpu@100 {
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device_type = "cpu";
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compatible = "apm,strega", "arm,armv8";
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reg = <0x0 0x100>;
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enable-method = "spin-table";
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cpu-release-addr = <0x1 0x0000fff8>;
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};
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cpu@101 {
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device_type = "cpu";
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compatible = "apm,strega", "arm,armv8";
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reg = <0x0 0x101>;
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enable-method = "spin-table";
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cpu-release-addr = <0x1 0x0000fff8>;
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};
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cpu@200 {
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device_type = "cpu";
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compatible = "apm,strega", "arm,armv8";
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reg = <0x0 0x200>;
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enable-method = "spin-table";
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cpu-release-addr = <0x1 0x0000fff8>;
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};
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cpu@201 {
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device_type = "cpu";
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compatible = "apm,strega", "arm,armv8";
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reg = <0x0 0x201>;
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enable-method = "spin-table";
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cpu-release-addr = <0x1 0x0000fff8>;
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};
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cpu@300 {
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device_type = "cpu";
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compatible = "apm,strega", "arm,armv8";
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reg = <0x0 0x300>;
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enable-method = "spin-table";
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cpu-release-addr = <0x1 0x0000fff8>;
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};
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cpu@301 {
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device_type = "cpu";
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compatible = "apm,strega", "arm,armv8";
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reg = <0x0 0x301>;
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enable-method = "spin-table";
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cpu-release-addr = <0x1 0x0000fff8>;
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};
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};
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gic: interrupt-controller@78090000 {
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compatible = "arm,cortex-a15-gic";
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#interrupt-cells = <3>;
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-controller;
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interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */
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ranges = <0 0 0 0x79000000 0x0 0x800000>; /* MSI Range */
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reg = <0x0 0x78090000 0x0 0x10000>, /* GIC Dist */
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<0x0 0x780A0000 0x0 0x20000>, /* GIC CPU */
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<0x0 0x780C0000 0x0 0x10000>, /* GIC VCPU Control */
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<0x0 0x780E0000 0x0 0x20000>; /* GIC VCPU */
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};
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pmu {
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compatible = "arm,armv8-pmuv3";
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interrupts = <1 12 0xff04>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <1 0 0xff04>, /* Secure Phys IRQ */
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<1 13 0xff04>, /* Non-secure Phys IRQ */
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<1 14 0xff04>, /* Virt IRQ */
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<1 15 0xff04>; /* Hyp IRQ */
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clock-frequency = <50000000>;
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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clocks {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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refclk: refclk {
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compatible = "fixed-clock";
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#clock-cells = <1>;
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clock-frequency = <100000000>;
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clock-output-names = "refclk";
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};
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socpll: socpll@17000120 {
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compatible = "apm,xgene-socpll-clock";
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#clock-cells = <1>;
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clocks = <&refclk 0>;
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reg = <0x0 0x17000120 0x0 0x1000>;
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clock-output-names = "socpll";
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};
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socplldiv2: socplldiv2 {
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compatible = "fixed-factor-clock";
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#clock-cells = <1>;
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clocks = <&socpll 0>;
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clock-mult = <1>;
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clock-div = <2>;
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clock-output-names = "socplldiv2";
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};
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pcie0clk: pcie0clk@1f2bc000 {
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compatible = "apm,xgene-device-clock";
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#clock-cells = <1>;
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clocks = <&socplldiv2 0>;
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reg = <0x0 0x1f2bc000 0x0 0x1000>;
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reg-names = "csr-reg";
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clock-output-names = "pcie0clk";
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};
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xge0clk: xge0clk@1f61c000 {
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compatible = "apm,xgene-device-clock";
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#clock-cells = <1>;
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clocks = <&socplldiv2 0>;
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reg = <0x0 0x1f61c000 0x0 0x1000>;
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reg-names = "csr-reg";
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enable-mask = <0x3>;
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csr-mask = <0x3>;
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clock-output-names = "xge0clk";
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};
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xge1clk: xge1clk@1f62c000 {
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compatible = "apm,xgene-device-clock";
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#clock-cells = <1>;
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clocks = <&socplldiv2 0>;
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reg = <0x0 0x1f62c000 0x0 0x1000>;
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reg-names = "csr-reg";
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enable-mask = <0x3>;
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csr-mask = <0x3>;
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clock-output-names = "xge1clk";
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};
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};
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scu: system-clk-controller@17000000 {
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compatible = "apm,xgene-scu","syscon";
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reg = <0x0 0x17000000 0x0 0x400>;
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};
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reboot: reboot@17000014 {
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compatible = "syscon-reboot";
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regmap = <&scu>;
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offset = <0x14>;
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mask = <0x1>;
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};
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serial0: serial@10600000 {
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device_type = "serial";
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compatible = "ns16550";
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reg = <0 0x10600000 0x0 0x1000>;
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reg-shift = <2>;
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clock-frequency = <10000000>;
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interrupt-parent = <&gic>;
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interrupts = <0x0 0x4c 0x4>;
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};
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sata1: sata@1a000000 {
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compatible = "apm,xgene-ahci";
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reg = <0x0 0x1a000000 0x0 0x1000>,
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<0x0 0x1f200000 0x0 0x1000>,
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<0x0 0x1f20d000 0x0 0x1000>,
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<0x0 0x1f20e000 0x0 0x1000>;
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interrupts = <0x0 0x5a 0x4>;
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dma-coherent;
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};
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sata2: sata@1a200000 {
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compatible = "apm,xgene-ahci";
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reg = <0x0 0x1a200000 0x0 0x1000>,
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<0x0 0x1f210000 0x0 0x1000>,
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<0x0 0x1f21d000 0x0 0x1000>,
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<0x0 0x1f21e000 0x0 0x1000>;
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interrupts = <0x0 0x5b 0x4>;
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dma-coherent;
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};
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sata3: sata@1a400000 {
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compatible = "apm,xgene-ahci";
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reg = <0x0 0x1a400000 0x0 0x1000>,
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<0x0 0x1f220000 0x0 0x1000>,
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<0x0 0x1f22d000 0x0 0x1000>,
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<0x0 0x1f22e000 0x0 0x1000>;
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interrupts = <0x0 0x5c 0x4>;
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dma-coherent;
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};
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sbgpio: sbgpio@17001000{
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compatible = "apm,xgene-gpio-sb";
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reg = <0x0 0x17001000 0x0 0x400>;
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#gpio-cells = <2>;
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gpio-controller;
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interrupts = <0x0 0x28 0x1>,
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<0x0 0x29 0x1>,
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<0x0 0x2a 0x1>,
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<0x0 0x2b 0x1>,
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<0x0 0x2c 0x1>,
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<0x0 0x2d 0x1>,
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<0x0 0x2e 0x1>,
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<0x0 0x2f 0x1>;
|
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};
|
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|
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sgenet0: ethernet@1f610000 {
|
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compatible = "apm,xgene2-sgenet";
|
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status = "disabled";
|
||||
reg = <0x0 0x1f610000 0x0 0x10000>,
|
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<0x0 0x1f600000 0x0 0Xd100>,
|
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<0x0 0x20000000 0x0 0X20000>;
|
||||
interrupts = <0 96 4>,
|
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<0 97 4>;
|
||||
dma-coherent;
|
||||
clocks = <&xge0clk 0>;
|
||||
local-mac-address = [00 01 73 00 00 01];
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
|
||||
xgenet1: ethernet@1f620000 {
|
||||
compatible = "apm,xgene2-xgenet";
|
||||
status = "disabled";
|
||||
reg = <0x0 0x1f620000 0x0 0x10000>,
|
||||
<0x0 0x1f600000 0x0 0Xd100>,
|
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<0x0 0x20000000 0x0 0X220000>;
|
||||
interrupts = <0 108 4>,
|
||||
<0 109 4>;
|
||||
port-id = <1>;
|
||||
dma-coherent;
|
||||
clocks = <&xge1clk 0>;
|
||||
local-mac-address = [00 01 73 00 00 02];
|
||||
phy-connection-type = "xgmii";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -97,6 +97,11 @@
|
|||
clock-frequency = <50000000>;
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "apm,potenza-pmu", "arm,armv8-pmuv3";
|
||||
interrupts = <1 12 0xff04>;
|
||||
};
|
||||
|
||||
soc {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
|
|
@ -396,6 +401,18 @@
|
|||
0x0 0x1f 0x4>;
|
||||
};
|
||||
|
||||
scu: system-clk-controller@17000000 {
|
||||
compatible = "apm,xgene-scu","syscon";
|
||||
reg = <0x0 0x17000000 0x0 0x400>;
|
||||
};
|
||||
|
||||
reboot: reboot@17000014 {
|
||||
compatible = "syscon-reboot";
|
||||
regmap = <&scu>;
|
||||
offset = <0x14>;
|
||||
mask = <0x1>;
|
||||
};
|
||||
|
||||
csw: csw@7e200000 {
|
||||
compatible = "apm,xgene-csw", "syscon";
|
||||
reg = <0x0 0x7e200000 0x0 0x1000>;
|
||||
|
|
|
|||
Loading…
Reference in New Issue