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ARM: EXYNOS: Clock settings for SATA and SATA PHY 

This patch adds neccessary clock entries for SATA, SATA PHY and
I2C_SATAPHY

Signed-off-by: Vasanth Ananthan <vasanth.a@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This commit is contained in:
Vasanth Ananthan 2012-11-20 21:00:01 +09:00 committed by Kukjin Kim
parent 0f9e03591f
commit b8edec0f4e
1 changed files with 18 additions and 3 deletions
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21
arch/arm/mach-exynos/clock-exynos5.c
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@ -658,15 +658,20 @@ static struct clk exynos5_init_clocks_off[] = {
.ctrlbit = (1 << 15),
}, {
.name = "sata",
.devname = "ahci",
.devname = "exynos5-sata",
.parent = &exynos5_clk_aclk_200.clk,
.enable = exynos5_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 6),
}, {
.name = "sata_phy",
.name = "sata-phy",
.devname = "exynos5-sata-phy",
.parent = &exynos5_clk_aclk_200.clk,
.enable = exynos5_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 24),
}, {
.name = "sata_phy_i2c",
.name = "i2c",
.devname = "exynos5-sata-phy-i2c",
.parent = &exynos5_clk_aclk_200.clk,
.enable = exynos5_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 25),
}, {
@ -1241,6 +1246,16 @@ static struct clksrc_clk exynos5_clksrcs[] = {
.sources = &exynos5_clkset_aclk,
.reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 20, .size = 1 },
.reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 24, .size = 3 },
}, {
.clk = {
.name = "sclk_sata",
.devname = "exynos5-sata",
.enable = exynos5_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 24),
},
.sources = &exynos5_clkset_aclk,
.reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 24, .size = 1 },
.reg_div = { .reg = EXYNOS5_CLKDIV_FSYS0, .shift = 20, .size = 4 },
}, {
.clk = {
.name = "sclk_gscl_wrap",