net: z85230: add some required spaces
Add space required before the open parenthesis '(' and '{'.
Add space required after that close brace '}' and ','
Add spaces required around that '=' , '&', '*', '|', '+', '/' and '-'.
Signed-off-by: Peng Li <lipeng321@huawei.com>
Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Peng Li
David S. Miller
parent
a04544ffe8
commit
b87a5cf656
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@ -71,9 +71,9 @@
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static inline int z8530_read_port(unsigned long p)
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{
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u8 r=inb(Z8530_PORT_OF(p));
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u8 r = inb(Z8530_PORT_OF(p));
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if(p&Z8530_PORT_SLEEP) /* gcc should figure this out efficiently ! */
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if (p & Z8530_PORT_SLEEP) /* gcc should figure this out efficiently ! */
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udelay(5);
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return r;
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}
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@ -95,8 +95,8 @@ static inline int z8530_read_port(unsigned long p)
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static inline void z8530_write_port(unsigned long p, u8 d)
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{
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outb(d,Z8530_PORT_OF(p));
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if(p&Z8530_PORT_SLEEP)
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outb(d, Z8530_PORT_OF(p));
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if (p & Z8530_PORT_SLEEP)
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udelay(5);
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}
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@ -116,7 +116,7 @@ static void z8530_tx_done(struct z8530_channel *c);
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static inline u8 read_zsreg(struct z8530_channel *c, u8 reg)
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{
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if(reg)
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if (reg)
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z8530_write_port(c->ctrlio, reg);
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return z8530_read_port(c->ctrlio);
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}
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@ -133,7 +133,7 @@ static inline u8 read_zsdata(struct z8530_channel *c)
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{
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u8 r;
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r=z8530_read_port(c->dataio);
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r = z8530_read_port(c->dataio);
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return r;
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}
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@ -151,7 +151,7 @@ static inline u8 read_zsdata(struct z8530_channel *c)
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*/
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static inline void write_zsreg(struct z8530_channel *c, u8 reg, u8 val)
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{
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if(reg)
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if (reg)
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z8530_write_port(c->ctrlio, reg);
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z8530_write_port(c->ctrlio, val);
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}
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@ -184,7 +184,7 @@ static inline void write_zsdata(struct z8530_channel *c, u8 val)
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/* Register loading parameters for a dead port
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*/
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u8 z8530_dead_port[]=
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u8 z8530_dead_port[] =
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{
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255
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};
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@ -197,22 +197,22 @@ EXPORT_SYMBOL(z8530_dead_port);
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* "kilostream" service, and most other similar services.
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*/
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u8 z8530_hdlc_kilostream[]=
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u8 z8530_hdlc_kilostream[] =
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{
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4, SYNC_ENAB|SDLC|X1CLK,
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4, SYNC_ENAB | SDLC | X1CLK,
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2, 0, /* No vector */
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1, 0,
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3, ENT_HM|RxCRC_ENAB|Rx8,
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5, TxCRC_ENAB|RTS|TxENAB|Tx8|DTR,
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3, ENT_HM | RxCRC_ENAB | Rx8,
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5, TxCRC_ENAB | RTS | TxENAB | Tx8 | DTR,
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9, 0, /* Disable interrupts */
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6, 0xFF,
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7, FLAG,
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10, ABUNDER|NRZ|CRCPS,/*MARKIDLE ??*/
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10, ABUNDER | NRZ | CRCPS,/*MARKIDLE ??*/
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11, TCTRxCP,
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14, DISDPLL,
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15, DCDIE|SYNCIE|CTSIE|TxUIE|BRKIE,
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1, EXT_INT_ENAB|TxINT_ENAB|INT_ALL_Rx,
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9, NV|MIE|NORESET,
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15, DCDIE | SYNCIE | CTSIE | TxUIE | BRKIE,
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1, EXT_INT_ENAB | TxINT_ENAB | INT_ALL_Rx,
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9, NV | MIE | NORESET,
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255
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};
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EXPORT_SYMBOL(z8530_hdlc_kilostream);
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@ -220,22 +220,22 @@ EXPORT_SYMBOL(z8530_hdlc_kilostream);
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/* As above but for enhanced chips.
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*/
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u8 z8530_hdlc_kilostream_85230[]=
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u8 z8530_hdlc_kilostream_85230[] =
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{
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4, SYNC_ENAB|SDLC|X1CLK,
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4, SYNC_ENAB | SDLC | X1CLK,
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2, 0, /* No vector */
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1, 0,
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3, ENT_HM|RxCRC_ENAB|Rx8,
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5, TxCRC_ENAB|RTS|TxENAB|Tx8|DTR,
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3, ENT_HM | RxCRC_ENAB | Rx8,
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5, TxCRC_ENAB | RTS | TxENAB | Tx8 | DTR,
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9, 0, /* Disable interrupts */
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6, 0xFF,
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7, FLAG,
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10, ABUNDER|NRZ|CRCPS, /* MARKIDLE?? */
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10, ABUNDER | NRZ | CRCPS, /* MARKIDLE?? */
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11, TCTRxCP,
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14, DISDPLL,
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15, DCDIE|SYNCIE|CTSIE|TxUIE|BRKIE,
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1, EXT_INT_ENAB|TxINT_ENAB|INT_ALL_Rx,
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9, NV|MIE|NORESET,
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15, DCDIE | SYNCIE | CTSIE | TxUIE | BRKIE,
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1, EXT_INT_ENAB | TxINT_ENAB | INT_ALL_Rx,
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9, NV | MIE | NORESET,
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23, 3, /* Extended mode AUTO TX and EOM*/
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255
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@ -260,7 +260,7 @@ static void z8530_flush_fifo(struct z8530_channel *c)
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read_zsreg(c, R1);
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read_zsreg(c, R1);
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read_zsreg(c, R1);
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if(c->dev->type==Z85230)
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if (c->dev->type == Z85230)
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{
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read_zsreg(c, R1);
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read_zsreg(c, R1);
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@ -315,40 +315,40 @@ static void z8530_rtsdtr(struct z8530_channel *c, int set)
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static void z8530_rx(struct z8530_channel *c)
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{
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u8 ch,stat;
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u8 ch, stat;
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while(1)
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while (1)
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{
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/* FIFO empty ? */
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if(!(read_zsreg(c, R0)&1))
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if (!(read_zsreg(c, R0) & 1))
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break;
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ch=read_zsdata(c);
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stat=read_zsreg(c, R1);
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ch = read_zsdata(c);
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stat = read_zsreg(c, R1);
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/* Overrun ?
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*/
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if(c->count < c->max)
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if (c->count < c->max)
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{
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*c->dptr++=ch;
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*c->dptr++ = ch;
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c->count++;
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}
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if(stat&END_FR)
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if (stat & END_FR)
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{
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/* Error ?
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*/
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if(stat&(Rx_OVR|CRC_ERR))
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if (stat & (Rx_OVR | CRC_ERR))
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{
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/* Rewind the buffer and return */
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if(c->skb)
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c->dptr=c->skb->data;
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c->count=0;
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if(stat&Rx_OVR)
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if (c->skb)
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c->dptr = c->skb->data;
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c->count = 0;
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if (stat & Rx_OVR)
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{
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pr_warn("%s: overrun\n", c->dev->name);
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c->rx_overrun++;
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}
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if(stat&CRC_ERR)
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if (stat & CRC_ERR)
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{
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c->rx_crc_err++;
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/* printk("crc error\n"); */
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@ -381,9 +381,9 @@ static void z8530_rx(struct z8530_channel *c)
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static void z8530_tx(struct z8530_channel *c)
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{
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while(c->txcount) {
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while (c->txcount) {
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/* FIFO full ? */
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if(!(read_zsreg(c, R0)&4))
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if (!(read_zsreg(c, R0) & 4))
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return;
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c->txcount--;
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/* Shovel out the byte
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@ -391,10 +391,10 @@ static void z8530_tx(struct z8530_channel *c)
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write_zsreg(c, R8, *c->tx_ptr++);
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write_zsctrl(c, RES_H_IUS);
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/* We are about to underflow */
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if(c->txcount==0)
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if (c->txcount == 0)
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{
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write_zsctrl(c, RES_EOM_L);
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write_zsreg(c, R10, c->regs[10]&~ABUNDER);
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write_zsreg(c, R10, c->regs[10] & ~ABUNDER);
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}
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}
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@ -471,7 +471,7 @@ EXPORT_SYMBOL(z8530_sync);
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static void z8530_dma_rx(struct z8530_channel *chan)
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{
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if(chan->rxdma_on)
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if (chan->rxdma_on)
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{
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/* Special condition check only */
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u8 status;
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@ -479,12 +479,11 @@ static void z8530_dma_rx(struct z8530_channel *chan)
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read_zsreg(chan, R7);
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read_zsreg(chan, R6);
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status=read_zsreg(chan, R1);
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status = read_zsreg(chan, R1);
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if(status&END_FR)
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{
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if (status & END_FR)
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z8530_rx_done(chan); /* Fire up the next one */
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}
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write_zsctrl(chan, ERR_RES);
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write_zsctrl(chan, RES_H_IUS);
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} else {
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@ -502,7 +501,7 @@ static void z8530_dma_rx(struct z8530_channel *chan)
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*/
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static void z8530_dma_tx(struct z8530_channel *chan)
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{
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if(!chan->dma_tx)
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if (!chan->dma_tx)
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{
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pr_warn("Hey who turned the DMA off?\n");
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z8530_tx(chan);
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@ -526,21 +525,21 @@ static void z8530_dma_status(struct z8530_channel *chan)
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{
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u8 status, altered;
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status=read_zsreg(chan, R0);
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altered=chan->status^status;
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status = read_zsreg(chan, R0);
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altered = chan->status ^ status;
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chan->status=status;
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chan->status = status;
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if(chan->dma_tx)
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if (chan->dma_tx)
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{
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if(status&TxEOM)
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if (status & TxEOM)
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{
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unsigned long flags;
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flags=claim_dma_lock();
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flags = claim_dma_lock();
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disable_dma(chan->txdma);
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clear_dma_ff(chan->txdma);
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chan->txdma_on=0;
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chan->txdma_on = 0;
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release_dma_lock(flags);
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z8530_tx_done(chan);
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}
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@ -594,9 +593,9 @@ static void z8530_rx_clear(struct z8530_channel *c)
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u8 stat;
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read_zsdata(c);
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stat=read_zsreg(c, R1);
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stat = read_zsreg(c, R1);
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if(stat&END_FR)
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if (stat & END_FR)
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write_zsctrl(c, RES_Rx_CRC);
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/* Clear irq
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*/
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@ -630,9 +629,9 @@ static void z8530_tx_clear(struct z8530_channel *c)
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static void z8530_status_clear(struct z8530_channel *chan)
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{
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u8 status=read_zsreg(chan, R0);
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u8 status = read_zsreg(chan, R0);
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if(status&TxEOM)
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if (status & TxEOM)
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write_zsctrl(chan, ERR_RES);
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write_zsctrl(chan, RES_EXT_INT);
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write_zsctrl(chan, RES_H_IUS);
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@ -663,25 +662,26 @@ EXPORT_SYMBOL(z8530_nop);
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irqreturn_t z8530_interrupt(int irq, void *dev_id)
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{
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struct z8530_dev *dev=dev_id;
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struct z8530_dev *dev = dev_id;
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u8 intr;
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static volatile int locker=0;
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int work=0;
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int work = 0;
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struct z8530_irqhandler *irqs;
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if(locker)
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if (locker)
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{
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pr_err("IRQ re-enter\n");
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return IRQ_NONE;
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}
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locker=1;
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locker = 1;
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spin_lock(&dev->lock);
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while(++work<5000)
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while (++work < 5000)
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{
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intr = read_zsreg(&dev->chanA, R3);
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if(!(intr & (CHARxIP|CHATxIP|CHAEXT|CHBRxIP|CHBTxIP|CHBEXT)))
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if (!(intr &
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(CHARxIP | CHATxIP | CHAEXT | CHBRxIP | CHBTxIP | CHBEXT)))
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break;
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/* This holds the IRQ status. On the 8530 you must read it
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@ -692,46 +692,46 @@ irqreturn_t z8530_interrupt(int irq, void *dev_id)
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* an IRQ for someone else remember
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*/
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irqs=dev->chanA.irqs;
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irqs = dev->chanA.irqs;
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if(intr & (CHARxIP|CHATxIP|CHAEXT))
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if (intr & (CHARxIP | CHATxIP | CHAEXT))
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{
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if(intr&CHARxIP)
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if (intr & CHARxIP)
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irqs->rx(&dev->chanA);
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if(intr&CHATxIP)
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if (intr & CHATxIP)
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irqs->tx(&dev->chanA);
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if(intr&CHAEXT)
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if (intr & CHAEXT)
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irqs->status(&dev->chanA);
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}
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irqs=dev->chanB.irqs;
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irqs = dev->chanB.irqs;
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if(intr & (CHBRxIP|CHBTxIP|CHBEXT))
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if (intr & (CHBRxIP | CHBTxIP | CHBEXT))
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{
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if(intr&CHBRxIP)
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if (intr & CHBRxIP)
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irqs->rx(&dev->chanB);
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if(intr&CHBTxIP)
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if (intr & CHBTxIP)
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irqs->tx(&dev->chanB);
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if(intr&CHBEXT)
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if (intr & CHBEXT)
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irqs->status(&dev->chanB);
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}
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}
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spin_unlock(&dev->lock);
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if(work==5000)
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if (work == 5000)
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pr_err("%s: interrupt jammed - abort(0x%X)!\n",
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dev->name, intr);
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/* Ok all done */
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locker=0;
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locker = 0;
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return IRQ_HANDLED;
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}
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EXPORT_SYMBOL(z8530_interrupt);
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static const u8 reg_init[16]=
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static const u8 reg_init[16] =
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{
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0,0,0,0,
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0,0,0,0,
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0,0,0,0,
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0x55,0,0,0
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0, 0, 0, 0,
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0, 0, 0, 0,
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0, 0, 0, 0,
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0x55, 0, 0, 0
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};
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/**
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@ -749,7 +749,7 @@ int z8530_sync_open(struct net_device *dev, struct z8530_channel *c)
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spin_lock_irqsave(c->lock, flags);
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c->sync = 1;
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c->mtu = dev->mtu+64;
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c->mtu = dev->mtu + 64;
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c->count = 0;
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c->skb = NULL;
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c->skb2 = NULL;
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@ -758,11 +758,11 @@ int z8530_sync_open(struct net_device *dev, struct z8530_channel *c)
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/* This loads the double buffer up */
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z8530_rx_done(c); /* Load the frame ring */
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z8530_rx_done(c); /* Load the backup frame */
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z8530_rtsdtr(c,1);
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z8530_rtsdtr(c, 1);
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c->dma_tx = 0;
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c->regs[R1]|=TxINT_ENAB;
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c->regs[R1] |= TxINT_ENAB;
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write_zsreg(c, R1, c->regs[R1]);
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write_zsreg(c, R3, c->regs[R3]|RxENABLE);
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write_zsreg(c, R3, c->regs[R3] | RxENABLE);
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spin_unlock_irqrestore(c->lock, flags);
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return 0;
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@ -787,9 +787,9 @@ int z8530_sync_close(struct net_device *dev, struct z8530_channel *c)
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c->max = 0;
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c->sync = 0;
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chk=read_zsreg(c,R0);
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chk = read_zsreg(c, R0);
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write_zsreg(c, R3, c->regs[R3]);
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z8530_rtsdtr(c,0);
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z8530_rtsdtr(c, 0);
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spin_unlock_irqrestore(c->lock, flags);
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return 0;
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@ -810,7 +810,7 @@ int z8530_sync_dma_open(struct net_device *dev, struct z8530_channel *c)
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unsigned long cflags, dflags;
|
||||
|
||||
c->sync = 1;
|
||||
c->mtu = dev->mtu+64;
|
||||
c->mtu = dev->mtu + 64;
|
||||
c->count = 0;
|
||||
c->skb = NULL;
|
||||
c->skb2 = NULL;
|
||||
|
|
@ -825,27 +825,27 @@ int z8530_sync_dma_open(struct net_device *dev, struct z8530_channel *c)
|
|||
* should be fine.
|
||||
*/
|
||||
|
||||
if(c->mtu > PAGE_SIZE/2)
|
||||
if (c->mtu > PAGE_SIZE / 2)
|
||||
return -EMSGSIZE;
|
||||
|
||||
c->rx_buf[0]=(void *)get_zeroed_page(GFP_KERNEL|GFP_DMA);
|
||||
c->rx_buf[0] = (void *)get_zeroed_page(GFP_KERNEL | GFP_DMA);
|
||||
if (!c->rx_buf[0])
|
||||
return -ENOBUFS;
|
||||
c->rx_buf[1]=c->rx_buf[0]+PAGE_SIZE/2;
|
||||
c->rx_buf[1] = c->rx_buf[0] + PAGE_SIZE / 2;
|
||||
|
||||
c->tx_dma_buf[0]=(void *)get_zeroed_page(GFP_KERNEL|GFP_DMA);
|
||||
c->tx_dma_buf[0] = (void *)get_zeroed_page(GFP_KERNEL | GFP_DMA);
|
||||
if (!c->tx_dma_buf[0])
|
||||
{
|
||||
free_page((unsigned long)c->rx_buf[0]);
|
||||
c->rx_buf[0]=NULL;
|
||||
c->rx_buf[0] = NULL;
|
||||
return -ENOBUFS;
|
||||
}
|
||||
c->tx_dma_buf[1]=c->tx_dma_buf[0]+PAGE_SIZE/2;
|
||||
c->tx_dma_buf[1] = c->tx_dma_buf[0] + PAGE_SIZE / 2;
|
||||
|
||||
c->tx_dma_used=0;
|
||||
c->tx_dma_used = 0;
|
||||
c->dma_tx = 1;
|
||||
c->dma_num=0;
|
||||
c->dma_ready=1;
|
||||
c->dma_num = 0;
|
||||
c->dma_ready = 1;
|
||||
|
||||
/* Enable DMA control mode
|
||||
*/
|
||||
|
|
@ -855,21 +855,21 @@ int z8530_sync_dma_open(struct net_device *dev, struct z8530_channel *c)
|
|||
/* TX DMA via DIR/REQ
|
||||
*/
|
||||
|
||||
c->regs[R14]|= DTRREQ;
|
||||
c->regs[R14] |= DTRREQ;
|
||||
write_zsreg(c, R14, c->regs[R14]);
|
||||
|
||||
c->regs[R1]&= ~TxINT_ENAB;
|
||||
c->regs[R1] &= ~TxINT_ENAB;
|
||||
write_zsreg(c, R1, c->regs[R1]);
|
||||
|
||||
/* RX DMA via W/Req
|
||||
*/
|
||||
|
||||
c->regs[R1]|= WT_FN_RDYFN;
|
||||
c->regs[R1]|= WT_RDY_RT;
|
||||
c->regs[R1]|= INT_ERR_Rx;
|
||||
c->regs[R1]&= ~TxINT_ENAB;
|
||||
c->regs[R1] |= WT_FN_RDYFN;
|
||||
c->regs[R1] |= WT_RDY_RT;
|
||||
c->regs[R1] |= INT_ERR_Rx;
|
||||
c->regs[R1] &= ~TxINT_ENAB;
|
||||
write_zsreg(c, R1, c->regs[R1]);
|
||||
c->regs[R1]|= WT_RDY_ENAB;
|
||||
c->regs[R1] |= WT_RDY_ENAB;
|
||||
write_zsreg(c, R1, c->regs[R1]);
|
||||
|
||||
/* DMA interrupts
|
||||
|
|
@ -878,11 +878,11 @@ int z8530_sync_dma_open(struct net_device *dev, struct z8530_channel *c)
|
|||
/* Set up the DMA configuration
|
||||
*/
|
||||
|
||||
dflags=claim_dma_lock();
|
||||
dflags = claim_dma_lock();
|
||||
|
||||
disable_dma(c->rxdma);
|
||||
clear_dma_ff(c->rxdma);
|
||||
set_dma_mode(c->rxdma, DMA_MODE_READ|0x10);
|
||||
set_dma_mode(c->rxdma, DMA_MODE_READ | 0x10);
|
||||
set_dma_addr(c->rxdma, virt_to_bus(c->rx_buf[0]));
|
||||
set_dma_count(c->rxdma, c->mtu);
|
||||
enable_dma(c->rxdma);
|
||||
|
|
@ -902,8 +902,8 @@ int z8530_sync_dma_open(struct net_device *dev, struct z8530_channel *c)
|
|||
c->tx_dma_used = 1;
|
||||
|
||||
c->irqs = &z8530_dma_sync;
|
||||
z8530_rtsdtr(c,1);
|
||||
write_zsreg(c, R3, c->regs[R3]|RxENABLE);
|
||||
z8530_rtsdtr(c, 1);
|
||||
write_zsreg(c, R3, c->regs[R3] | RxENABLE);
|
||||
|
||||
spin_unlock_irqrestore(c->lock, cflags);
|
||||
|
||||
|
|
@ -949,27 +949,27 @@ int z8530_sync_dma_close(struct net_device *dev, struct z8530_channel *c)
|
|||
/* Disable DMA control mode
|
||||
*/
|
||||
|
||||
c->regs[R1]&= ~WT_RDY_ENAB;
|
||||
c->regs[R1] &= ~WT_RDY_ENAB;
|
||||
write_zsreg(c, R1, c->regs[R1]);
|
||||
c->regs[R1]&= ~(WT_RDY_RT|WT_FN_RDYFN|INT_ERR_Rx);
|
||||
c->regs[R1]|= INT_ALL_Rx;
|
||||
c->regs[R1] &= ~(WT_RDY_RT | WT_FN_RDYFN | INT_ERR_Rx);
|
||||
c->regs[R1] |= INT_ALL_Rx;
|
||||
write_zsreg(c, R1, c->regs[R1]);
|
||||
c->regs[R14]&= ~DTRREQ;
|
||||
c->regs[R14] &= ~DTRREQ;
|
||||
write_zsreg(c, R14, c->regs[R14]);
|
||||
|
||||
if(c->rx_buf[0])
|
||||
if (c->rx_buf[0])
|
||||
{
|
||||
free_page((unsigned long)c->rx_buf[0]);
|
||||
c->rx_buf[0]=NULL;
|
||||
c->rx_buf[0] = NULL;
|
||||
}
|
||||
if(c->tx_dma_buf[0])
|
||||
if (c->tx_dma_buf[0])
|
||||
{
|
||||
free_page((unsigned long)c->tx_dma_buf[0]);
|
||||
c->tx_dma_buf[0]=NULL;
|
||||
c->tx_dma_buf[0] = NULL;
|
||||
}
|
||||
chk=read_zsreg(c,R0);
|
||||
chk = read_zsreg(c, R0);
|
||||
write_zsreg(c, R3, c->regs[R3]);
|
||||
z8530_rtsdtr(c,0);
|
||||
z8530_rtsdtr(c, 0);
|
||||
|
||||
spin_unlock_irqrestore(c->lock, flags);
|
||||
|
||||
|
|
@ -993,7 +993,7 @@ int z8530_sync_txdma_open(struct net_device *dev, struct z8530_channel *c)
|
|||
|
||||
printk("Opening sync interface for TX-DMA\n");
|
||||
c->sync = 1;
|
||||
c->mtu = dev->mtu+64;
|
||||
c->mtu = dev->mtu + 64;
|
||||
c->count = 0;
|
||||
c->skb = NULL;
|
||||
c->skb2 = NULL;
|
||||
|
|
@ -1003,14 +1003,14 @@ int z8530_sync_txdma_open(struct net_device *dev, struct z8530_channel *c)
|
|||
* should be fine.
|
||||
*/
|
||||
|
||||
if(c->mtu > PAGE_SIZE/2)
|
||||
if (c->mtu > PAGE_SIZE / 2)
|
||||
return -EMSGSIZE;
|
||||
|
||||
c->tx_dma_buf[0]=(void *)get_zeroed_page(GFP_KERNEL|GFP_DMA);
|
||||
c->tx_dma_buf[0] = (void *)get_zeroed_page(GFP_KERNEL | GFP_DMA);
|
||||
if (!c->tx_dma_buf[0])
|
||||
return -ENOBUFS;
|
||||
|
||||
c->tx_dma_buf[1] = c->tx_dma_buf[0] + PAGE_SIZE/2;
|
||||
c->tx_dma_buf[1] = c->tx_dma_buf[0] + PAGE_SIZE / 2;
|
||||
|
||||
spin_lock_irqsave(c->lock, cflags);
|
||||
|
||||
|
|
@ -1026,9 +1026,9 @@ int z8530_sync_txdma_open(struct net_device *dev, struct z8530_channel *c)
|
|||
c->rxdma_on = 0;
|
||||
c->txdma_on = 0;
|
||||
|
||||
c->tx_dma_used=0;
|
||||
c->dma_num=0;
|
||||
c->dma_ready=1;
|
||||
c->tx_dma_used = 0;
|
||||
c->dma_num = 0;
|
||||
c->dma_ready = 1;
|
||||
c->dma_tx = 1;
|
||||
|
||||
/* Enable DMA control mode
|
||||
|
|
@ -1036,10 +1036,10 @@ int z8530_sync_txdma_open(struct net_device *dev, struct z8530_channel *c)
|
|||
|
||||
/* TX DMA via DIR/REQ
|
||||
*/
|
||||
c->regs[R14]|= DTRREQ;
|
||||
c->regs[R14] |= DTRREQ;
|
||||
write_zsreg(c, R14, c->regs[R14]);
|
||||
|
||||
c->regs[R1]&= ~TxINT_ENAB;
|
||||
c->regs[R1] &= ~TxINT_ENAB;
|
||||
write_zsreg(c, R1, c->regs[R1]);
|
||||
|
||||
/* Set up the DMA configuration
|
||||
|
|
@ -1062,8 +1062,8 @@ int z8530_sync_txdma_open(struct net_device *dev, struct z8530_channel *c)
|
|||
c->tx_dma_used = 1;
|
||||
|
||||
c->irqs = &z8530_txdma_sync;
|
||||
z8530_rtsdtr(c,1);
|
||||
write_zsreg(c, R3, c->regs[R3]|RxENABLE);
|
||||
z8530_rtsdtr(c, 1);
|
||||
write_zsreg(c, R3, c->regs[R3] | RxENABLE);
|
||||
spin_unlock_irqrestore(c->lock, cflags);
|
||||
|
||||
return 0;
|
||||
|
|
@ -1105,22 +1105,22 @@ int z8530_sync_txdma_close(struct net_device *dev, struct z8530_channel *c)
|
|||
/* Disable DMA control mode
|
||||
*/
|
||||
|
||||
c->regs[R1]&= ~WT_RDY_ENAB;
|
||||
c->regs[R1] &= ~WT_RDY_ENAB;
|
||||
write_zsreg(c, R1, c->regs[R1]);
|
||||
c->regs[R1]&= ~(WT_RDY_RT|WT_FN_RDYFN|INT_ERR_Rx);
|
||||
c->regs[R1]|= INT_ALL_Rx;
|
||||
c->regs[R1] &= ~(WT_RDY_RT | WT_FN_RDYFN | INT_ERR_Rx);
|
||||
c->regs[R1] |= INT_ALL_Rx;
|
||||
write_zsreg(c, R1, c->regs[R1]);
|
||||
c->regs[R14]&= ~DTRREQ;
|
||||
c->regs[R14] &= ~DTRREQ;
|
||||
write_zsreg(c, R14, c->regs[R14]);
|
||||
|
||||
if(c->tx_dma_buf[0])
|
||||
if (c->tx_dma_buf[0])
|
||||
{
|
||||
free_page((unsigned long)c->tx_dma_buf[0]);
|
||||
c->tx_dma_buf[0]=NULL;
|
||||
c->tx_dma_buf[0] = NULL;
|
||||
}
|
||||
chk=read_zsreg(c,R0);
|
||||
chk = read_zsreg(c, R0);
|
||||
write_zsreg(c, R3, c->regs[R3]);
|
||||
z8530_rtsdtr(c,0);
|
||||
z8530_rtsdtr(c, 0);
|
||||
|
||||
spin_unlock_irqrestore(c->lock, cflags);
|
||||
return 0;
|
||||
|
|
@ -1130,7 +1130,7 @@ EXPORT_SYMBOL(z8530_sync_txdma_close);
|
|||
/* Name strings for Z8530 chips. SGI claim to have a 130, Zilog deny
|
||||
* it exists...
|
||||
*/
|
||||
static const char *z8530_type_name[]={
|
||||
static const char * const z8530_type_name[] = {
|
||||
"Z8530",
|
||||
"Z85C30",
|
||||
"Z85230"
|
||||
|
|
@ -1165,23 +1165,23 @@ static inline int do_z8530_init(struct z8530_dev *dev)
|
|||
/* NOP the interrupt handlers first - we might get a
|
||||
* floating IRQ transition when we reset the chip
|
||||
*/
|
||||
dev->chanA.irqs=&z8530_nop;
|
||||
dev->chanB.irqs=&z8530_nop;
|
||||
dev->chanA.dcdcheck=DCD;
|
||||
dev->chanB.dcdcheck=DCD;
|
||||
dev->chanA.irqs = &z8530_nop;
|
||||
dev->chanB.irqs = &z8530_nop;
|
||||
dev->chanA.dcdcheck = DCD;
|
||||
dev->chanB.dcdcheck = DCD;
|
||||
|
||||
/* Reset the chip */
|
||||
write_zsreg(&dev->chanA, R9, 0xC0);
|
||||
udelay(200);
|
||||
/* Now check its valid */
|
||||
write_zsreg(&dev->chanA, R12, 0xAA);
|
||||
if(read_zsreg(&dev->chanA, R12)!=0xAA)
|
||||
if (read_zsreg(&dev->chanA, R12) != 0xAA)
|
||||
return -ENODEV;
|
||||
write_zsreg(&dev->chanA, R12, 0x55);
|
||||
if(read_zsreg(&dev->chanA, R12)!=0x55)
|
||||
if (read_zsreg(&dev->chanA, R12) != 0x55)
|
||||
return -ENODEV;
|
||||
|
||||
dev->type=Z8530;
|
||||
dev->type = Z8530;
|
||||
|
||||
/* See the application note.
|
||||
*/
|
||||
|
|
@ -1192,12 +1192,12 @@ static inline int do_z8530_init(struct z8530_dev *dev)
|
|||
* the chip is enhanced.
|
||||
*/
|
||||
|
||||
if(read_zsreg(&dev->chanA, R15)==0x01)
|
||||
if (read_zsreg(&dev->chanA, R15) == 0x01)
|
||||
{
|
||||
/* This C30 versus 230 detect is from Klaus Kudielka's dmascc */
|
||||
/* Put a char in the fifo */
|
||||
write_zsreg(&dev->chanA, R8, 0);
|
||||
if(read_zsreg(&dev->chanA, R0)&Tx_BUF_EMP)
|
||||
if (read_zsreg(&dev->chanA, R0) & Tx_BUF_EMP)
|
||||
dev->type = Z85230; /* Has a FIFO */
|
||||
else
|
||||
dev->type = Z85C30; /* Z85C30, 1 byte FIFO */
|
||||
|
|
@ -1214,7 +1214,7 @@ static inline int do_z8530_init(struct z8530_dev *dev)
|
|||
*/
|
||||
|
||||
memcpy(dev->chanA.regs, reg_init, 16);
|
||||
memcpy(dev->chanB.regs, reg_init ,16);
|
||||
memcpy(dev->chanB.regs, reg_init, 16);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -1270,8 +1270,8 @@ int z8530_shutdown(struct z8530_dev *dev)
|
|||
/* Reset the chip */
|
||||
|
||||
spin_lock_irqsave(&dev->lock, flags);
|
||||
dev->chanA.irqs=&z8530_nop;
|
||||
dev->chanB.irqs=&z8530_nop;
|
||||
dev->chanA.irqs = &z8530_nop;
|
||||
dev->chanB.irqs = &z8530_nop;
|
||||
write_zsreg(&dev->chanA, R9, 0xC0);
|
||||
/* We must lock the udelay, the chip is offlimits here */
|
||||
udelay(100);
|
||||
|
|
@ -1297,27 +1297,27 @@ int z8530_channel_load(struct z8530_channel *c, u8 *rtable)
|
|||
|
||||
spin_lock_irqsave(c->lock, flags);
|
||||
|
||||
while(*rtable!=255)
|
||||
while (*rtable != 255)
|
||||
{
|
||||
int reg=*rtable++;
|
||||
int reg = *rtable++;
|
||||
|
||||
if(reg>0x0F)
|
||||
write_zsreg(c, R15, c->regs[15]|1);
|
||||
write_zsreg(c, reg&0x0F, *rtable);
|
||||
if(reg>0x0F)
|
||||
write_zsreg(c, R15, c->regs[15]&~1);
|
||||
c->regs[reg]=*rtable++;
|
||||
if (reg > 0x0F)
|
||||
write_zsreg(c, R15, c->regs[15] | 1);
|
||||
write_zsreg(c, reg & 0x0F, *rtable);
|
||||
if (reg > 0x0F)
|
||||
write_zsreg(c, R15, c->regs[15] & ~1);
|
||||
c->regs[reg] = *rtable++;
|
||||
}
|
||||
c->rx_function=z8530_null_rx;
|
||||
c->skb=NULL;
|
||||
c->tx_skb=NULL;
|
||||
c->tx_next_skb=NULL;
|
||||
c->mtu=1500;
|
||||
c->max=0;
|
||||
c->count=0;
|
||||
c->status=read_zsreg(c, R0);
|
||||
c->sync=1;
|
||||
write_zsreg(c, R3, c->regs[R3]|RxENABLE);
|
||||
c->rx_function = z8530_null_rx;
|
||||
c->skb = NULL;
|
||||
c->tx_skb = NULL;
|
||||
c->tx_next_skb = NULL;
|
||||
c->mtu = 1500;
|
||||
c->max = 0;
|
||||
c->count = 0;
|
||||
c->status = read_zsreg(c, R0);
|
||||
c->sync = 1;
|
||||
write_zsreg(c, R3, c->regs[R3] | RxENABLE);
|
||||
|
||||
spin_unlock_irqrestore(c->lock, flags);
|
||||
return 0;
|
||||
|
|
@ -1342,19 +1342,19 @@ static void z8530_tx_begin(struct z8530_channel *c)
|
|||
{
|
||||
unsigned long flags;
|
||||
|
||||
if(c->tx_skb)
|
||||
if (c->tx_skb)
|
||||
return;
|
||||
|
||||
c->tx_skb=c->tx_next_skb;
|
||||
c->tx_next_skb=NULL;
|
||||
c->tx_ptr=c->tx_next_ptr;
|
||||
c->tx_skb = c->tx_next_skb;
|
||||
c->tx_next_skb = NULL;
|
||||
c->tx_ptr = c->tx_next_ptr;
|
||||
|
||||
if (!c->tx_skb)
|
||||
{
|
||||
/* Idle on */
|
||||
if(c->dma_tx)
|
||||
if (c->dma_tx)
|
||||
{
|
||||
flags=claim_dma_lock();
|
||||
flags = claim_dma_lock();
|
||||
disable_dma(c->txdma);
|
||||
/* Check if we crapped out.
|
||||
*/
|
||||
|
|
@ -1365,11 +1365,11 @@ static void z8530_tx_begin(struct z8530_channel *c)
|
|||
}
|
||||
release_dma_lock(flags);
|
||||
}
|
||||
c->txcount=0;
|
||||
c->txcount = 0;
|
||||
} else {
|
||||
c->txcount=c->tx_skb->len;
|
||||
c->txcount = c->tx_skb->len;
|
||||
|
||||
if(c->dma_tx)
|
||||
if (c->dma_tx)
|
||||
{
|
||||
/* FIXME. DMA is broken for the original 8530,
|
||||
* on the older parts we need to set a flag and
|
||||
|
|
@ -1377,25 +1377,25 @@ static void z8530_tx_begin(struct z8530_channel *c)
|
|||
* stage off
|
||||
*/
|
||||
|
||||
flags=claim_dma_lock();
|
||||
flags = claim_dma_lock();
|
||||
disable_dma(c->txdma);
|
||||
|
||||
/* These two are needed by the 8530/85C30
|
||||
* and must be issued when idling.
|
||||
*/
|
||||
if(c->dev->type!=Z85230)
|
||||
if (c->dev->type != Z85230)
|
||||
{
|
||||
write_zsctrl(c, RES_Tx_CRC);
|
||||
write_zsctrl(c, RES_EOM_L);
|
||||
}
|
||||
write_zsreg(c, R10, c->regs[10]&~ABUNDER);
|
||||
write_zsreg(c, R10, c->regs[10] & ~ABUNDER);
|
||||
clear_dma_ff(c->txdma);
|
||||
set_dma_addr(c->txdma, virt_to_bus(c->tx_ptr));
|
||||
set_dma_count(c->txdma, c->txcount);
|
||||
enable_dma(c->txdma);
|
||||
release_dma_lock(flags);
|
||||
write_zsctrl(c, RES_EOM_L);
|
||||
write_zsreg(c, R5, c->regs[R5]|TxENAB);
|
||||
write_zsreg(c, R5, c->regs[R5] | TxENAB);
|
||||
} else {
|
||||
/* ABUNDER off */
|
||||
write_zsreg(c, R10, c->regs[10]);
|
||||
|
|
@ -1472,35 +1472,35 @@ static void z8530_rx_done(struct z8530_channel *c)
|
|||
|
||||
/* Is our receive engine in DMA mode
|
||||
*/
|
||||
if(c->rxdma_on)
|
||||
if (c->rxdma_on)
|
||||
{
|
||||
/* Save the ready state and the buffer currently
|
||||
* being used as the DMA target
|
||||
*/
|
||||
int ready=c->dma_ready;
|
||||
unsigned char *rxb=c->rx_buf[c->dma_num];
|
||||
int ready = c->dma_ready;
|
||||
unsigned char *rxb = c->rx_buf[c->dma_num];
|
||||
unsigned long flags;
|
||||
|
||||
/* Complete this DMA. Necessary to find the length
|
||||
*/
|
||||
flags=claim_dma_lock();
|
||||
flags = claim_dma_lock();
|
||||
|
||||
disable_dma(c->rxdma);
|
||||
clear_dma_ff(c->rxdma);
|
||||
c->rxdma_on=0;
|
||||
ct=c->mtu-get_dma_residue(c->rxdma);
|
||||
if(ct<0)
|
||||
ct=2; /* Shit happens.. */
|
||||
c->dma_ready=0;
|
||||
c->rxdma_on = 0;
|
||||
ct = c->mtu - get_dma_residue(c->rxdma);
|
||||
if (ct < 0)
|
||||
ct = 2; /* Shit happens.. */
|
||||
c->dma_ready = 0;
|
||||
|
||||
/* Normal case: the other slot is free, start the next DMA
|
||||
* into it immediately.
|
||||
*/
|
||||
|
||||
if(ready)
|
||||
if (ready)
|
||||
{
|
||||
c->dma_num^=1;
|
||||
set_dma_mode(c->rxdma, DMA_MODE_READ|0x10);
|
||||
c->dma_num ^= 1;
|
||||
set_dma_mode(c->rxdma, DMA_MODE_READ | 0x10);
|
||||
set_dma_addr(c->rxdma, virt_to_bus(c->rx_buf[c->dma_num]));
|
||||
set_dma_count(c->rxdma, c->mtu);
|
||||
c->rxdma_on = 1;
|
||||
|
|
@ -1551,7 +1551,7 @@ static void z8530_rx_done(struct z8530_channel *c)
|
|||
* sync IRQ for the RT_LOCK area.
|
||||
*
|
||||
*/
|
||||
ct=c->count;
|
||||
ct = c->count;
|
||||
|
||||
c->skb = c->skb2;
|
||||
c->count = 0;
|
||||
|
|
@ -1594,10 +1594,10 @@ static void z8530_rx_done(struct z8530_channel *c)
|
|||
|
||||
static inline int spans_boundary(struct sk_buff *skb)
|
||||
{
|
||||
unsigned long a=(unsigned long)skb->data;
|
||||
unsigned long a = (unsigned long)skb->data;
|
||||
|
||||
a^=(a+skb->len);
|
||||
if(a&0x00010000) /* If the 64K bit is different.. */
|
||||
a ^= (a + skb->len);
|
||||
if (a & 0x00010000) /* If the 64K bit is different.. */
|
||||
return 1;
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -1620,7 +1620,7 @@ netdev_tx_t z8530_queue_xmit(struct z8530_channel *c, struct sk_buff *skb)
|
|||
unsigned long flags;
|
||||
|
||||
netif_stop_queue(c->netdevice);
|
||||
if(c->tx_next_skb)
|
||||
if (c->tx_next_skb)
|
||||
return NETDEV_TX_BUSY;
|
||||
|
||||
/* PC SPECIFIC - DMA limits */
|
||||
|
|
@ -1628,7 +1628,9 @@ netdev_tx_t z8530_queue_xmit(struct z8530_channel *c, struct sk_buff *skb)
|
|||
* limit, then copy to the flip buffer
|
||||
*/
|
||||
|
||||
if(c->dma_tx && ((unsigned long)(virt_to_bus(skb->data+skb->len))>=16*1024*1024 || spans_boundary(skb)))
|
||||
if (c->dma_tx &&
|
||||
((unsigned long)(virt_to_bus(skb->data + skb->len)) >=
|
||||
16 * 1024 * 1024 || spans_boundary(skb)))
|
||||
{
|
||||
/* Send the flip buffer, and flip the flippy bit.
|
||||
* We don't care which is used when just so long as
|
||||
|
|
@ -1636,14 +1638,14 @@ netdev_tx_t z8530_queue_xmit(struct z8530_channel *c, struct sk_buff *skb)
|
|||
* only one buffer can be going out at a time the other
|
||||
* has to be safe.
|
||||
*/
|
||||
c->tx_next_ptr=c->tx_dma_buf[c->tx_dma_used];
|
||||
c->tx_dma_used^=1; /* Flip temp buffer */
|
||||
c->tx_next_ptr = c->tx_dma_buf[c->tx_dma_used];
|
||||
c->tx_dma_used ^= 1; /* Flip temp buffer */
|
||||
skb_copy_from_linear_data(skb, c->tx_next_ptr, skb->len);
|
||||
} else {
|
||||
c->tx_next_ptr = skb->data;
|
||||
}
|
||||
RT_LOCK;
|
||||
c->tx_next_skb=skb;
|
||||
c->tx_next_skb = skb;
|
||||
RT_UNLOCK;
|
||||
|
||||
spin_lock_irqsave(c->lock, flags);
|
||||
|
|
|
|||
Loading…
Reference in New Issue