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drm/amd/powerplay: use smu7 hwmgr to manager fiji 

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Rex Zhu 2016-08-16 20:00:49 +08:00 committed by Alex Deucher
parent 18edef19ea
commit b859c20703
2 changed files with 27 additions and 4 deletions
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3
drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
View File

@ -7,10 +7,9 @@ HARDWARE_MGR = hwmgr.o processpptables.o functiontables.o \
cz_clockpowergating.o tonga_powertune.o\ cz_clockpowergating.o tonga_powertune.o\
process_pptables_v1_0.o ppatomctrl.o \ process_pptables_v1_0.o ppatomctrl.o \
tonga_hwmgr.o pppcielanes.o tonga_thermal.o\ tonga_hwmgr.o pppcielanes.o tonga_thermal.o\
fiji_powertune.o fiji_hwmgr.o tonga_clockpowergating.o \
fiji_clockpowergating.o fiji_thermal.o \
smu7_hwmgr.o smu7_powertune.o smu7_thermal.o \ smu7_hwmgr.o smu7_powertune.o smu7_thermal.o \
smu7_clockpowergating.o iceland_hwmgr.o \ smu7_clockpowergating.o iceland_hwmgr.o \
tonga_clockpowergating.o \
iceland_clockpowergating.o iceland_thermal.o \ iceland_clockpowergating.o iceland_thermal.o \
iceland_powertune.o iceland_powertune.o

28
drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
View File

@ -37,12 +37,12 @@
extern int cz_hwmgr_init(struct pp_hwmgr *hwmgr); extern int cz_hwmgr_init(struct pp_hwmgr *hwmgr);
extern int tonga_hwmgr_init(struct pp_hwmgr *hwmgr); extern int tonga_hwmgr_init(struct pp_hwmgr *hwmgr);
extern int fiji_hwmgr_init(struct pp_hwmgr *hwmgr);
extern int iceland_hwmgr_init(struct pp_hwmgr *hwmgr); extern int iceland_hwmgr_init(struct pp_hwmgr *hwmgr);
static int polaris_set_asic_special_caps(struct pp_hwmgr *hwmgr); static int polaris_set_asic_special_caps(struct pp_hwmgr *hwmgr);
static void hwmgr_init_default_caps(struct pp_hwmgr *hwmgr); static void hwmgr_init_default_caps(struct pp_hwmgr *hwmgr);
static int hwmgr_set_user_specify_caps(struct pp_hwmgr *hwmgr); static int hwmgr_set_user_specify_caps(struct pp_hwmgr *hwmgr);
static int fiji_set_asic_special_caps(struct pp_hwmgr *hwmgr);
uint8_t convert_to_vid(uint16_t vddc) uint8_t convert_to_vid(uint16_t vddc)
{ {
@ -84,8 +84,13 @@ int hwmgr_init(struct amd_pp_init *pp_init, struct pp_instance *handle)
case CHIP_TONGA: case CHIP_TONGA:
tonga_hwmgr_init(hwmgr); tonga_hwmgr_init(hwmgr);
break; break;
case CHIP_FIJI: case CHIP_FIJI:
fiji_hwmgr_init(hwmgr); smu7_hwmgr_init(hwmgr);
fiji_set_asic_special_caps(hwmgr);
hwmgr->feature_mask &= ~(PP_SMC_VOLTAGE_CONTROL_MASK |
PP_VBI_TIME_SUPPORT_MASK |
PP_ENABLE_GFX_CG_THRU_SMU);
break; break;
case CHIP_POLARIS11: case CHIP_POLARIS11:
case CHIP_POLARIS10: case CHIP_POLARIS10:
@ -744,3 +749,22 @@ int polaris_set_asic_special_caps(struct pp_hwmgr *hwmgr)
return 0; return 0;
} }
int fiji_set_asic_special_caps(struct pp_hwmgr *hwmgr)
{
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_SQRamping);
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_DBRamping);
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_TDRamping);
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_TCPRamping);
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_TablelessHardwareInterface);
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_CAC);
return 0;
}