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clk: mediatek: mt8516: Convert to platform driver and simple probe 

Convert the MT8516 clock drivers to be platform drivers and use the
common probe mechanism.

Thanks to the conversion, more error handling was added to the clocks
registration.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20230306140543.1813621-30-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
AngeloGioacchino Del Regno 2023-03-06 15:05:18 +01:00 committed by Stephen Boyd
parent f419069ad8
commit b8390192f2
2 changed files with 57 additions and 66 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

35
drivers/clk/mediatek/clk-mt8516-aud.c
View File

@ -3,6 +3,7 @@
* Copyright (c) 2019 MediaTek Inc.
* Author: James Liao <jamesjj.liao@mediatek.com>
* Fabien Parent <fparent@baylibre.com>
* Copyright (c) 2023 Collabora Ltd.
*/
#include <linux/clk-provider.h>
@ -25,7 +26,7 @@ static const struct mtk_gate_regs aud_cg_regs = {
#define GATE_AUD(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &aud_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
static const struct mtk_gate aud_clks[] __initconst = {
static const struct mtk_gate aud_clks[] = {
GATE_AUD(CLK_AUD_AFE, "aud_afe", "clk26m_ck", 2),
GATE_AUD(CLK_AUD_I2S, "aud_i2s", "i2s_infra_bck", 6),
GATE_AUD(CLK_AUD_22M, "aud_22m", "rg_aud_engen1", 8),
@ -41,19 +42,25 @@ static const struct mtk_gate aud_clks[] __initconst = {
GATE_AUD(CLK_AUD_TML, "aud_tml", "aud_afe", 27),
};
static void __init mtk_audsys_init(struct device_node *node)
{
struct clk_hw_onecell_data *clk_data;
int r;
static const struct mtk_clk_desc aud_desc = {
.clks = aud_clks,
.num_clks = ARRAY_SIZE(aud_clks),
};
clk_data = mtk_alloc_clk_data(CLK_AUD_NR_CLK);
static const struct of_device_id of_match_clk_mt8516_aud[] = {
{ .compatible = "mediatek,mt8516-audsys", .data = &aud_desc },
{ /* sentinel */ }
};
mtk_clk_register_gates(NULL, node, aud_clks, ARRAY_SIZE(aud_clks), clk_data);
static struct platform_driver clk_mt8516_aud_drv = {
.probe = mtk_clk_simple_probe,
.remove = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8516-aud",
.of_match_table = of_match_clk_mt8516_aud,
},
};
builtin_platform_driver(clk_mt8516_aud_drv);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
pr_err("%s(): could not register clock provider: %d\n",
__func__, r);
}
CLK_OF_DECLARE(mtk_audsys, "mediatek,mt8516-audsys", mtk_audsys_init);
MODULE_DESCRIPTION("MediaTek MT8516 audiosys clocks driver");
MODULE_LICENSE("GPL");

88
drivers/clk/mediatek/clk-mt8516.c
View File

@ -3,6 +3,7 @@
* Copyright (c) 2019 MediaTek Inc.
* Author: James Liao <jamesjj.liao@mediatek.com>
* Fabien Parent <fparent@baylibre.com>
* Copyright (c) 2023 Collabora Ltd.
*/
#include <linux/delay.h>
@ -10,6 +11,7 @@
#include <linux/of_address.h>
#include <linux/slab.h>
#include <linux/mfd/syscon.h>
#include <linux/platform_device.h>
#include "clk-gate.h"
#include "clk-mtk.h"
@ -638,59 +640,41 @@ static const struct mtk_gate top_clks[] __initconst = {
GATE_TOP5(CLK_TOP_APLL12_DIV6, "apll12_div6", "apll12_ck_div6", 8),
};
static void __init mtk_topckgen_init(struct device_node *node)
{
struct clk_hw_onecell_data *clk_data;
int r;
void __iomem *base;
static const struct mtk_clk_desc topck_desc = {
.clks = top_clks,
.num_clks = ARRAY_SIZE(top_clks),
.fixed_clks = fixed_clks,
.num_fixed_clks = ARRAY_SIZE(fixed_clks),
.factor_clks = top_divs,
.num_factor_clks = ARRAY_SIZE(top_divs),
.composite_clks = top_muxes,
.num_composite_clks = ARRAY_SIZE(top_muxes),
.divider_clks = top_adj_divs,
.num_divider_clks = ARRAY_SIZE(top_adj_divs),
.clk_lock = &mt8516_clk_lock,
};
base = of_iomap(node, 0);
if (!base) {
pr_err("%s(): ioremap failed\n", __func__);
return;
}
static const struct mtk_clk_desc infra_desc = {
.composite_clks = ifr_muxes,
.num_composite_clks = ARRAY_SIZE(ifr_muxes),
.clk_lock = &mt8516_clk_lock,
};
clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
static const struct of_device_id of_match_clk_mt8516[] = {
{ .compatible = "mediatek,mt8516-topckgen", .data = &topck_desc },
{ .compatible = "mediatek,mt8516-infracfg", .data = &infra_desc },
{ /* sentinel */ }
};
mtk_clk_register_fixed_clks(fixed_clks, ARRAY_SIZE(fixed_clks),
clk_data);
mtk_clk_register_gates(NULL, node, top_clks, ARRAY_SIZE(top_clks), clk_data);
static struct platform_driver clk_mt8516_drv = {
.probe = mtk_clk_simple_probe,
.remove = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8516",
.of_match_table = of_match_clk_mt8516,
},
};
module_platform_driver(clk_mt8516_drv);
mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
mtk_clk_register_composites(NULL, top_muxes,
ARRAY_SIZE(top_muxes), base,
&mt8516_clk_lock, clk_data);
mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs),
base, &mt8516_clk_lock, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
pr_err("%s(): could not register clock provider: %d\n",
__func__, r);
}
CLK_OF_DECLARE(mtk_topckgen, "mediatek,mt8516-topckgen", mtk_topckgen_init);
static void __init mtk_infracfg_init(struct device_node *node)
{
struct clk_hw_onecell_data *clk_data;
int r;
void __iomem *base;
base = of_iomap(node, 0);
if (!base) {
pr_err("%s(): ioremap failed\n", __func__);
return;
}
clk_data = mtk_alloc_clk_data(CLK_IFR_NR_CLK);
mtk_clk_register_composites(NULL, ifr_muxes,
ARRAY_SIZE(ifr_muxes), base,
&mt8516_clk_lock, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
pr_err("%s(): could not register clock provider: %d\n",
__func__, r);
}
CLK_OF_DECLARE(mtk_infracfg, "mediatek,mt8516-infracfg", mtk_infracfg_init);
MODULE_DESCRIPTION("MediaTek MT8516 clocks driver");
MODULE_LICENSE("GPL");