ASoC: nau8825: Add registers patch for NAU8825C
The patch is to update default regmap and register a set of registers for NAU8825C. Signed-off-by: David Lin <CTLIN0@nuvoton.com> Link: https://lore.kernel.org/r/20230602040924.188913-2-CTLIN0@nuvoton.com Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -178,6 +178,8 @@ static const struct reg_default nau8825_reg_defaults[] = {
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{ NAU8825_REG_CLASSG_CTRL, 0x0 },
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{ NAU8825_REG_OPT_EFUSE_CTRL, 0x0 },
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{ NAU8825_REG_MISC_CTRL, 0x0 },
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{ NAU8825_REG_FLL2_LOWER, 0x0 },
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{ NAU8825_REG_FLL2_UPPER, 0x0 },
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{ NAU8825_REG_BIAS_ADJ, 0x0 },
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{ NAU8825_REG_TRIM_SETTINGS, 0x0 },
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{ NAU8825_REG_ANALOG_CONTROL_1, 0x0 },
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@ -200,6 +202,23 @@ static struct reg_default nau8825_xtalk_baktab[] = {
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{ NAU8825_REG_DACR_CTRL, 0x02cf },
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};
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/* The regmap patch for Rev C */
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static const struct reg_sequence nau8825_regmap_patch[] = {
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{ NAU8825_REG_FLL2, 0x0000 },
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{ NAU8825_REG_FLL4, 0x8010 },
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{ NAU8825_REG_FLL_VCO_RSV, 0x0bc0 },
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{ NAU8825_REG_INTERRUPT_MASK, 0x0800 },
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{ NAU8825_REG_DACL_CTRL, 0x00cf },
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{ NAU8825_REG_DACR_CTRL, 0x02cf },
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{ NAU8825_REG_OPT_EFUSE_CTRL, 0x0400 },
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{ NAU8825_REG_FLL2_LOWER, 0x26e9 },
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{ NAU8825_REG_FLL2_UPPER, 0x0031 },
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{ NAU8825_REG_ANALOG_CONTROL_2, 0x0020 },
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{ NAU8825_REG_ANALOG_ADC_2, 0x0220 },
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{ NAU8825_REG_MIC_BIAS, 0x0046 },
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};
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static const unsigned short logtable[256] = {
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0x0000, 0x0171, 0x02e0, 0x044e, 0x05ba, 0x0725, 0x088e, 0x09f7,
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0x0b5d, 0x0cc3, 0x0e27, 0x0f8a, 0x10eb, 0x124b, 0x13aa, 0x1508,
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@ -855,7 +874,7 @@ static bool nau8825_readable_reg(struct device *dev, unsigned int reg)
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case NAU8825_REG_IMM_MODE_CTRL ... NAU8825_REG_IMM_RMS_R:
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case NAU8825_REG_CLASSG_CTRL ... NAU8825_REG_OPT_EFUSE_CTRL:
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case NAU8825_REG_MISC_CTRL:
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case NAU8825_REG_I2C_DEVICE_ID ... NAU8825_REG_SARDOUT_RAM_STATUS:
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case NAU8825_REG_I2C_DEVICE_ID ... NAU8825_REG_FLL2_UPPER:
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case NAU8825_REG_BIAS_ADJ:
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case NAU8825_REG_TRIM_SETTINGS ... NAU8825_REG_ANALOG_CONTROL_2:
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case NAU8825_REG_ANALOG_ADC_1 ... NAU8825_REG_MIC_BIAS:
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@ -881,6 +900,7 @@ static bool nau8825_writeable_reg(struct device *dev, unsigned int reg)
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case NAU8825_REG_IMM_MODE_CTRL:
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case NAU8825_REG_CLASSG_CTRL ... NAU8825_REG_OPT_EFUSE_CTRL:
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case NAU8825_REG_MISC_CTRL:
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case NAU8825_REG_FLL2_LOWER ... NAU8825_REG_FLL2_UPPER:
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case NAU8825_REG_BIAS_ADJ:
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case NAU8825_REG_TRIM_SETTINGS ... NAU8825_REG_ANALOG_CONTROL_2:
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case NAU8825_REG_ANALOG_ADC_1 ... NAU8825_REG_MIC_BIAS:
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@ -2930,8 +2950,19 @@ static int nau8825_i2c_probe(struct i2c_client *i2c)
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ret);
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return ret;
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}
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if ((value & NAU8825_SOFTWARE_ID_MASK) !=
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NAU8825_SOFTWARE_ID_NAU8825) {
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nau8825->sw_id = value & NAU8825_SOFTWARE_ID_MASK;
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switch (nau8825->sw_id) {
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case NAU8825_SOFTWARE_ID_NAU8825:
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break;
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case NAU8825_SOFTWARE_ID_NAU8825C:
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ret = regmap_register_patch(nau8825->regmap, nau8825_regmap_patch,
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ARRAY_SIZE(nau8825_regmap_patch));
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if (ret) {
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dev_err(dev, "Failed to register Rev C patch: %d\n", ret);
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return ret;
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}
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break;
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default:
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dev_err(dev, "Not a NAU8825 chip\n");
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return -ENODEV;
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}
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@ -75,6 +75,8 @@
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#define NAU8825_REG_MISC_CTRL 0x55
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#define NAU8825_REG_I2C_DEVICE_ID 0x58
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#define NAU8825_REG_SARDOUT_RAM_STATUS 0x59
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#define NAU8825_REG_FLL2_LOWER 0x5a
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#define NAU8825_REG_FLL2_UPPER 0x5b
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#define NAU8825_REG_BIAS_ADJ 0x66
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#define NAU8825_REG_TRIM_SETTINGS 0x68
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#define NAU8825_REG_ANALOG_CONTROL_1 0x69
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@ -386,6 +388,7 @@
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#define NAU8825_GPIO2JD1 (1 << 7)
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#define NAU8825_SOFTWARE_ID_MASK 0x3
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#define NAU8825_SOFTWARE_ID_NAU8825 0x0
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#define NAU8825_SOFTWARE_ID_NAU8825C 0x1
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/* BIAS_ADJ (0x66) */
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#define NAU8825_BIAS_HPR_IMP (1 << 15)
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@ -497,6 +500,7 @@ struct nau8825 {
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struct clk *mclk;
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struct work_struct xtalk_work;
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struct semaphore xtalk_sem;
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int sw_id;
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int irq;
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int mclk_freq; /* 0 - mclk is disabled */
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int button_pressed;
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