drm/bridge: ti-sn65dsi86: Implement AUX channel
This was hand-rolled in the first version, and will surely be useful as we expand the driver to support more varied use cases. Changes in v2: - Change subject prefix s/panel/bridge/ - Downgrade warning in poll function to error message - Fix DP_EDP_CONFIGURATION_SET write value (Sandeep) - Mask upper 8 bits of msg->address (Sandeep) - Check aux cmd status for errors after completing the send (Sandeep) - Remove length check since it's covered in the aux status - Flip the READ check in transfer to WRITE check + early exit Changes in v3: - Added to the set - Wrapped (x) in WDATA/RDATA #defines - Replace readx_poll* with regmap_read_poll* Cc: Sandeep Panda <spanda@codeaurora.org> Reviewed-by: Sandeep Panda <spanda@codeaurora.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: https://patchwork.freedesktop.org/patch/msgid/20180813213058.184821-4-sean@poorly.run
This commit is contained in:
Sean Paul
parent
6c76c0eb03
commit
b814ec6d45
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@ -7,12 +7,14 @@
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#include <drm/drm_atomic.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_crtc_helper.h>
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#include <drm/drm_dp_helper.h>
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#include <drm/drm_mipi_dsi.h>
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#include <drm/drm_of.h>
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#include <drm/drm_panel.h>
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#include <linux/clk.h>
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#include <linux/gpio/consumer.h>
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#include <linux/i2c.h>
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#include <linux/iopoll.h>
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#include <linux/of_graph.h>
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#include <linux/pm_runtime.h>
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#include <linux/regmap.h>
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@ -46,7 +48,7 @@
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#define SN_DATA_FORMAT_REG 0x5B
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#define SN_HPD_DISABLE_REG 0x5C
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#define HPD_DISABLE BIT(0)
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#define SN_AUX_WDATA0_REG 0x64
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#define SN_AUX_WDATA_REG(x) (0x64 + (x))
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#define SN_AUX_ADDR_19_16_REG 0x74
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#define SN_AUX_ADDR_15_8_REG 0x75
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#define SN_AUX_ADDR_7_0_REG 0x76
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@ -54,6 +56,7 @@
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#define SN_AUX_CMD_REG 0x78
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#define AUX_CMD_SEND BIT(1)
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#define AUX_CMD_REQ(x) ((x) << 4)
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#define SN_AUX_RDATA_REG(x) (0x79 + (x))
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#define SN_SSC_CONFIG_REG 0x93
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#define DP_NUM_LANES_MASK GENMASK(5, 4)
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#define DP_NUM_LANES(x) ((x) << 4)
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@ -63,6 +66,10 @@
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#define SN_ML_TX_MODE_REG 0x96
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#define ML_TX_MAIN_LINK_OFF 0
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#define ML_TX_NORMAL_MODE BIT(0)
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#define SN_AUX_CMD_STATUS_REG 0xF4
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#define AUX_IRQ_STATUS_AUX_RPLY_TOUT BIT(3)
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#define AUX_IRQ_STATUS_AUX_SHORT BIT(5)
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#define AUX_IRQ_STATUS_NAT_I2C_FAIL BIT(6)
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#define MIN_DSI_CLK_FREQ_MHZ 40
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@ -70,11 +77,15 @@
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#define DP_CLK_FUDGE_NUM 10
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#define DP_CLK_FUDGE_DEN 8
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/* Matches DP_AUX_MAX_PAYLOAD_BYTES (for now) */
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#define SN_AUX_MAX_PAYLOAD_BYTES 16
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#define SN_REGULATOR_SUPPLY_NUM 4
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struct ti_sn_bridge {
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struct device *dev;
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struct regmap *regmap;
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struct drm_dp_aux aux;
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struct drm_bridge bridge;
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struct drm_connector connector;
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struct device_node *host_node;
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@ -471,13 +482,8 @@ static void ti_sn_bridge_enable(struct drm_bridge *bridge)
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* authentication method. We need to enable this method in the eDP panel
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* at DisplayPort address 0x0010A prior to link training.
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*/
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regmap_write(pdata->regmap, SN_AUX_WDATA0_REG, 0x01);
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regmap_write(pdata->regmap, SN_AUX_ADDR_19_16_REG, 0x00);
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regmap_write(pdata->regmap, SN_AUX_ADDR_15_8_REG, 0x01);
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regmap_write(pdata->regmap, SN_AUX_ADDR_7_0_REG, 0x0A);
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regmap_write(pdata->regmap, SN_AUX_LENGTH_REG, 0x01);
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regmap_write(pdata->regmap, SN_AUX_CMD_REG, 0x81);
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usleep_range(10000, 10500); /* 10ms delay recommended by spec */
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drm_dp_dpcd_writeb(&pdata->aux, DP_EDP_CONFIGURATION_SET,
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DP_ALTERNATE_SCRAMBLER_RESET_ENABLE);
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/* Semi auto link training mode */
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regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0x0A);
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@ -525,6 +531,82 @@ static const struct drm_bridge_funcs ti_sn_bridge_funcs = {
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.post_disable = ti_sn_bridge_post_disable,
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};
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static struct ti_sn_bridge *aux_to_ti_sn_bridge(struct drm_dp_aux *aux)
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{
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return container_of(aux, struct ti_sn_bridge, aux);
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}
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static ssize_t ti_sn_aux_transfer(struct drm_dp_aux *aux,
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struct drm_dp_aux_msg *msg)
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{
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struct ti_sn_bridge *pdata = aux_to_ti_sn_bridge(aux);
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u32 request = msg->request & ~DP_AUX_I2C_MOT;
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u32 request_val = AUX_CMD_REQ(msg->request);
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u8 *buf = (u8 *)msg->buffer;
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unsigned int val;
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int ret, i;
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if (msg->size > SN_AUX_MAX_PAYLOAD_BYTES)
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return -EINVAL;
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switch (request) {
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case DP_AUX_NATIVE_WRITE:
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case DP_AUX_I2C_WRITE:
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case DP_AUX_NATIVE_READ:
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case DP_AUX_I2C_READ:
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regmap_write(pdata->regmap, SN_AUX_CMD_REG, request_val);
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break;
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default:
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return -EINVAL;
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}
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regmap_write(pdata->regmap, SN_AUX_ADDR_19_16_REG,
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(msg->address >> 16) & 0xF);
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regmap_write(pdata->regmap, SN_AUX_ADDR_15_8_REG,
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(msg->address >> 8) & 0xFF);
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regmap_write(pdata->regmap, SN_AUX_ADDR_7_0_REG, msg->address & 0xFF);
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regmap_write(pdata->regmap, SN_AUX_LENGTH_REG, msg->size);
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if (request == DP_AUX_NATIVE_WRITE || request == DP_AUX_I2C_WRITE) {
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for (i = 0; i < msg->size; i++)
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regmap_write(pdata->regmap, SN_AUX_WDATA_REG(i),
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buf[i]);
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}
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regmap_write(pdata->regmap, SN_AUX_CMD_REG, request_val | AUX_CMD_SEND);
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ret = regmap_read_poll_timeout(pdata->regmap, SN_AUX_CMD_REG, val,
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!(val & AUX_CMD_SEND), 200,
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50 * 1000);
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if (ret)
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return ret;
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ret = regmap_read(pdata->regmap, SN_AUX_CMD_STATUS_REG, &val);
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if (ret)
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return ret;
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else if ((val & AUX_IRQ_STATUS_NAT_I2C_FAIL)
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|| (val & AUX_IRQ_STATUS_AUX_RPLY_TOUT)
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|| (val & AUX_IRQ_STATUS_AUX_SHORT))
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return -ENXIO;
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if (request == DP_AUX_NATIVE_WRITE || request == DP_AUX_I2C_WRITE)
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return msg->size;
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for (i = 0; i < msg->size; i++) {
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unsigned int val;
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ret = regmap_read(pdata->regmap, SN_AUX_RDATA_REG(i),
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&val);
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if (ret)
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return ret;
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WARN_ON(val & ~0xFF);
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buf[i] = (u8)(val & 0xFF);
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}
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return msg->size;
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}
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static int ti_sn_bridge_parse_dsi_host(struct ti_sn_bridge *pdata)
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{
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struct device_node *np = pdata->dev->of_node;
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@ -604,6 +686,11 @@ static int ti_sn_bridge_probe(struct i2c_client *client,
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i2c_set_clientdata(client, pdata);
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pdata->aux.name = "ti-sn65dsi86-aux";
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pdata->aux.dev = pdata->dev;
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pdata->aux.transfer = ti_sn_aux_transfer;
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drm_dp_aux_register(&pdata->aux);
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pdata->bridge.funcs = &ti_sn_bridge_funcs;
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pdata->bridge.of_node = client->dev.of_node;
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