spi: Fixes for v6.4
A few more driver specific fixes, the DesignWare fix is for an issue introduced by conversion to the chip select accessor functions and is pretty important but the other two are less severe. -----BEGIN PGP SIGNATURE----- iQEzBAABCgAdFiEEreZoqmdXGLWf4p/qJNaLcl1Uh9AFAmSK+EcACgkQJNaLcl1U h9AGrQf+OypgdT5kMex1gYUB7GaNPW3HcK49b0v2TudjmkRNVQCPZVVzbWQI7VfZ EuB3+miDKbwxgpmFQHae+iQZL7uavqQWBQU2D8Gk5H15FDmdRw9aHCFZAsZrSn1x QBRXo3b+tD2q1Feh1oCX0epbkDZB8MSlbUBTTtT/Q/LoEKEk/JDogsjsa7LVTKtz GsUEWsQouNZ1ZrKfXVQ9RM5z9y6nhk3JNzs9bH+kvN/fRwj41mbHin96bb1+xL9U bqta9JyDPAF1NWXagerky/BTuT/84ESbxiOcXujqr+wtaUgjgkKaCSj2uE5hws+o 9sld5NL3X3uqId+QQ+pivUYQ8Et2sQ== =/wJ/ -----END PGP SIGNATURE----- Merge tag 'spi-fix-v6.4-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi Pull spi fixes from Mark Brown: "A few more driver specific fixes. The DesignWare fix is for an issue introduced by conversion to the chip select accessor functions and is pretty important but the other two are less severe" * tag 'spi-fix-v6.4-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: spi: dw: Replace incorrect spi_get_chipselect with set spi: fsl-dspi: avoid SCK glitches with continuous transfers spi: cadence-quadspi: Add missing check for dma_set_mask
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commit
b7feaa490b
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@ -1756,8 +1756,11 @@ static int cqspi_probe(struct platform_device *pdev)
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cqspi->slow_sram = true;
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if (of_device_is_compatible(pdev->dev.of_node,
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"xlnx,versal-ospi-1.0"))
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dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
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"xlnx,versal-ospi-1.0")) {
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ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
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if (ret)
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goto probe_reset_failed;
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}
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}
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ret = devm_request_irq(dev, irq, cqspi_irq_handler, 0,
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@ -274,7 +274,7 @@ static void dw_spi_elba_set_cs(struct spi_device *spi, bool enable)
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*/
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spi_set_chipselect(spi, 0, 0);
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dw_spi_set_cs(spi, enable);
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spi_get_chipselect(spi, cs);
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spi_set_chipselect(spi, 0, cs);
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}
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static int dw_spi_elba_init(struct platform_device *pdev,
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@ -1002,7 +1002,9 @@ static int dspi_transfer_one_message(struct spi_controller *ctlr,
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static int dspi_setup(struct spi_device *spi)
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{
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struct fsl_dspi *dspi = spi_controller_get_devdata(spi->controller);
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u32 period_ns = DIV_ROUND_UP(NSEC_PER_SEC, spi->max_speed_hz);
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unsigned char br = 0, pbr = 0, pcssck = 0, cssck = 0;
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u32 quarter_period_ns = DIV_ROUND_UP(period_ns, 4);
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u32 cs_sck_delay = 0, sck_cs_delay = 0;
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struct fsl_dspi_platform_data *pdata;
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unsigned char pasc = 0, asc = 0;
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@ -1031,6 +1033,19 @@ static int dspi_setup(struct spi_device *spi)
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sck_cs_delay = pdata->sck_cs_delay;
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}
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/* Since tCSC and tASC apply to continuous transfers too, avoid SCK
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* glitches of half a cycle by never allowing tCSC + tASC to go below
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* half a SCK period.
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*/
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if (cs_sck_delay < quarter_period_ns)
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cs_sck_delay = quarter_period_ns;
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if (sck_cs_delay < quarter_period_ns)
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sck_cs_delay = quarter_period_ns;
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dev_dbg(&spi->dev,
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"DSPI controller timing params: CS-to-SCK delay %u ns, SCK-to-CS delay %u ns\n",
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cs_sck_delay, sck_cs_delay);
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clkrate = clk_get_rate(dspi->clk);
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hz_to_spi_baud(&pbr, &br, spi->max_speed_hz, clkrate);
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