gpu: ipu-v3: Fix CSI selection for VDIC
The description of the CSI_SEL bit in the i.MX6 reference manual is incorrect. It states "This bit defines which CSI is the input to the IC. This bit is effective only if IC_INPUT is bit cleared". From experiment it was found this is in fact not correct. The CSI_SEL bit selects which CSI is input to _both_ the VDIC _and_ the IC. If the IC_INPUT bit is set so that the IC is receiving from the VDIC, the IC ignores the CSI_SEL bit, but CSI_SEL still selects which CSI the VDIC receives from in that case. Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
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@ -725,15 +725,16 @@ void ipu_set_ic_src_mux(struct ipu_soc *ipu, int csi_id, bool vdi)
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spin_lock_irqsave(&ipu->lock, flags);
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val = ipu_cm_read(ipu, IPU_CONF);
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if (vdi) {
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if (vdi)
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val |= IPU_CONF_IC_INPUT;
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} else {
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else
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val &= ~IPU_CONF_IC_INPUT;
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if (csi_id == 1)
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val |= IPU_CONF_CSI_SEL;
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else
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val &= ~IPU_CONF_CSI_SEL;
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}
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if (csi_id == 1)
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val |= IPU_CONF_CSI_SEL;
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else
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val &= ~IPU_CONF_CSI_SEL;
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ipu_cm_write(ipu, val, IPU_CONF);
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spin_unlock_irqrestore(&ipu->lock, flags);
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