drm/amd/display: move dsc clock from plane_resource to stream_resource
code restructure. Signed-off-by: Tony Cheng <tony.cheng@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -2204,7 +2204,7 @@ bool dcn20_validate_bandwidth(struct dc *dc,
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context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz =
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pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
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#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
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context->res_ctx.pipe_ctx[i].plane_res.bw.dscclk_khz =
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context->res_ctx.pipe_ctx[i].stream_res.dscclk_khz =
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context->bw_ctx.dml.vba.DSCCLK_calculated[pipe_idx] * 1000;
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#endif
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context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest;
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@ -222,15 +222,14 @@ struct resource_pool {
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struct dcn_fe_bandwidth {
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int dppclk_khz;
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#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
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int dscclk_khz;
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#endif
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};
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struct stream_resource {
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struct output_pixel_processor *opp;
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#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
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struct display_stream_compressor *dsc;
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int dscclk_khz;
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#endif
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struct timing_generator *tg;
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struct stream_encoder *stream_enc;
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