T104xD4RDB: Add qe node to t104xd4rdb
add qe node to t104xd4rdb.dtsi and t1040si-post.dtsi. Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Signed-off-by: Scott Wood <oss@buserror.net>
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@ -673,3 +673,48 @@
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};
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};
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};
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&qe {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "qe";
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compatible = "fsl,qe";
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fsl,qe-num-riscs = <1>;
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fsl,qe-num-snums = <28>;
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qeic: interrupt-controller@80 {
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interrupt-controller;
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compatible = "fsl,qe-ic";
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#address-cells = <0>;
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#interrupt-cells = <1>;
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reg = <0x80 0x80>;
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interrupts = <95 2 0 0 94 2 0 0>; //high:79 low:78
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};
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ucc@2000 {
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cell-index = <1>;
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reg = <0x2000 0x200>;
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interrupts = <32>;
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interrupt-parent = <&qeic>;
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};
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ucc@2200 {
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cell-index = <3>;
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reg = <0x2200 0x200>;
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interrupts = <34>;
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interrupt-parent = <&qeic>;
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};
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muram@10000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,qe-muram", "fsl,cpm-muram";
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ranges = <0x0 0x10000 0x6000>;
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data-only@0 {
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compatible = "fsl,qe-muram-data",
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"fsl,cpm-muram-data";
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reg = <0x0 0x6000>;
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};
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};
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};
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@ -212,4 +212,42 @@
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0 0x00010000>;
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};
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};
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qe: qe@ffe140000 {
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ranges = <0x0 0xf 0xfe140000 0x40000>;
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reg = <0xf 0xfe140000 0 0x480>;
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brg-frequency = <0>;
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bus-frequency = <0>;
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si1: si@700 {
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compatible = "fsl,t1040-qe-si";
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reg = <0x700 0x80>;
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};
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siram1: siram@1000 {
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compatible = "fsl,t1040-qe-siram";
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reg = <0x1000 0x800>;
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};
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ucc_hdlc: ucc@2000 {
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compatible = "fsl,ucc-hdlc";
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rx-clock-name = "clk8";
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tx-clock-name = "clk9";
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fsl,rx-sync-clock = "rsync_pin";
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fsl,tx-sync-clock = "tsync_pin";
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fsl,tx-timeslot-mask = <0xfffffffe>;
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fsl,rx-timeslot-mask = <0xfffffffe>;
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fsl,tdm-framer-type = "e1";
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fsl,tdm-id = <0>;
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fsl,siram-entry-id = <0>;
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fsl,tdm-interface;
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};
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ucc_serial: ucc@2200 {
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compatible = "fsl,t1040-ucc-uart";
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port-number = <0>;
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rx-clock-name = "brg2";
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tx-clock-name = "brg2";
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};
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};
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};
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