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- added support for TP-Link HC220 G5 v1 

- added support for Wifi/Bluetooth on CI20
 - reworked Ralink clock and reset handling
 - cleanups and fixes
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Merge tag 'mips_6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux

Pull MIPS updates from Thomas Bogendoerfer:

 - add support for TP-Link HC220 G5 v1

 - add support for Wifi/Bluetooth on CI20

 - rework Ralink clock and reset handling

 - cleanups and fixes

* tag 'mips_6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (58 commits)
  MIPS: Loongson64: DTS: Add RTC support to Loongson-2K1000
  MIPS: Loongson64: DTS: Add RTC support to LS7A PCH
  MIPS: OCTEON: octeon-usb: cleanup divider calculation
  MIPS: OCTEON: octeon-usb: introduce dwc3_octeon_{read,write}q
  MIPS: OCTEON: octeon-usb: move gpio config to separate function
  MIPS: OCTEON: octeon-usb: use bitfields for shim register
  MIPS: OCTEON: octeon-usb: use bitfields for host config register
  MIPS: OCTEON: octeon-usb: use bitfields for control register
  MIPS: OCTEON: octeon-usb: add all register offsets
  mips: ralink: match all supported system controller compatible strings
  MIPS: dec: prom: Address -Warray-bounds warning
  MIPS: DTS: CI20: Raise VDDCORE voltage to 1.125 volts
  clk: ralink: mtmips: Fix uninitialized use of ret in mtmips_register_{fixed,factor}_clocks()
  mips: ralink: introduce commonly used remap node function
  mips: pci-mt7620: use dev_info() to log PCIe device detection result
  mips: pci-mt7620: do not print NFTS register value as error log
  MAINTAINERS: add Mediatek MTMIPS Clock maintainer
  mips: ralink: get cpu rate from new driver code
  mips: ralink: remove reset related code
  mips: ralink: mt7620: remove clock related code
  ...
This commit is contained in:
Linus Torvalds 2023-06-29 15:01:51 -07:00
parent 18f38fedfa e47084e116
commit b775d6c585
56 changed files with 2092 additions and 1136 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
Documentation/admin-guide/kernel-parameters.txt
View File

@ -3716,8 +3716,8 @@
nohibernate [HIBERNATION] Disable hibernation and resume.
nohlt [ARM,ARM64,MICROBLAZE,SH] Forces the kernel to busy wait
in do_idle() and not use the arch_cpu_idle()
nohlt [ARM,ARM64,MICROBLAZE,MIPS,SH] Forces the kernel to
busy wait in do_idle() and not use the arch_cpu_idle()
implementation; requires CONFIG_GENERIC_IDLE_POLL_SETUP
to be effective. This is useful on platforms where the
sleep(SH) or wfi(ARM,ARM64) instructions do not work
@ -3852,7 +3852,7 @@
nosmp [SMP] Tells an SMP kernel to act as a UP kernel,
and disable the IO APIC. legacy for "maxcpus=0".
nosmt [KNL,S390] Disable symmetric multithreading (SMT).
nosmt [KNL,MIPS,S390] Disable symmetric multithreading (SMT).
Equivalent to smt=1.
[KNL,X86] Disable symmetric multithreading (SMT).
@ -5770,7 +5770,7 @@
1: Fast pin select (default)
2: ATC IRMode
smt= [KNL,S390] Set the maximum number of threads (logical
smt= [KNL,MIPS,S390] Set the maximum number of threads (logical
CPUs) to use per physical CPU on systems capable of
symmetric multithreading (SMT). Will be capped to the
actual hardware limit.

64
Documentation/devicetree/bindings/clock/mediatek,mtmips-sysc.yaml Normal file
View File

@ -0,0 +1,64 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/mediatek,mtmips-sysc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MTMIPS SoCs System Controller
maintainers:
- Sergio Paracuellos <sergio.paracuellos@gmail.com>
description: |
MediaTek MIPS and Ralink SoCs provides a system controller to allow
to access to system control registers. These registers include clock
and reset related ones so this node is both clock and reset provider
for the rest of the world.
These SoCs have an XTAL from where the cpu clock is
provided as well as derived clocks for the bus and the peripherals.
properties:
compatible:
items:
- enum:
- ralink,mt7620-sysc
- ralink,mt7628-sysc
- ralink,mt7688-sysc
- ralink,rt2880-sysc
- ralink,rt3050-sysc
- ralink,rt3052-sysc
- ralink,rt3352-sysc
- ralink,rt3883-sysc
- ralink,rt5350-sysc
- const: syscon
reg:
maxItems: 1
'#clock-cells':
description:
The first cell indicates the clock number.
const: 1
'#reset-cells':
description:
The first cell indicates the reset bit within the register.
const: 1
required:
- compatible
- reg
- '#clock-cells'
- '#reset-cells'
additionalProperties: false
examples:
- |
syscon@0 {
compatible = "ralink,rt5350-sysc", "syscon";
reg = <0x0 0x100>;
#clock-cells = <1>;
#reset-cells = <1>;
};

1
Documentation/devicetree/bindings/mips/ralink.yaml
View File

@ -80,6 +80,7 @@ properties:
- enum:
- gnubee,gb-pc1
- gnubee,gb-pc2
- tplink,hc220-g5-v1
- const: mediatek,mt7621-soc
additionalProperties: true

7
MAINTAINERS
View File

@ -11442,7 +11442,6 @@ F: tools/testing/selftests/kvm/aarch64/
KERNEL VIRTUAL MACHINE FOR MIPS (KVM/mips)
M: Huacai Chen <chenhuacai@kernel.org>
M: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
L: linux-mips@vger.kernel.org
L: kvm@vger.kernel.org
S: Maintained
@ -13331,6 +13330,12 @@ S: Maintained
F: Documentation/devicetree/bindings/i2c/mediatek,mt7621-i2c.yaml
F: drivers/i2c/busses/i2c-mt7621.c
MEDIATEK MTMIPS CLOCK DRIVER
M: Sergio Paracuellos <sergio.paracuellos@gmail.com>
S: Maintained
F: Documentation/devicetree/bindings/clock/mediatek,mtmips-sysc.yaml
F: drivers/clk/ralink/clk-mtmips.c
MEDIATEK NAND CONTROLLER DRIVER
L: linux-mtd@lists.infradead.org
S: Orphan

4
arch/mips/Kconfig
View File

@ -45,6 +45,7 @@ config MIPS
select GENERIC_LIB_UCMPDI2
select GENERIC_SCHED_CLOCK if !CAVIUM_OCTEON_SOC
select GENERIC_SMP_IDLE_THREAD
select GENERIC_IDLE_POLL_SETUP
select GENERIC_TIME_VSYSCALL
select GUP_GET_PXX_LOW_HIGH if CPU_MIPS32 && PHYS_ADDR_T_64BIT
select HAS_IOPORT if !NO_IOPORT_MAP || ISA
@ -80,7 +81,6 @@ config MIPS
select HAVE_LD_DEAD_CODE_DATA_ELIMINATION
select HAVE_MOD_ARCH_SPECIFIC
select HAVE_NMI
select HAVE_PATA_PLATFORM
select HAVE_PERF_EVENTS
select HAVE_PERF_REGS
select HAVE_PERF_USER_STACK_DUMP
@ -155,9 +155,11 @@ config MIPS_GENERIC_KERNEL
select SWAP_IO_SPACE
select SYS_HAS_CPU_MIPS32_R1
select SYS_HAS_CPU_MIPS32_R2
select SYS_HAS_CPU_MIPS32_R5
select SYS_HAS_CPU_MIPS32_R6
select SYS_HAS_CPU_MIPS64_R1
select SYS_HAS_CPU_MIPS64_R2
select SYS_HAS_CPU_MIPS64_R5
select SYS_HAS_CPU_MIPS64_R6
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_64BIT_KERNEL

1
arch/mips/alchemy/Kconfig
View File

@ -14,6 +14,7 @@ config MIPS_DB1XXX
bool "Alchemy DB1XXX / PB1XXX boards"
select GPIOLIB
select HAVE_PCI
select HAVE_PATA_PLATFORM
select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_HAS_EARLY_PRINTK
help

152
arch/mips/boot/dts/ingenic/ci20.dts
View File

@ -67,14 +67,14 @@
};
};
eth0_power: fixedregulator@0 {
eth0_power: fixedregulator-0 {
compatible = "regulator-fixed";
regulator-name = "eth0_power";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpb 25 GPIO_ACTIVE_LOW>;
gpio = <&gpb 25 0>;
enable-active-high;
};
@ -97,25 +97,64 @@
gpios = <&gpe 3 GPIO_ACTIVE_LOW>;
};
wlan0_power: fixedregulator@1 {
bt_power: fixedregulator-1 {
compatible = "regulator-fixed";
regulator-name = "wlan0_power";
regulator-name = "bt_power";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-settling-time-us = <1400>;
gpio = <&gpb 19 GPIO_ACTIVE_LOW>;
vin-supply = <&vcc_50>;
gpio = <&gpb 19 0>;
enable-active-high;
};
otg_power: fixedregulator@2 {
otg_power: fixedregulator-2 {
compatible = "regulator-fixed";
regulator-name = "otg_power";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpf 15 GPIO_ACTIVE_LOW>;
gpio = <&gpf 15 0>;
enable-active-high;
};
wifi_power: fixedregulator-4 {
compatible = "regulator-fixed";
regulator-name = "wifi_power";
/*
* Technically it's 5V, the WiFi chip has its own internal
* regulators; but the MMC/SD subsystem won't accept such a
* value.
*/
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-settling-time-us = <150000>;
vin-supply = <&bt_power>;
};
vcc_33v: fixedregulator-5 {
compatible = "regulator-fixed";
regulator-name = "vcc_33v";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
wifi_pwrseq: pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&gpf 7 GPIO_ACTIVE_LOW>;
clocks = <&rtc_dev>;
clock-names = "ext_clock";
};
};
&ext {
@ -129,10 +168,11 @@
*/
assigned-clocks = <&cgu JZ4780_CLK_OTGPHY>, <&cgu JZ4780_CLK_RTC>,
<&cgu JZ4780_CLK_SSIPLL>, <&cgu JZ4780_CLK_SSI>,
<&cgu JZ4780_CLK_HDMI>;
<&cgu JZ4780_CLK_HDMI>, <&cgu JZ4780_CLK_MSCMUX>;
assigned-clock-parents = <0>, <&cgu JZ4780_CLK_RTCLK>,
<&cgu JZ4780_CLK_MPLL>,
<&cgu JZ4780_CLK_SSIPLL>;
<&cgu JZ4780_CLK_SSIPLL>,
<0>, <&cgu JZ4780_CLK_MPLL>;
assigned-clock-rates = <48000000>, <0>, <54000000>, <0>, <27000000>;
};
@ -160,24 +200,33 @@
pinctrl-0 = <&pins_mmc0>;
cd-gpios = <&gpf 20 GPIO_ACTIVE_LOW>;
vmmc-supply = <&vcc_33v>;
vqmmc-supply = <&vcc_33v>;
};
&mmc1 {
status = "okay";
bus-width = <4>;
max-frequency = <50000000>;
max-frequency = <25000000>;
mmc-pwrseq = <&wifi_pwrseq>;
vmmc-supply = <&wifi_power>;
vqmmc-supply = <&wifi_io>;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&pins_mmc1>;
brcmf: wifi@1 {
/* reg = <4>;*/
compatible = "brcm,bcm4330-fmac";
vcc-supply = <&wlan0_power>;
device-wakeup-gpios = <&gpd 9 GPIO_ACTIVE_HIGH>;
shutdown-gpios = <&gpf 7 GPIO_ACTIVE_LOW>;
#address-cells = <1>;
#size-cells = <0>;
wifi@1 {
compatible = "brcm,bcm4329-fmac";
reg = <1>;
interrupt-parent = <&gpd>;
interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
interrupt-names = "host-wake";
};
};
@ -204,11 +253,20 @@
bluetooth {
compatible = "brcm,bcm4330-bt";
reset-gpios = <&gpf 8 GPIO_ACTIVE_HIGH>;
vcc-supply = <&wlan0_power>;
vbat-supply = <&bt_power>;
vddio-supply = <&wifi_io>;
interrupt-parent = <&gpf>;
interrupts = <6 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "host-wakeup";
clocks = <&rtc_dev>;
clock-names = "lpo";
reset-gpios = <&gpf 8 GPIO_ACTIVE_LOW>;
device-wakeup-gpios = <&gpf 5 GPIO_ACTIVE_HIGH>;
host-wakeup-gpios = <&gpf 6 GPIO_ACTIVE_HIGH>;
shutdown-gpios = <&gpf 4 GPIO_ACTIVE_LOW>;
shutdown-gpios = <&gpf 4 GPIO_ACTIVE_HIGH>;
};
};
@ -237,59 +295,54 @@
act8600: act8600@5a {
compatible = "active-semi,act8600";
reg = <0x5a>;
status = "okay";
regulators {
vddcore: SUDCDC1 {
regulator-name = "DCDC_REG1";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
vddcore: DCDC1 {
regulator-min-microvolt = <1125000>;
regulator-max-microvolt = <1125000>;
vp1-supply = <&vcc_33v>;
regulator-always-on;
};
vddmem: SUDCDC2 {
regulator-name = "DCDC_REG2";
vddmem: DCDC2 {
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
vp2-supply = <&vcc_33v>;
regulator-always-on;
};
vcc_33: SUDCDC3 {
regulator-name = "DCDC_REG3";
vcc_33: DCDC3 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vp3-supply = <&vcc_33v>;
regulator-always-on;
};
vcc_50: SUDCDC4 {
regulator-name = "SUDCDC_REG4";
vcc_50: SUDCDC_REG4 {
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
vcc_25: LDO_REG5 {
regulator-name = "LDO_REG5";
vcc_25: LDO5 {
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
inl-supply = <&vcc_33v>;
regulator-always-on;
};
wifi_io: LDO_REG6 {
regulator-name = "LDO_REG6";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
regulator-always-on;
wifi_io: LDO6 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-settling-time-us = <150000>;
inl-supply = <&vcc_33v>;
};
vcc_28: LDO_REG7 {
regulator-name = "LDO_REG7";
cim_io_28: LDO7 {
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-always-on;
inl-supply = <&vcc_33v>;
};
vcc_15: LDO_REG8 {
regulator-name = "LDO_REG8";
cim_io_15: LDO8 {
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-always-on;
inl-supply = <&vcc_33v>;
};
vrtc_18: LDO_REG9 {
regulator-name = "LDO_REG9";
/* Despite the datasheet stating 3.3V
* for REG9 and the driver expecting that,
* REG9 outputs 1.8V.
@ -303,7 +356,6 @@
regulator-always-on;
};
vcc_11: LDO_REG10 {
regulator-name = "LDO_REG10";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
@ -363,7 +415,7 @@
#address-cells = <1>;
#size-cells = <0>;
ingenic,bch-controller = <&bch>;
ecc-engine = <&bch>;
ingenic,nemc-tAS = <10>;
ingenic,nemc-tAH = <5>;
@ -429,8 +481,8 @@
pinctrl-names = "default";
pinctrl-0 = <&pins_nemc_cs6>;
reg = <6 0 1 /* addr */
6 2 1>; /* data */
reg = <6 0 1>, /* addr */
<6 2 1>; /* data */
ingenic,nemc-tAS = <15>;
ingenic,nemc-tAH = <10>;
@ -442,7 +494,7 @@
vcc-supply = <&eth0_power>;
interrupt-parent = <&gpe>;
interrupts = <19 4>;
interrupts = <19 IRQ_TYPE_EDGE_RISING>;
nvmem-cells = <&eth0_addr>;
nvmem-cell-names = "mac-address";

7
arch/mips/boot/dts/ingenic/jz4725b.dtsi
View File

@ -198,11 +198,8 @@
#sound-dai-cells = <0>;
clocks = <&cgu JZ4725B_CLK_AIC>,
<&cgu JZ4725B_CLK_I2S>,
<&cgu JZ4725B_CLK_EXT>,
<&cgu JZ4725B_CLK_PLL_HALF>;
clock-names = "aic", "i2s", "ext", "pll half";
clocks = <&cgu JZ4725B_CLK_AIC>, <&cgu JZ4725B_CLK_I2S>;
clock-names = "aic", "i2s";
interrupt-parent = <&intc>;
interrupts = <10>;

7
arch/mips/boot/dts/ingenic/jz4740.dtsi
View File

@ -192,11 +192,8 @@
interrupt-parent = <&intc>;
interrupts = <18>;
clocks = <&cgu JZ4740_CLK_AIC>,
<&cgu JZ4740_CLK_I2S>,
<&cgu JZ4740_CLK_EXT>,
<&cgu JZ4740_CLK_PLL_HALF>;
clock-names = "aic", "i2s", "ext", "pll half";
clocks = <&cgu JZ4740_CLK_AIC>, <&cgu JZ4740_CLK_I2S>;
clock-names = "aic", "i2s";
dmas = <&dmac 25 0xffffffff>, <&dmac 24 0xffffffff>;
dma-names = "rx", "tx";

5
arch/mips/boot/dts/ingenic/jz4770.dtsi
View File

@ -238,9 +238,8 @@
#sound-dai-cells = <0>;
clocks = <&cgu JZ4770_CLK_AIC>, <&cgu JZ4770_CLK_I2S>,
<&cgu JZ4770_CLK_EXT>, <&cgu JZ4770_CLK_PLL0>;
clock-names = "aic", "i2s", "ext", "pll half";
clocks = <&cgu JZ4770_CLK_AIC>, <&cgu JZ4770_CLK_I2S>;
clock-names = "aic", "i2s";
interrupt-parent = <&intc>;
interrupts = <34>;

6
arch/mips/boot/dts/ingenic/qi_lb60.dts
View File

@ -27,7 +27,7 @@
stdout-path = &uart0;
};
vcc: regulator@0 {
vcc: regulator-0 {
compatible = "regulator-fixed";
regulator-name = "vcc";
@ -36,7 +36,7 @@
regulator-always-on;
};
mmc_power: regulator@1 {
mmc_power: regulator-1 {
compatible = "regulator-fixed";
regulator-name = "mmc_vcc";
gpio = <&gpd 2 0>;
@ -45,7 +45,7 @@
regulator-max-microvolt = <3300000>;
};
amp_supply: regulator@2 {
amp_supply: regulator-2 {
compatible = "regulator-fixed";
regulator-name = "amp_supply";
gpio = <&gpd 4 0>;

18
arch/mips/boot/dts/ingenic/x1000.dtsi
View File

@ -417,4 +417,22 @@
status = "disabled";
};
aic: audio-controller@10020000 {
compatible = "ingenic,x1000-i2s";
reg = <0x10020000 0x38>;
#sound-dai-cells = <0>;
interrupt-parent = <&intc>;
interrupts = <1>;
clocks = <&cgu X1000_CLK_AIC>,
<&cgu X1000_CLK_I2S>;
clock-names = "aic", "i2s";
dmas = <&pdma X1000_DMA_I2S0_RX 0xffffffff>,
<&pdma X1000_DMA_I2S0_TX 0xffffffff>;
dma-names = "rx", "tx";
};
};

7
arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi
View File

@ -97,6 +97,13 @@
<0x00000000>; /* int3 */
};
rtc0: rtc@1fe07800 {
compatible = "loongson,ls2k1000-rtc";
reg = <0 0x1fe07800 0 0x78>;
interrupt-parent = <&liointc0>;
interrupts = <60 IRQ_TYPE_LEVEL_LOW>;
};
uart0: serial@1fe00000 {
compatible = "ns16550a";
reg = <0 0x1fe00000 0 0x8>;

7
arch/mips/boot/dts/loongson/ls7a-pch.dtsi
View File

@ -19,6 +19,13 @@
#interrupt-cells = <2>;
};
rtc0: rtc@100d0100 {
compatible = "loongson,ls7a-rtc";
reg = <0 0x100d0100 0 0x78>;
interrupt-parent = <&pic>;
interrupts = <52 IRQ_TYPE_LEVEL_HIGH>;
};
ls7a_uart0: serial@10080000 {
compatible = "ns16550a";
reg = <0 0x10080000 0 0x100>;

3
arch/mips/boot/dts/ralink/Makefile
View File

@ -8,6 +8,7 @@ dtb-$(CONFIG_DTB_VOCORE2) += vocore2.dtb
dtb-$(CONFIG_SOC_MT7621) += \
mt7621-gnubee-gb-pc1.dtb \
mt7621-gnubee-gb-pc2.dtb
mt7621-gnubee-gb-pc2.dtb \
mt7621-tplink-hc220-g5-v1.dtb
obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))

84
arch/mips/boot/dts/ralink/mt7621-tplink-hc220-g5-v1.dts Normal file
View File

@ -0,0 +1,84 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/dts-v1/;
#include "mt7621.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
/ {
compatible = "tplink,hc220-g5-v1", "mediatek,mt7621-soc";
model = "TP-Link HC220 G5 v1";
memory@0 {
device_type = "memory";
reg = <0x00000000 0x08000000>;
};
chosen {
bootargs = "earlycon console=ttyS0,115200";
};
gpio-keys {
compatible = "gpio-keys";
key-reset {
label = "reset";
gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
key-wps {
label = "wps";
gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
};
};
leds {
compatible = "gpio-leds";
led-fault {
color = <LED_COLOR_ID_RED>;
function = LED_FUNCTION_FAULT;
gpios = <&gpio 13 GPIO_ACTIVE_HIGH>;
};
led-power {
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_POWER;
gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "default-on";
};
led-wps {
color = <LED_COLOR_ID_BLUE>;
function = LED_FUNCTION_WPS;
gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
};
};
};
&pcie {
status = "okay";
};
&switch0 {
ports {
port@0 {
status = "okay";
label = "lan2";
};
port@1 {
status = "okay";
label = "lan1";
};
port@2 {
status = "okay";
label = "wan";
};
};
};

40
arch/mips/boot/dts/ralink/mt7628a.dtsi
View File

@ -51,85 +51,85 @@
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x1>;
pinmux_gpio_gpio: pinmux_gpio_gpio {
pinmux_gpio_gpio: gpio-gpio-pins {
pinctrl-single,bits = <0x0 0x0 0x3>;
};
pinmux_spi_cs1_cs: pinmux_spi_cs1_cs {
pinmux_spi_cs1_cs: spi-cs1-cs-pins {
pinctrl-single,bits = <0x0 0x0 0x30>;
};
pinmux_i2s_gpio: pinmux_i2s_gpio {
pinmux_i2s_gpio: i2s-gpio-pins {
pinctrl-single,bits = <0x0 0x40 0xc0>;
};
pinmux_uart0_uart: pinmux_uart0_uart0 {
pinmux_uart0_uart: uart0-uart0-pins {
pinctrl-single,bits = <0x0 0x0 0x300>;
};
pinmux_sdmode_sdxc: pinmux_sdmode_sdxc {
pinmux_sdmode_sdxc: sdmode-sdxc-pins {
pinctrl-single,bits = <0x0 0x0 0xc00>;
};
pinmux_sdmode_gpio: pinmux_sdmode_gpio {
pinmux_sdmode_gpio: sdmode-gpio-pins {
pinctrl-single,bits = <0x0 0x400 0xc00>;
};
pinmux_spi_spi: pinmux_spi_spi {
pinmux_spi_spi: spi-spi-pins {
pinctrl-single,bits = <0x0 0x0 0x1000>;
};
pinmux_refclk_gpio: pinmux_refclk_gpio {
pinmux_refclk_gpio: refclk-gpio-pins {
pinctrl-single,bits = <0x0 0x40000 0x40000>;
};
pinmux_i2c_i2c: pinmux_i2c_i2c {
pinmux_i2c_i2c: i2c-i2c-pins {
pinctrl-single,bits = <0x0 0x0 0x300000>;
};
pinmux_uart1_uart: pinmux_uart1_uart1 {
pinmux_uart1_uart: uart1-uart1-pins {
pinctrl-single,bits = <0x0 0x0 0x3000000>;
};
pinmux_uart2_uart: pinmux_uart2_uart {
pinmux_uart2_uart: uart2-uart-pins {
pinctrl-single,bits = <0x0 0x0 0xc000000>;
};
pinmux_pwm0_pwm: pinmux_pwm0_pwm {
pinmux_pwm0_pwm: pwm0-pwm-pins {
pinctrl-single,bits = <0x0 0x0 0x30000000>;
};
pinmux_pwm0_gpio: pinmux_pwm0_gpio {
pinmux_pwm0_gpio: pwm0-gpio-pins {
pinctrl-single,bits = <0x0 0x10000000
0x30000000>;
};
pinmux_pwm1_pwm: pinmux_pwm1_pwm {
pinmux_pwm1_pwm: pwm1-pwm-pins {
pinctrl-single,bits = <0x0 0x0 0xc0000000>;
};
pinmux_pwm1_gpio: pinmux_pwm1_gpio {
pinmux_pwm1_gpio: pwm1-gpio-pins {
pinctrl-single,bits = <0x0 0x40000000
0xc0000000>;
};
pinmux_p0led_an_gpio: pinmux_p0led_an_gpio {
pinmux_p0led_an_gpio: p0led-an-gpio-pins {
pinctrl-single,bits = <0x4 0x4 0xc>;
};
pinmux_p1led_an_gpio: pinmux_p1led_an_gpio {
pinmux_p1led_an_gpio: p1led-an-gpio-pins {
pinctrl-single,bits = <0x4 0x10 0x30>;
};
pinmux_p2led_an_gpio: pinmux_p2led_an_gpio {
pinmux_p2led_an_gpio: p2led-an-gpio-pins {
pinctrl-single,bits = <0x4 0x40 0xc0>;
};
pinmux_p3led_an_gpio: pinmux_p3led_an_gpio {
pinmux_p3led_an_gpio: p3led-an-gpio-pins {
pinctrl-single,bits = <0x4 0x100 0x300>;
};
pinmux_p4led_an_gpio: pinmux_p4led_an_gpio {
pinmux_p4led_an_gpio: p4led-an-gpio-pins {
pinctrl-single,bits = <0x4 0x400 0xc00>;
};
};

627
arch/mips/cavium-octeon/octeon-usb.c
View File

@ -8,232 +8,255 @@
* for more details.
*/
#include <linux/module.h>
#include <linux/bitfield.h>
#include <linux/bits.h>
#include <linux/device.h>
#include <linux/mutex.h>
#include <linux/delay.h>
#include <linux/of_platform.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/of_platform.h>
#include <asm/octeon/octeon.h>
/*
* USB Control Register
*/
#define USBDRD_UCTL_CTL 0x00
/* BIST fast-clear mode select. A BIST run with this bit set
* clears all entries in USBH RAMs to 0x0.
*/
# define USBDRD_UCTL_CTL_CLEAR_BIST BIT(63)
/* 1 = Start BIST and cleared by hardware */
# define USBDRD_UCTL_CTL_START_BIST BIT(62)
/* Reference clock select for SuperSpeed and HighSpeed PLLs:
* 0x0 = Both PLLs use DLMC_REF_CLK0 for reference clock
* 0x1 = Both PLLs use DLMC_REF_CLK1 for reference clock
* 0x2 = SuperSpeed PLL uses DLMC_REF_CLK0 for reference clock &
* HighSpeed PLL uses PLL_REF_CLK for reference clck
* 0x3 = SuperSpeed PLL uses DLMC_REF_CLK1 for reference clock &
* HighSpeed PLL uses PLL_REF_CLK for reference clck
*/
# define USBDRD_UCTL_CTL_REF_CLK_SEL GENMASK(61, 60)
/* 1 = Spread-spectrum clock enable, 0 = SS clock disable */
# define USBDRD_UCTL_CTL_SSC_EN BIT(59)
/* Spread-spectrum clock modulation range:
* 0x0 = -4980 ppm downspread
* 0x1 = -4492 ppm downspread
* 0x2 = -4003 ppm downspread
* 0x3 - 0x7 = Reserved
*/
# define USBDRD_UCTL_CTL_SSC_RANGE GENMASK(58, 56)
/* Enable non-standard oscillator frequencies:
* [55:53] = modules -1
* [52:47] = 2's complement push amount, 0 = Feature disabled
*/
# define USBDRD_UCTL_CTL_SSC_REF_CLK_SEL GENMASK(55, 47)
/* Reference clock multiplier for non-standard frequencies:
* 0x19 = 100MHz on DLMC_REF_CLK* if REF_CLK_SEL = 0x0 or 0x1
* 0x28 = 125MHz on DLMC_REF_CLK* if REF_CLK_SEL = 0x0 or 0x1
* 0x32 = 50MHz on DLMC_REF_CLK* if REF_CLK_SEL = 0x0 or 0x1
* Other Values = Reserved
*/
# define USBDRD_UCTL_CTL_MPLL_MULTIPLIER GENMASK(46, 40)
/* Enable reference clock to prescaler for SuperSpeed functionality.
* Should always be set to "1"
*/
# define USBDRD_UCTL_CTL_REF_SSP_EN BIT(39)
/* Divide the reference clock by 2 before entering the
* REF_CLK_FSEL divider:
* If REF_CLK_SEL = 0x0 or 0x1, then only 0x0 is legal
* If REF_CLK_SEL = 0x2 or 0x3, then:
* 0x1 = DLMC_REF_CLK* is 125MHz
* 0x0 = DLMC_REF_CLK* is another supported frequency
*/
# define USBDRD_UCTL_CTL_REF_CLK_DIV2 BIT(38)
/* Select reference clock freqnuency for both PLL blocks:
* 0x27 = REF_CLK_SEL is 0x0 or 0x1
* 0x07 = REF_CLK_SEL is 0x2 or 0x3
*/
# define USBDRD_UCTL_CTL_REF_CLK_FSEL GENMASK(37, 32)
/* Controller clock enable. */
# define USBDRD_UCTL_CTL_H_CLK_EN BIT(30)
/* Select bypass input to controller clock divider:
* 0x0 = Use divided coprocessor clock from H_CLKDIV
* 0x1 = Use clock from GPIO pins
*/
# define USBDRD_UCTL_CTL_H_CLK_BYP_SEL BIT(29)
/* Reset controller clock divider. */
# define USBDRD_UCTL_CTL_H_CLKDIV_RST BIT(28)
/* Clock divider select:
* 0x0 = divide by 1
* 0x1 = divide by 2
* 0x2 = divide by 4
* 0x3 = divide by 6
* 0x4 = divide by 8
* 0x5 = divide by 16
* 0x6 = divide by 24
* 0x7 = divide by 32
*/
# define USBDRD_UCTL_CTL_H_CLKDIV_SEL GENMASK(26, 24)
/* USB3 port permanently attached: 0x0 = No, 0x1 = Yes */
# define USBDRD_UCTL_CTL_USB3_PORT_PERM_ATTACH BIT(21)
/* USB2 port permanently attached: 0x0 = No, 0x1 = Yes */
# define USBDRD_UCTL_CTL_USB2_PORT_PERM_ATTACH BIT(20)
/* Disable SuperSpeed PHY: 0x0 = No, 0x1 = Yes */
# define USBDRD_UCTL_CTL_USB3_PORT_DISABLE BIT(18)
/* Disable HighSpeed PHY: 0x0 = No, 0x1 = Yes */
# define USBDRD_UCTL_CTL_USB2_PORT_DISABLE BIT(16)
/* Enable PHY SuperSpeed block power: 0x0 = No, 0x1 = Yes */
# define USBDRD_UCTL_CTL_SS_POWER_EN BIT(14)
/* Enable PHY HighSpeed block power: 0x0 = No, 0x1 = Yes */
# define USBDRD_UCTL_CTL_HS_POWER_EN BIT(12)
/* Enable USB UCTL interface clock: 0xx = No, 0x1 = Yes */
# define USBDRD_UCTL_CTL_CSCLK_EN BIT(4)
/* Controller mode: 0x0 = Host, 0x1 = Device */
# define USBDRD_UCTL_CTL_DRD_MODE BIT(3)
/* PHY reset */
# define USBDRD_UCTL_CTL_UPHY_RST BIT(2)
/* Software reset UAHC */
# define USBDRD_UCTL_CTL_UAHC_RST BIT(1)
/* Software resets UCTL */
# define USBDRD_UCTL_CTL_UCTL_RST BIT(0)
/* USB Control Register */
union cvm_usbdrd_uctl_ctl {
uint64_t u64;
struct cvm_usbdrd_uctl_ctl_s {
/* 1 = BIST and set all USB RAMs to 0x0, 0 = BIST */
__BITFIELD_FIELD(uint64_t clear_bist:1,
/* 1 = Start BIST and cleared by hardware */
__BITFIELD_FIELD(uint64_t start_bist:1,
/* Reference clock select for SuperSpeed and HighSpeed PLLs:
* 0x0 = Both PLLs use DLMC_REF_CLK0 for reference clock
* 0x1 = Both PLLs use DLMC_REF_CLK1 for reference clock
* 0x2 = SuperSpeed PLL uses DLMC_REF_CLK0 for reference clock &
* HighSpeed PLL uses PLL_REF_CLK for reference clck
* 0x3 = SuperSpeed PLL uses DLMC_REF_CLK1 for reference clock &
* HighSpeed PLL uses PLL_REF_CLK for reference clck
*/
__BITFIELD_FIELD(uint64_t ref_clk_sel:2,
/* 1 = Spread-spectrum clock enable, 0 = SS clock disable */
__BITFIELD_FIELD(uint64_t ssc_en:1,
/* Spread-spectrum clock modulation range:
* 0x0 = -4980 ppm downspread
* 0x1 = -4492 ppm downspread
* 0x2 = -4003 ppm downspread
* 0x3 - 0x7 = Reserved
*/
__BITFIELD_FIELD(uint64_t ssc_range:3,
/* Enable non-standard oscillator frequencies:
* [55:53] = modules -1
* [52:47] = 2's complement push amount, 0 = Feature disabled
*/
__BITFIELD_FIELD(uint64_t ssc_ref_clk_sel:9,
/* Reference clock multiplier for non-standard frequencies:
* 0x19 = 100MHz on DLMC_REF_CLK* if REF_CLK_SEL = 0x0 or 0x1
* 0x28 = 125MHz on DLMC_REF_CLK* if REF_CLK_SEL = 0x0 or 0x1
* 0x32 = 50MHz on DLMC_REF_CLK* if REF_CLK_SEL = 0x0 or 0x1
* Other Values = Reserved
*/
__BITFIELD_FIELD(uint64_t mpll_multiplier:7,
/* Enable reference clock to prescaler for SuperSpeed functionality.
* Should always be set to "1"
*/
__BITFIELD_FIELD(uint64_t ref_ssp_en:1,
/* Divide the reference clock by 2 before entering the
* REF_CLK_FSEL divider:
* If REF_CLK_SEL = 0x0 or 0x1, then only 0x0 is legal
* If REF_CLK_SEL = 0x2 or 0x3, then:
* 0x1 = DLMC_REF_CLK* is 125MHz
* 0x0 = DLMC_REF_CLK* is another supported frequency
*/
__BITFIELD_FIELD(uint64_t ref_clk_div2:1,
/* Select reference clock freqnuency for both PLL blocks:
* 0x27 = REF_CLK_SEL is 0x0 or 0x1
* 0x07 = REF_CLK_SEL is 0x2 or 0x3
*/
__BITFIELD_FIELD(uint64_t ref_clk_fsel:6,
/* Reserved */
__BITFIELD_FIELD(uint64_t reserved_31_31:1,
/* Controller clock enable. */
__BITFIELD_FIELD(uint64_t h_clk_en:1,
/* Select bypass input to controller clock divider:
* 0x0 = Use divided coprocessor clock from H_CLKDIV
* 0x1 = Use clock from GPIO pins
*/
__BITFIELD_FIELD(uint64_t h_clk_byp_sel:1,
/* Reset controller clock divider. */
__BITFIELD_FIELD(uint64_t h_clkdiv_rst:1,
/* Reserved */
__BITFIELD_FIELD(uint64_t reserved_27_27:1,
/* Clock divider select:
* 0x0 = divide by 1
* 0x1 = divide by 2
* 0x2 = divide by 4
* 0x3 = divide by 6
* 0x4 = divide by 8
* 0x5 = divide by 16
* 0x6 = divide by 24
* 0x7 = divide by 32
*/
__BITFIELD_FIELD(uint64_t h_clkdiv_sel:3,
/* Reserved */
__BITFIELD_FIELD(uint64_t reserved_22_23:2,
/* USB3 port permanently attached: 0x0 = No, 0x1 = Yes */
__BITFIELD_FIELD(uint64_t usb3_port_perm_attach:1,
/* USB2 port permanently attached: 0x0 = No, 0x1 = Yes */
__BITFIELD_FIELD(uint64_t usb2_port_perm_attach:1,
/* Reserved */
__BITFIELD_FIELD(uint64_t reserved_19_19:1,
/* Disable SuperSpeed PHY: 0x0 = No, 0x1 = Yes */
__BITFIELD_FIELD(uint64_t usb3_port_disable:1,
/* Reserved */
__BITFIELD_FIELD(uint64_t reserved_17_17:1,
/* Disable HighSpeed PHY: 0x0 = No, 0x1 = Yes */
__BITFIELD_FIELD(uint64_t usb2_port_disable:1,
/* Reserved */
__BITFIELD_FIELD(uint64_t reserved_15_15:1,
/* Enable PHY SuperSpeed block power: 0x0 = No, 0x1 = Yes */
__BITFIELD_FIELD(uint64_t ss_power_en:1,
/* Reserved */
__BITFIELD_FIELD(uint64_t reserved_13_13:1,
/* Enable PHY HighSpeed block power: 0x0 = No, 0x1 = Yes */
__BITFIELD_FIELD(uint64_t hs_power_en:1,
/* Reserved */
__BITFIELD_FIELD(uint64_t reserved_5_11:7,
/* Enable USB UCTL interface clock: 0xx = No, 0x1 = Yes */
__BITFIELD_FIELD(uint64_t csclk_en:1,
/* Controller mode: 0x0 = Host, 0x1 = Device */
__BITFIELD_FIELD(uint64_t drd_mode:1,
/* PHY reset */
__BITFIELD_FIELD(uint64_t uphy_rst:1,
/* Software reset UAHC */
__BITFIELD_FIELD(uint64_t uahc_rst:1,
/* Software resets UCTL */
__BITFIELD_FIELD(uint64_t uctl_rst:1,
;)))))))))))))))))))))))))))))))))
} s;
};
#define USBDRD_UCTL_BIST_STATUS 0x08
#define USBDRD_UCTL_SPARE0 0x10
#define USBDRD_UCTL_INTSTAT 0x30
#define USBDRD_UCTL_PORT_CFG_HS(port) (0x40 + (0x20 * port))
#define USBDRD_UCTL_PORT_CFG_SS(port) (0x48 + (0x20 * port))
#define USBDRD_UCTL_PORT_CR_DBG_CFG(port) (0x50 + (0x20 * port))
#define USBDRD_UCTL_PORT_CR_DBG_STATUS(port) (0x58 + (0x20 * port))
/* UAHC Configuration Register */
union cvm_usbdrd_uctl_host_cfg {
uint64_t u64;
struct cvm_usbdrd_uctl_host_cfg_s {
/* Reserved */
__BITFIELD_FIELD(uint64_t reserved_60_63:4,
/* Indicates minimum value of all received BELT values */
__BITFIELD_FIELD(uint64_t host_current_belt:12,
/* Reserved */
__BITFIELD_FIELD(uint64_t reserved_38_47:10,
/* HS jitter adjustment */
__BITFIELD_FIELD(uint64_t fla:6,
/* Reserved */
__BITFIELD_FIELD(uint64_t reserved_29_31:3,
/* Bus-master enable: 0x0 = Disabled (stall DMAs), 0x1 = enabled */
__BITFIELD_FIELD(uint64_t bme:1,
/* Overcurrent protection enable: 0x0 = unavailable, 0x1 = available */
__BITFIELD_FIELD(uint64_t oci_en:1,
/* Overcurrent sene selection:
* 0x0 = Overcurrent indication from off-chip is active-low
* 0x1 = Overcurrent indication from off-chip is active-high
*/
__BITFIELD_FIELD(uint64_t oci_active_high_en:1,
/* Port power control enable: 0x0 = unavailable, 0x1 = available */
__BITFIELD_FIELD(uint64_t ppc_en:1,
/* Port power control sense selection:
* 0x0 = Port power to off-chip is active-low
* 0x1 = Port power to off-chip is active-high
*/
__BITFIELD_FIELD(uint64_t ppc_active_high_en:1,
/* Reserved */
__BITFIELD_FIELD(uint64_t reserved_0_23:24,
;)))))))))))
} s;
};
/*
* UCTL Configuration Register
*/
#define USBDRD_UCTL_HOST_CFG 0xe0
/* Indicates minimum value of all received BELT values */
# define USBDRD_UCTL_HOST_CFG_HOST_CURRENT_BELT GENMASK(59, 48)
/* HS jitter adjustment */
# define USBDRD_UCTL_HOST_CFG_FLA GENMASK(37, 32)
/* Bus-master enable: 0x0 = Disabled (stall DMAs), 0x1 = enabled */
# define USBDRD_UCTL_HOST_CFG_BME BIT(28)
/* Overcurrent protection enable: 0x0 = unavailable, 0x1 = available */
# define USBDRD_UCTL_HOST_OCI_EN BIT(27)
/* Overcurrent sene selection:
* 0x0 = Overcurrent indication from off-chip is active-low
* 0x1 = Overcurrent indication from off-chip is active-high
*/
# define USBDRD_UCTL_HOST_OCI_ACTIVE_HIGH_EN BIT(26)
/* Port power control enable: 0x0 = unavailable, 0x1 = available */
# define USBDRD_UCTL_HOST_PPC_EN BIT(25)
/* Port power control sense selection:
* 0x0 = Port power to off-chip is active-low
* 0x1 = Port power to off-chip is active-high
*/
# define USBDRD_UCTL_HOST_PPC_ACTIVE_HIGH_EN BIT(24)
/* UCTL Shim Features Register */
union cvm_usbdrd_uctl_shim_cfg {
uint64_t u64;
struct cvm_usbdrd_uctl_shim_cfg_s {
/* Out-of-bound UAHC register access: 0 = read, 1 = write */
__BITFIELD_FIELD(uint64_t xs_ncb_oob_wrn:1,
/* Reserved */
__BITFIELD_FIELD(uint64_t reserved_60_62:3,
/* SRCID error log for out-of-bound UAHC register access:
* [59:58] = chipID
* [57] = Request source: 0 = core, 1 = NCB-device
* [56:51] = Core/NCB-device number, [56] always 0 for NCB devices
* [50:48] = SubID
*/
__BITFIELD_FIELD(uint64_t xs_ncb_oob_osrc:12,
/* Error log for bad UAHC DMA access: 0 = Read log, 1 = Write log */
__BITFIELD_FIELD(uint64_t xm_bad_dma_wrn:1,
/* Reserved */
__BITFIELD_FIELD(uint64_t reserved_44_46:3,
/* Encoded error type for bad UAHC DMA */
__BITFIELD_FIELD(uint64_t xm_bad_dma_type:4,
/* Reserved */
__BITFIELD_FIELD(uint64_t reserved_13_39:27,
/* Select the IOI read command used by DMA accesses */
__BITFIELD_FIELD(uint64_t dma_read_cmd:1,
/* Reserved */
__BITFIELD_FIELD(uint64_t reserved_10_11:2,
/* Select endian format for DMA accesses to the L2c:
* 0x0 = Little endian
*` 0x1 = Big endian
* 0x2 = Reserved
* 0x3 = Reserved
*/
__BITFIELD_FIELD(uint64_t dma_endian_mode:2,
/* Reserved */
__BITFIELD_FIELD(uint64_t reserved_2_7:6,
/* Select endian format for IOI CSR access to UAHC:
* 0x0 = Little endian
*` 0x1 = Big endian
* 0x2 = Reserved
* 0x3 = Reserved
*/
__BITFIELD_FIELD(uint64_t csr_endian_mode:2,
;))))))))))))
} s;
};
/*
* UCTL Shim Features Register
*/
#define USBDRD_UCTL_SHIM_CFG 0xe8
/* Out-of-bound UAHC register access: 0 = read, 1 = write */
# define USBDRD_UCTL_SHIM_CFG_XS_NCB_OOB_WRN BIT(63)
/* SRCID error log for out-of-bound UAHC register access:
* [59:58] = chipID
* [57] = Request source: 0 = core, 1 = NCB-device
* [56:51] = Core/NCB-device number, [56] always 0 for NCB devices
* [50:48] = SubID
*/
# define USBDRD_UCTL_SHIM_CFG_XS_NCB_OOB_OSRC GENMASK(59, 48)
/* Error log for bad UAHC DMA access: 0 = Read log, 1 = Write log */
# define USBDRD_UCTL_SHIM_CFG_XM_BAD_DMA_WRN BIT(47)
/* Encoded error type for bad UAHC DMA */
# define USBDRD_UCTL_SHIM_CFG_XM_BAD_DMA_TYPE GENMASK(43, 40)
/* Select the IOI read command used by DMA accesses */
# define USBDRD_UCTL_SHIM_CFG_DMA_READ_CMD BIT(12)
/* Select endian format for DMA accesses to the L2C:
* 0x0 = Little endian
* 0x1 = Big endian
* 0x2 = Reserved
* 0x3 = Reserved
*/
# define USBDRD_UCTL_SHIM_CFG_DMA_ENDIAN_MODE GENMASK(9, 8)
/* Select endian format for IOI CSR access to UAHC:
* 0x0 = Little endian
* 0x1 = Big endian
* 0x2 = Reserved
* 0x3 = Reserved
*/
# define USBDRD_UCTL_SHIM_CFG_CSR_ENDIAN_MODE GENMASK(1, 0)
#define OCTEON_H_CLKDIV_SEL 8
#define OCTEON_MIN_H_CLK_RATE 150000000
#define OCTEON_MAX_H_CLK_RATE 300000000
#define USBDRD_UCTL_ECC 0xf0
#define USBDRD_UCTL_SPARE1 0xf8
static DEFINE_MUTEX(dwc3_octeon_clocks_mutex);
static uint8_t clk_div[OCTEON_H_CLKDIV_SEL] = {1, 2, 4, 6, 8, 16, 24, 32};
static int dwc3_octeon_config_power(struct device *dev, u64 base)
#ifdef CONFIG_CAVIUM_OCTEON_SOC
#include <asm/octeon/octeon.h>
static inline uint64_t dwc3_octeon_readq(void __iomem *addr)
{
return cvmx_readq_csr(addr);
}
static inline void dwc3_octeon_writeq(void __iomem *base, uint64_t val)
{
cvmx_writeq_csr(base, val);
}
static void dwc3_octeon_config_gpio(int index, int gpio)
{
#define UCTL_HOST_CFG 0xe0
union cvm_usbdrd_uctl_host_cfg uctl_host_cfg;
union cvmx_gpio_bit_cfgx gpio_bit;
if ((OCTEON_IS_MODEL(OCTEON_CN73XX) ||
OCTEON_IS_MODEL(OCTEON_CNF75XX))
&& gpio <= 31) {
gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_BIT_CFGX(gpio));
gpio_bit.s.tx_oe = 1;
gpio_bit.s.output_sel = (index == 0 ? 0x14 : 0x15);
cvmx_write_csr(CVMX_GPIO_BIT_CFGX(gpio), gpio_bit.u64);
} else if (gpio <= 15) {
gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_BIT_CFGX(gpio));
gpio_bit.s.tx_oe = 1;
gpio_bit.s.output_sel = (index == 0 ? 0x14 : 0x19);
cvmx_write_csr(CVMX_GPIO_BIT_CFGX(gpio), gpio_bit.u64);
} else {
gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_XBIT_CFGX(gpio));
gpio_bit.s.tx_oe = 1;
gpio_bit.s.output_sel = (index == 0 ? 0x14 : 0x19);
cvmx_write_csr(CVMX_GPIO_XBIT_CFGX(gpio), gpio_bit.u64);
}
}
#else
static inline uint64_t dwc3_octeon_readq(void __iomem *addr)
{
return 0;
}
static inline void dwc3_octeon_writeq(void __iomem *base, uint64_t val) { }
static inline void dwc3_octeon_config_gpio(int index, int gpio) { }
#endif
static int dwc3_octeon_get_divider(void)
{
static const uint8_t clk_div[] = { 1, 2, 4, 6, 8, 16, 24, 32 };
int div = 0;
while (div < ARRAY_SIZE(clk_div)) {
uint64_t rate = octeon_get_io_clock_rate() / clk_div[div];
if (rate <= 300000000 && rate >= 150000000)
break;
div++;
}
return div;
}
static int dwc3_octeon_config_power(struct device *dev, void __iomem *base)
{
uint32_t gpio_pwr[3];
int gpio, len, power_active_low;
struct device_node *node = dev->of_node;
int index = (base >> 24) & 1;
u64 val;
void __iomem *uctl_host_cfg_reg = base + USBDRD_UCTL_HOST_CFG;
if (of_find_property(node, "power", &len) != NULL) {
if (len == 12) {
@ -248,51 +271,33 @@ static int dwc3_octeon_config_power(struct device *dev, u64 base)
dev_err(dev, "invalid power configuration\n");
return -EINVAL;
}
if ((OCTEON_IS_MODEL(OCTEON_CN73XX) ||
OCTEON_IS_MODEL(OCTEON_CNF75XX))
&& gpio <= 31) {
gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_BIT_CFGX(gpio));
gpio_bit.s.tx_oe = 1;
gpio_bit.s.output_sel = (index == 0 ? 0x14 : 0x15);
cvmx_write_csr(CVMX_GPIO_BIT_CFGX(gpio), gpio_bit.u64);
} else if (gpio <= 15) {
gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_BIT_CFGX(gpio));
gpio_bit.s.tx_oe = 1;
gpio_bit.s.output_sel = (index == 0 ? 0x14 : 0x19);
cvmx_write_csr(CVMX_GPIO_BIT_CFGX(gpio), gpio_bit.u64);
} else {
gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_XBIT_CFGX(gpio));
gpio_bit.s.tx_oe = 1;
gpio_bit.s.output_sel = (index == 0 ? 0x14 : 0x19);
cvmx_write_csr(CVMX_GPIO_XBIT_CFGX(gpio), gpio_bit.u64);
}
dwc3_octeon_config_gpio(((u64)base >> 24) & 1, gpio);
/* Enable XHCI power control and set if active high or low. */
uctl_host_cfg.u64 = cvmx_read_csr(base + UCTL_HOST_CFG);
uctl_host_cfg.s.ppc_en = 1;
uctl_host_cfg.s.ppc_active_high_en = !power_active_low;
cvmx_write_csr(base + UCTL_HOST_CFG, uctl_host_cfg.u64);
val = dwc3_octeon_readq(uctl_host_cfg_reg);
val |= USBDRD_UCTL_HOST_PPC_EN;
if (power_active_low)
val &= ~USBDRD_UCTL_HOST_PPC_ACTIVE_HIGH_EN;
else
val |= USBDRD_UCTL_HOST_PPC_ACTIVE_HIGH_EN;
dwc3_octeon_writeq(uctl_host_cfg_reg, val);
} else {
/* Disable XHCI power control and set if active high. */
uctl_host_cfg.u64 = cvmx_read_csr(base + UCTL_HOST_CFG);
uctl_host_cfg.s.ppc_en = 0;
uctl_host_cfg.s.ppc_active_high_en = 0;
cvmx_write_csr(base + UCTL_HOST_CFG, uctl_host_cfg.u64);
val = dwc3_octeon_readq(uctl_host_cfg_reg);
val &= ~USBDRD_UCTL_HOST_PPC_EN;
val &= ~USBDRD_UCTL_HOST_PPC_ACTIVE_HIGH_EN;
dwc3_octeon_writeq(uctl_host_cfg_reg, val);
dev_info(dev, "power control disabled\n");
}
return 0;
}
static int dwc3_octeon_clocks_start(struct device *dev, u64 base)
static int dwc3_octeon_clocks_start(struct device *dev, void __iomem *base)
{
union cvm_usbdrd_uctl_ctl uctl_ctl;
int ref_clk_sel = 2;
u64 div;
int i, div, mpll_mul, ref_clk_fsel, ref_clk_sel = 2;
u32 clock_rate;
int mpll_mul;
int i;
u64 h_clk_rate;
u64 uctl_ctl_reg = base;
u64 val;
void __iomem *uctl_ctl_reg = base + USBDRD_UCTL_CTL;
if (dev->of_node) {
const char *ss_clock_type;
@ -356,44 +361,42 @@ static int dwc3_octeon_clocks_start(struct device *dev, u64 base)
/* Step 2: Select GPIO for overcurrent indication, if desired. SKIP */
/* Step 3: Assert all resets. */
uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
uctl_ctl.s.uphy_rst = 1;
uctl_ctl.s.uahc_rst = 1;
uctl_ctl.s.uctl_rst = 1;
cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64);
val = dwc3_octeon_readq(uctl_ctl_reg);
val |= USBDRD_UCTL_CTL_UPHY_RST |
USBDRD_UCTL_CTL_UAHC_RST |
USBDRD_UCTL_CTL_UCTL_RST;
dwc3_octeon_writeq(uctl_ctl_reg, val);
/* Step 4a: Reset the clock dividers. */
uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
uctl_ctl.s.h_clkdiv_rst = 1;
cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64);
val = dwc3_octeon_readq(uctl_ctl_reg);
val |= USBDRD_UCTL_CTL_H_CLKDIV_RST;
dwc3_octeon_writeq(uctl_ctl_reg, val);
/* Step 4b: Select controller clock frequency. */
for (div = 0; div < OCTEON_H_CLKDIV_SEL; div++) {
h_clk_rate = octeon_get_io_clock_rate() / clk_div[div];
if (h_clk_rate <= OCTEON_MAX_H_CLK_RATE &&
h_clk_rate >= OCTEON_MIN_H_CLK_RATE)
break;
}
uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
uctl_ctl.s.h_clkdiv_sel = div;
uctl_ctl.s.h_clk_en = 1;
cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64);
uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
if ((div != uctl_ctl.s.h_clkdiv_sel) || (!uctl_ctl.s.h_clk_en)) {
div = dwc3_octeon_get_divider();
val = dwc3_octeon_readq(uctl_ctl_reg);
val &= ~USBDRD_UCTL_CTL_H_CLKDIV_SEL;
val |= FIELD_PREP(USBDRD_UCTL_CTL_H_CLKDIV_SEL, div);
val |= USBDRD_UCTL_CTL_H_CLK_EN;
dwc3_octeon_writeq(uctl_ctl_reg, val);
val = dwc3_octeon_readq(uctl_ctl_reg);
if ((div != FIELD_GET(USBDRD_UCTL_CTL_H_CLKDIV_SEL, val)) ||
(!(FIELD_GET(USBDRD_UCTL_CTL_H_CLK_EN, val)))) {
dev_err(dev, "dwc3 controller clock init failure.\n");
return -EINVAL;
}
/* Step 4c: Deassert the controller clock divider reset. */
uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
uctl_ctl.s.h_clkdiv_rst = 0;
cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64);
val &= ~USBDRD_UCTL_CTL_H_CLKDIV_RST;
dwc3_octeon_writeq(uctl_ctl_reg, val);
/* Step 5a: Reference clock configuration. */
uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
uctl_ctl.s.ref_clk_sel = ref_clk_sel;
uctl_ctl.s.ref_clk_fsel = 0x07;
uctl_ctl.s.ref_clk_div2 = 0;
val = dwc3_octeon_readq(uctl_ctl_reg);
val &= ~USBDRD_UCTL_CTL_REF_CLK_DIV2;
val &= ~USBDRD_UCTL_CTL_REF_CLK_SEL;
val |= FIELD_PREP(USBDRD_UCTL_CTL_REF_CLK_SEL, ref_clk_sel);
ref_clk_fsel = 0x07;
switch (clock_rate) {
default:
dev_warn(dev, "Invalid ref_clk %u, using 100000000 instead\n",
@ -402,7 +405,7 @@ static int dwc3_octeon_clocks_start(struct device *dev, u64 base)
case 100000000:
mpll_mul = 0x19;
if (ref_clk_sel < 2)
uctl_ctl.s.ref_clk_fsel = 0x27;
ref_clk_fsel = 0x27;
break;
case 50000000:
mpll_mul = 0x32;
@ -411,28 +414,32 @@ static int dwc3_octeon_clocks_start(struct device *dev, u64 base)
mpll_mul = 0x28;
break;
}
uctl_ctl.s.mpll_multiplier = mpll_mul;
val &= ~USBDRD_UCTL_CTL_REF_CLK_FSEL;
val |= FIELD_PREP(USBDRD_UCTL_CTL_REF_CLK_FSEL, ref_clk_fsel);
val &= ~USBDRD_UCTL_CTL_MPLL_MULTIPLIER;
val |= FIELD_PREP(USBDRD_UCTL_CTL_MPLL_MULTIPLIER, mpll_mul);
/* Step 5b: Configure and enable spread-spectrum for SuperSpeed. */
uctl_ctl.s.ssc_en = 1;
val |= USBDRD_UCTL_CTL_SSC_EN;
/* Step 5c: Enable SuperSpeed. */
uctl_ctl.s.ref_ssp_en = 1;
val |= USBDRD_UCTL_CTL_REF_SSP_EN;
/* Step 5d: Configure PHYs. SKIP */
/* Step 6a & 6b: Power up PHYs. */
uctl_ctl.s.hs_power_en = 1;
uctl_ctl.s.ss_power_en = 1;
cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64);
val |= USBDRD_UCTL_CTL_HS_POWER_EN;
val |= USBDRD_UCTL_CTL_SS_POWER_EN;
dwc3_octeon_writeq(uctl_ctl_reg, val);
/* Step 7: Wait 10 controller-clock cycles to take effect. */
udelay(10);
/* Step 8a: Deassert UCTL reset signal. */
uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
uctl_ctl.s.uctl_rst = 0;
cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64);
val = dwc3_octeon_readq(uctl_ctl_reg);
val &= ~USBDRD_UCTL_CTL_UCTL_RST;
dwc3_octeon_writeq(uctl_ctl_reg, val);
/* Step 8b: Wait 10 controller-clock cycles. */
udelay(10);
@ -442,53 +449,49 @@ static int dwc3_octeon_clocks_start(struct device *dev, u64 base)
return -EINVAL;
/* Step 8d: Deassert UAHC reset signal. */
uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
uctl_ctl.s.uahc_rst = 0;
cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64);
val = dwc3_octeon_readq(uctl_ctl_reg);
val &= ~USBDRD_UCTL_CTL_UAHC_RST;
dwc3_octeon_writeq(uctl_ctl_reg, val);
/* Step 8e: Wait 10 controller-clock cycles. */
udelay(10);
/* Step 9: Enable conditional coprocessor clock of UCTL. */
uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
uctl_ctl.s.csclk_en = 1;
cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64);
val = dwc3_octeon_readq(uctl_ctl_reg);
val |= USBDRD_UCTL_CTL_CSCLK_EN;
dwc3_octeon_writeq(uctl_ctl_reg, val);
/*Step 10: Set for host mode only. */
uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
uctl_ctl.s.drd_mode = 0;
cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64);
val = dwc3_octeon_readq(uctl_ctl_reg);
val &= ~USBDRD_UCTL_CTL_DRD_MODE;
dwc3_octeon_writeq(uctl_ctl_reg, val);
return 0;
}
static void __init dwc3_octeon_set_endian_mode(u64 base)
static void __init dwc3_octeon_set_endian_mode(void __iomem *base)
{
#define UCTL_SHIM_CFG 0xe8
union cvm_usbdrd_uctl_shim_cfg shim_cfg;
u64 val;
void __iomem *uctl_shim_cfg_reg = base + USBDRD_UCTL_SHIM_CFG;
shim_cfg.u64 = cvmx_read_csr(base + UCTL_SHIM_CFG);
val = dwc3_octeon_readq(uctl_shim_cfg_reg);
val &= ~USBDRD_UCTL_SHIM_CFG_DMA_ENDIAN_MODE;
val &= ~USBDRD_UCTL_SHIM_CFG_CSR_ENDIAN_MODE;
#ifdef __BIG_ENDIAN
shim_cfg.s.dma_endian_mode = 1;
shim_cfg.s.csr_endian_mode = 1;
#else
shim_cfg.s.dma_endian_mode = 0;
shim_cfg.s.csr_endian_mode = 0;
val |= FIELD_PREP(USBDRD_UCTL_SHIM_CFG_DMA_ENDIAN_MODE, 1);
val |= FIELD_PREP(USBDRD_UCTL_SHIM_CFG_CSR_ENDIAN_MODE, 1);
#endif
cvmx_write_csr(base + UCTL_SHIM_CFG, shim_cfg.u64);
dwc3_octeon_writeq(uctl_shim_cfg_reg, val);
}
#define CVMX_USBDRDX_UCTL_CTL(index) \
(CVMX_ADD_IO_SEG(0x0001180068000000ull) + \
((index & 1) * 0x1000000ull))
static void __init dwc3_octeon_phy_reset(u64 base)
static void __init dwc3_octeon_phy_reset(void __iomem *base)
{
union cvm_usbdrd_uctl_ctl uctl_ctl;
int index = (base >> 24) & 1;
u64 val;
void __iomem *uctl_ctl_reg = base + USBDRD_UCTL_CTL;
uctl_ctl.u64 = cvmx_read_csr(CVMX_USBDRDX_UCTL_CTL(index));
uctl_ctl.s.uphy_rst = 0;
cvmx_write_csr(CVMX_USBDRDX_UCTL_CTL(index), uctl_ctl.u64);
val = dwc3_octeon_readq(uctl_ctl_reg);
val &= ~USBDRD_UCTL_CTL_UPHY_RST;
dwc3_octeon_writeq(uctl_ctl_reg, val);
}
static int __init dwc3_octeon_device_init(void)
@ -527,10 +530,10 @@ static int __init dwc3_octeon_device_init(void)
}
mutex_lock(&dwc3_octeon_clocks_mutex);
if (dwc3_octeon_clocks_start(&pdev->dev, (u64)base) == 0)
if (dwc3_octeon_clocks_start(&pdev->dev, base) == 0)
dev_info(&pdev->dev, "clocks initialized.\n");
dwc3_octeon_set_endian_mode((u64)base);
dwc3_octeon_phy_reset((u64)base);
dwc3_octeon_set_endian_mode(base);
dwc3_octeon_phy_reset(base);
mutex_unlock(&dwc3_octeon_clocks_mutex);
devm_iounmap(&pdev->dev, base);
devm_release_mem_region(&pdev->dev, res->start,

47
arch/mips/configs/ci20_defconfig
View File

@ -19,19 +19,19 @@ CONFIG_USER_NS=y
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_KALLSYMS_ALL=y
CONFIG_EMBEDDED=y
# CONFIG_VM_EVENT_COUNTERS is not set
# CONFIG_COMPAT_BRK is not set
CONFIG_SLAB=y
CONFIG_MACH_INGENIC_SOC=y
CONFIG_JZ4780_CI20=y
CONFIG_HIGHMEM=y
CONFIG_HZ_100=y
# CONFIG_SECCOMP is not set
# CONFIG_SUSPEND is not set
# CONFIG_SECCOMP is not set
CONFIG_MODULES=y
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
CONFIG_SLAB=y
# CONFIG_COMPAT_BRK is not set
# CONFIG_COMPACTION is not set
CONFIG_CMA=y
# CONFIG_VM_EVENT_COUNTERS is not set
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
@ -40,7 +40,12 @@ CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
# CONFIG_INET_DIAG is not set
# CONFIG_IPV6 is not set
# CONFIG_WIRELESS is not set
CONFIG_BT=m
# CONFIG_BT_LE is not set
CONFIG_BT_HCIUART=m
CONFIG_BT_HCIUART_BCM=y
CONFIG_CFG80211=m
CONFIG_CFG80211_WEXT=y
CONFIG_DEVTMPFS=y
CONFIG_FW_LOADER=m
# CONFIG_ALLOW_DEV_COREDUMP is not set
@ -68,10 +73,27 @@ CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL=y
# CONFIG_NET_VENDOR_STMICRO is not set
# CONFIG_NET_VENDOR_VIA is not set
# CONFIG_NET_VENDOR_WIZNET is not set
# CONFIG_WLAN is not set
# CONFIG_WLAN_VENDOR_ADMTEK is not set
# CONFIG_WLAN_VENDOR_ATH is not set
# CONFIG_WLAN_VENDOR_ATMEL is not set
CONFIG_BRCMFMAC=m
# CONFIG_WLAN_VENDOR_CISCO is not set
# CONFIG_WLAN_VENDOR_INTEL is not set
# CONFIG_WLAN_VENDOR_INTERSIL is not set
# CONFIG_WLAN_VENDOR_MARVELL is not set
# CONFIG_WLAN_VENDOR_MEDIATEK is not set
# CONFIG_WLAN_VENDOR_MICROCHIP is not set
# CONFIG_WLAN_VENDOR_PURELIFI is not set
# CONFIG_WLAN_VENDOR_RALINK is not set
# CONFIG_WLAN_VENDOR_REALTEK is not set
# CONFIG_WLAN_VENDOR_RSI is not set
# CONFIG_WLAN_VENDOR_SILABS is not set
# CONFIG_WLAN_VENDOR_ST is not set
# CONFIG_WLAN_VENDOR_TI is not set
# CONFIG_WLAN_VENDOR_ZYDAS is not set
# CONFIG_WLAN_VENDOR_QUANTENNA is not set
CONFIG_KEYBOARD_GPIO=m
# CONFIG_INPUT_MOUSE is not set
CONFIG_VT_HW_CONSOLE_BINDING=y
CONFIG_LEGACY_PTY_COUNT=2
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
@ -79,6 +101,7 @@ CONFIG_SERIAL_8250_NR_UARTS=5
CONFIG_SERIAL_8250_RUNTIME_UARTS=5
CONFIG_SERIAL_8250_INGENIC=y
CONFIG_SERIAL_OF_PLATFORM=y
CONFIG_SERIAL_DEV_BUS=y
CONFIG_I2C=y
CONFIG_I2C_JZ4780=y
CONFIG_SPI=y
@ -99,13 +122,12 @@ CONFIG_IR_GPIO_CIR=m
CONFIG_IR_GPIO_TX=m
CONFIG_MEDIA_SUPPORT=m
CONFIG_DRM=m
CONFIG_DRM_DISPLAY_CONNECTOR=m
CONFIG_DRM_INGENIC=m
CONFIG_DRM_INGENIC_DW_HDMI=m
CONFIG_DRM_DISPLAY_CONNECTOR=m
# CONFIG_VGA_CONSOLE is not set
CONFIG_FB=y
# CONFIG_VGA_CONSOLE is not set
CONFIG_FRAMEBUFFER_CONSOLE=y
# CONFIG_HID is not set
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_DWC2=y
@ -125,7 +147,6 @@ CONFIG_LEDS_TRIGGER_HEARTBEAT=y
CONFIG_LEDS_TRIGGER_BACKLIGHT=m
CONFIG_LEDS_TRIGGER_CPU=y
CONFIG_LEDS_TRIGGER_ACTIVITY=y
CONFIG_LEDS_TRIGGER_GPIO=y
CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
CONFIG_LEDS_TRIGGER_TRANSIENT=y
CONFIG_LEDS_TRIGGER_CAMERA=m
@ -144,7 +165,6 @@ CONFIG_JZ4780_NEMC=y
CONFIG_PWM=y
CONFIG_PWM_JZ4740=m
CONFIG_NVMEM_JZ4780_EFUSE=y
CONFIG_JZ4770_PHY=y
CONFIG_EXT4_FS=y
# CONFIG_DNOTIFY is not set
CONFIG_AUTOFS_FS=y
@ -157,7 +177,6 @@ CONFIG_CONFIGFS_FS=y
CONFIG_UBIFS_FS=y
CONFIG_NFS_FS=y
CONFIG_ROOT_NFS=y
CONFIG_NLS=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_CODEPAGE_737=y
CONFIG_NLS_CODEPAGE_775=y
@ -196,6 +215,7 @@ CONFIG_NLS_ISO8859_15=y
CONFIG_NLS_KOI8_R=y
CONFIG_NLS_KOI8_U=y
CONFIG_NLS_UTF8=y
# CONFIG_CRYPTO_AES is not set
CONFIG_DMA_CMA=y
CONFIG_CMA_SIZE_MBYTES=32
CONFIG_PRINTK_TIME=y
@ -206,7 +226,6 @@ CONFIG_DEBUG_FS=y
CONFIG_PANIC_ON_OOPS=y
CONFIG_PANIC_TIMEOUT=10
# CONFIG_SCHED_DEBUG is not set
# CONFIG_DEBUG_PREEMPT is not set
CONFIG_STACKTRACE=y
# CONFIG_FTRACE is not set
CONFIG_CMDLINE_BOOL=y

7
arch/mips/configs/loongson3_defconfig
View File

@ -276,6 +276,13 @@ CONFIG_MEDIA_SUPPORT=m
CONFIG_MEDIA_USB_SUPPORT=y
CONFIG_USB_VIDEO_CLASS=m
CONFIG_DRM=y
CONFIG_DRM_AMDGPU=m
CONFIG_DRM_AMDGPU_SI=y
CONFIG_DRM_AMDGPU_CIK=y
CONFIG_DRM_AMDGPU_USERPTR=y
CONFIG_DRM_AMD_ACP=y
CONFIG_DRM_AMD_DC=y
CONFIG_DRM_AMD_DC_SI=y
CONFIG_DRM_RADEON=m
CONFIG_DRM_QXL=y
CONFIG_DRM_VIRTIO_GPU=y

61
arch/mips/generic/board-ingenic.c
View File

@ -17,6 +17,7 @@
#include <linux/types.h>
#include <asm/bootinfo.h>
#include <asm/io.h>
#include <asm/machine.h>
#include <asm/reboot.h>
@ -60,6 +61,50 @@ static __init char *ingenic_get_system_type(unsigned long machtype)
}
}
#define INGENIC_CGU_BASE 0x10000000
#define JZ4750_CGU_CPCCR_ECS BIT(30)
#define JZ4760_CGU_CPCCR_ECS BIT(31)
static __init void ingenic_force_12M_ext(const void *fdt, unsigned int mask)
{
const __be32 *prop;
unsigned int cpccr;
void __iomem *cgu;
bool use_div;
int offset;
offset = fdt_path_offset(fdt, "/ext");
if (offset < 0)
return;
prop = fdt_getprop(fdt, offset, "clock-frequency", NULL);
if (!prop)
return;
/*
* If the external oscillator is 24 MHz, enable the /2 divider to
* drive it down to 12 MHz, since this is what the hardware can work
* with.
* The 16 MHz cutoff value is arbitrary; setting it to 12 MHz would not
* work as the crystal frequency (as reported in the Device Tree) might
* be slightly above this value.
*/
use_div = be32_to_cpup(prop) >= 16000000;
cgu = ioremap(INGENIC_CGU_BASE, 0x4);
if (!cgu)
return;
cpccr = ioread32(cgu);
if (use_div)
cpccr |= mask;
else
cpccr &= ~mask;
iowrite32(cpccr, cgu);
iounmap(cgu);
}
static __init const void *ingenic_fixup_fdt(const void *fdt, const void *match_data)
{
/*
@ -73,6 +118,18 @@ static __init const void *ingenic_fixup_fdt(const void *fdt, const void *match_d
mips_machtype = (unsigned long)match_data;
system_type = ingenic_get_system_type(mips_machtype);
switch (mips_machtype) {
case MACH_INGENIC_JZ4750:
case MACH_INGENIC_JZ4755:
ingenic_force_12M_ext(fdt, JZ4750_CGU_CPCCR_ECS);
break;
case MACH_INGENIC_JZ4760:
ingenic_force_12M_ext(fdt, JZ4760_CGU_CPCCR_ECS);
break;
default:
break;
}
return fdt;
}
@ -117,14 +174,14 @@ static void ingenic_halt(void)
ingenic_wait_instr();
}
static int __maybe_unused ingenic_pm_enter(suspend_state_t state)
static int ingenic_pm_enter(suspend_state_t state)
{
ingenic_wait_instr();
return 0;
}
static const struct platform_suspend_ops ingenic_pm_ops __maybe_unused = {
static const struct platform_suspend_ops ingenic_pm_ops = {
.valid = suspend_valid_only_mem,
.enter = ingenic_pm_enter,
};

4
arch/mips/include/asm/cpu-features.h
View File

@ -125,7 +125,7 @@
({ \
int __res; \
\
switch (current_cpu_type()) { \
switch (boot_cpu_type()) { \
case CPU_CAVIUM_OCTEON: \
case CPU_CAVIUM_OCTEON_PLUS: \
case CPU_CAVIUM_OCTEON2: \
@ -368,7 +368,7 @@
({ \
int __res; \
\
switch (current_cpu_type()) { \
switch (boot_cpu_type()) { \
case CPU_M14KC: \
case CPU_74K: \
case CPU_1074K: \

2
arch/mips/include/asm/dec/prom.h
View File

@ -70,7 +70,7 @@ static inline bool prom_is_rex(u32 magic)
*/
typedef struct {
int pagesize;
unsigned char bitmap[0];
unsigned char bitmap[];
} memmap;

1
arch/mips/include/asm/io.h
View File

@ -554,6 +554,7 @@ extern void (*_dma_cache_inv)(unsigned long start, unsigned long size);
* access
*/
#define xlate_dev_mem_ptr(p) __va(p)
#define unxlate_dev_mem_ptr(p, v) do { } while (0)
void __ioread64_copy(void *to, const void __iomem *from, size_t count);

1
arch/mips/include/asm/mach-loongson32/loongson1.h
View File

@ -48,6 +48,5 @@
#include <regs-clk.h>
#include <regs-mux.h>
#include <regs-rtc.h>
#include <regs-wdt.h>
#endif /* __ASM_MACH_LOONGSON32_LOONGSON1_H */

15
arch/mips/include/asm/mach-loongson32/regs-wdt.h
View File

@ -1,15 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
*
* Loongson 1 Watchdog Register Definitions.
*/
#ifndef __ASM_MACH_LOONGSON32_REGS_WDT_H
#define __ASM_MACH_LOONGSON32_REGS_WDT_H
#define WDT_EN 0x0
#define WDT_TIMER 0x4
#define WDT_SET 0x8
#endif /* __ASM_MACH_LOONGSON32_REGS_WDT_H */

35
arch/mips/include/asm/mach-ralink/mt7620.h
View File

@ -20,52 +20,17 @@
#define SYSC_REG_CHIP_REV 0x0c
#define SYSC_REG_SYSTEM_CONFIG0 0x10
#define SYSC_REG_SYSTEM_CONFIG1 0x14
#define SYSC_REG_CLKCFG0 0x2c
#define SYSC_REG_CPU_SYS_CLKCFG 0x3c
#define SYSC_REG_CPLL_CONFIG0 0x54
#define SYSC_REG_CPLL_CONFIG1 0x58
#define MT7620_CHIP_NAME0 0x3637544d
#define MT7620_CHIP_NAME1 0x20203032
#define MT7628_CHIP_NAME1 0x20203832
#define SYSCFG0_XTAL_FREQ_SEL BIT(6)
#define CHIP_REV_PKG_MASK 0x1
#define CHIP_REV_PKG_SHIFT 16
#define CHIP_REV_VER_MASK 0xf
#define CHIP_REV_VER_SHIFT 8
#define CHIP_REV_ECO_MASK 0xf
#define CLKCFG0_PERI_CLK_SEL BIT(4)
#define CPU_SYS_CLKCFG_OCP_RATIO_SHIFT 16
#define CPU_SYS_CLKCFG_OCP_RATIO_MASK 0xf
#define CPU_SYS_CLKCFG_OCP_RATIO_1 0 /* 1:1 (Reserved) */
#define CPU_SYS_CLKCFG_OCP_RATIO_1_5 1 /* 1:1.5 (Reserved) */
#define CPU_SYS_CLKCFG_OCP_RATIO_2 2 /* 1:2 */
#define CPU_SYS_CLKCFG_OCP_RATIO_2_5 3 /* 1:2.5 (Reserved) */
#define CPU_SYS_CLKCFG_OCP_RATIO_3 4 /* 1:3 */
#define CPU_SYS_CLKCFG_OCP_RATIO_3_5 5 /* 1:3.5 (Reserved) */
#define CPU_SYS_CLKCFG_OCP_RATIO_4 6 /* 1:4 */
#define CPU_SYS_CLKCFG_OCP_RATIO_5 7 /* 1:5 */
#define CPU_SYS_CLKCFG_OCP_RATIO_10 8 /* 1:10 */
#define CPU_SYS_CLKCFG_CPU_FDIV_SHIFT 8
#define CPU_SYS_CLKCFG_CPU_FDIV_MASK 0x1f
#define CPU_SYS_CLKCFG_CPU_FFRAC_SHIFT 0
#define CPU_SYS_CLKCFG_CPU_FFRAC_MASK 0x1f
#define CPLL_CFG0_SW_CFG BIT(31)
#define CPLL_CFG0_PLL_MULT_RATIO_SHIFT 16
#define CPLL_CFG0_PLL_MULT_RATIO_MASK 0x7
#define CPLL_CFG0_LC_CURFCK BIT(15)
#define CPLL_CFG0_BYPASS_REF_CLK BIT(14)
#define CPLL_CFG0_PLL_DIV_RATIO_SHIFT 10
#define CPLL_CFG0_PLL_DIV_RATIO_MASK 0x3
#define CPLL_CFG1_CPU_AUX1 BIT(25)
#define CPLL_CFG1_CPU_AUX0 BIT(24)
#define SYSCFG0_DRAM_TYPE_MASK 0x3
#define SYSCFG0_DRAM_TYPE_SHIFT 4
#define SYSCFG0_DRAM_TYPE_SDRAM 0

10
arch/mips/include/asm/mach-ralink/rt288x.h
View File

@ -18,7 +18,6 @@
#define SYSC_REG_CHIP_NAME1 0x04
#define SYSC_REG_CHIP_ID 0x0c
#define SYSC_REG_SYSTEM_CONFIG 0x10
#define SYSC_REG_CLKCFG 0x30
#define RT2880_CHIP_NAME0 0x38325452
#define RT2880_CHIP_NAME1 0x20203038
@ -27,15 +26,6 @@
#define CHIP_ID_ID_SHIFT 8
#define CHIP_ID_REV_MASK 0xff
#define SYSTEM_CONFIG_CPUCLK_SHIFT 20
#define SYSTEM_CONFIG_CPUCLK_MASK 0x3
#define SYSTEM_CONFIG_CPUCLK_250 0x0
#define SYSTEM_CONFIG_CPUCLK_266 0x1
#define SYSTEM_CONFIG_CPUCLK_280 0x2
#define SYSTEM_CONFIG_CPUCLK_300 0x3
#define CLKCFG_SRAM_CS_N_WDT BIT(9)
#define RT2880_SDRAM_BASE 0x08000000
#define RT2880_MEM_SIZE_MIN 2
#define RT2880_MEM_SIZE_MAX 128

21
arch/mips/include/asm/mach-ralink/rt305x.h
View File

@ -67,26 +67,9 @@ static inline int soc_is_rt5350(void)
#define CHIP_ID_ID_SHIFT 8
#define CHIP_ID_REV_MASK 0xff
#define RT305X_SYSCFG_CPUCLK_SHIFT 18
#define RT305X_SYSCFG_CPUCLK_MASK 0x1
#define RT305X_SYSCFG_CPUCLK_LOW 0x0
#define RT305X_SYSCFG_CPUCLK_HIGH 0x1
#define RT305X_SYSCFG_SRAM_CS0_MODE_SHIFT 2
#define RT305X_SYSCFG_CPUCLK_MASK 0x1
#define RT305X_SYSCFG_SRAM_CS0_MODE_WDT 0x1
#define RT3352_SYSCFG0_CPUCLK_SHIFT 8
#define RT3352_SYSCFG0_CPUCLK_MASK 0x1
#define RT3352_SYSCFG0_CPUCLK_LOW 0x0
#define RT3352_SYSCFG0_CPUCLK_HIGH 0x1
#define RT5350_SYSCFG0_CPUCLK_SHIFT 8
#define RT5350_SYSCFG0_CPUCLK_MASK 0x3
#define RT5350_SYSCFG0_CPUCLK_360 0x0
#define RT5350_SYSCFG0_CPUCLK_320 0x2
#define RT5350_SYSCFG0_CPUCLK_300 0x3
#define RT5350_SYSCFG0_DRAM_SIZE_SHIFT 12
#define RT5350_SYSCFG0_DRAM_SIZE_MASK 7
#define RT5350_SYSCFG0_DRAM_SIZE_2M 0
@ -117,13 +100,9 @@ static inline int soc_is_rt5350(void)
#define RT3352_SYSC_REG_SYSCFG0 0x010
#define RT3352_SYSC_REG_SYSCFG1 0x014
#define RT3352_SYSC_REG_CLKCFG1 0x030
#define RT3352_SYSC_REG_RSTCTRL 0x034
#define RT3352_SYSC_REG_USB_PS 0x05c
#define RT3352_CLKCFG0_XTAL_SEL BIT(20)
#define RT3352_CLKCFG1_UPHY0_CLK_EN BIT(18)
#define RT3352_CLKCFG1_UPHY1_CLK_EN BIT(20)
#define RT3352_RSTCTRL_UHST BIT(22)
#define RT3352_RSTCTRL_UDEV BIT(25)
#define RT3352_SYSCFG1_USB0_HOST_MODE BIT(10)

8
arch/mips/include/asm/mach-ralink/rt3883.h
View File

@ -92,14 +92,6 @@
#define RT3883_REVID_VER_ID_SHIFT 8
#define RT3883_REVID_ECO_ID_MASK 0x0f
#define RT3883_SYSCFG0_DRAM_TYPE_DDR2 BIT(17)
#define RT3883_SYSCFG0_CPUCLK_SHIFT 8
#define RT3883_SYSCFG0_CPUCLK_MASK 0x3
#define RT3883_SYSCFG0_CPUCLK_250 0x0
#define RT3883_SYSCFG0_CPUCLK_384 0x1
#define RT3883_SYSCFG0_CPUCLK_480 0x2
#define RT3883_SYSCFG0_CPUCLK_500 0x3
#define RT3883_SYSCFG1_USB0_HOST_MODE BIT(10)
#define RT3883_SYSCFG1_PCIE_RC_MODE BIT(8)
#define RT3883_SYSCFG1_PCI_HOST_MODE BIT(7)

2
arch/mips/include/asm/smp.h
View File

@ -57,6 +57,8 @@ extern int __cpu_logical_map[NR_CPUS];
/* Mask of CPUs which are currently definitely operating coherently */
extern cpumask_t cpu_coherent_mask;
extern unsigned int smp_max_threads __initdata;
extern asmlinkage void smp_bootstrap(void);
extern void calculate_cpu_foreign_map(void);

33
arch/mips/include/uapi/asm/inst.h
View File

@ -272,6 +272,27 @@ enum lx_func {
lbx_op = 0x16,
};
/*
* func field for special2 MXU opcodes (Ingenic XBurst MXU).
*/
enum mxu_func {
/* TODO, other MXU funcs */
mxu_lx_op = 0x28,
};
/*
* op field for special2 MXU LX opcodes (Ingenic XBurst MXU).
*/
enum lx_ingenic_func {
mxu_lxb_op,
mxu_lxh_op,
/* reserved */
mxu_lxw_op = 3,
mxu_lxbu_op,
mxu_lxhu_op,
/* more reserved */
};
/*
* BSHFL opcodes
*/
@ -774,6 +795,17 @@ struct dsp_format { /* SPEC3 DSP format instructions */
;))))))
};
struct mxu_lx_format { /* SPEC2 MXU LX format instructions */
__BITFIELD_FIELD(unsigned int opcode : 6,
__BITFIELD_FIELD(unsigned int rs : 5,
__BITFIELD_FIELD(unsigned int rt : 5,
__BITFIELD_FIELD(unsigned int rd : 5,
__BITFIELD_FIELD(unsigned int strd : 2,
__BITFIELD_FIELD(unsigned int op : 3,
__BITFIELD_FIELD(unsigned int func : 6,
;)))))))
};
struct spec3_format { /* SPEC3 */
__BITFIELD_FIELD(unsigned int opcode:6,
__BITFIELD_FIELD(unsigned int rs:5,
@ -1125,6 +1157,7 @@ union mips_instruction {
struct loongson3_lswc2_format loongson3_lswc2_format;
struct loongson3_lsdc2_format loongson3_lsdc2_format;
struct loongson3_lscsr_format loongson3_lscsr_format;
struct mxu_lx_format mxu_lx_format;
};
union mips16e_instruction {

14
arch/mips/kernel/asm-offsets.c
View File

@ -23,6 +23,7 @@
#include <linux/kvm_host.h>
void output_ptreg_defines(void);
void output_ptreg_defines(void)
{
COMMENT("MIPS pt_regs offsets.");
@ -75,6 +76,7 @@ void output_ptreg_defines(void)
BLANK();
}
void output_task_defines(void);
void output_task_defines(void)
{
COMMENT("MIPS task_struct offsets.");
@ -89,6 +91,7 @@ void output_task_defines(void)
BLANK();
}
void output_thread_info_defines(void);
void output_thread_info_defines(void)
{
COMMENT("MIPS thread_info offsets.");
@ -105,6 +108,7 @@ void output_thread_info_defines(void)
BLANK();
}
void output_thread_defines(void);
void output_thread_defines(void)
{
COMMENT("MIPS specific thread_struct offsets.");
@ -133,6 +137,7 @@ void output_thread_defines(void)
}
#ifdef CONFIG_MIPS_FP_SUPPORT
void output_thread_fpu_defines(void);
void output_thread_fpu_defines(void)
{
OFFSET(THREAD_FPU, task_struct, thread.fpu);
@ -176,6 +181,7 @@ void output_thread_fpu_defines(void)
}
#endif
void output_mm_defines(void);
void output_mm_defines(void)
{
COMMENT("Size of struct page");
@ -210,6 +216,7 @@ void output_mm_defines(void)
}
#ifdef CONFIG_32BIT
void output_sc_defines(void);
void output_sc_defines(void)
{
COMMENT("Linux sigcontext offsets.");
@ -232,6 +239,7 @@ void output_sc_defines(void)
#endif
#ifdef CONFIG_64BIT
void output_sc_defines(void);
void output_sc_defines(void)
{
COMMENT("Linux sigcontext offsets.");
@ -245,6 +253,7 @@ void output_sc_defines(void)
}
#endif
void output_signal_defined(void);
void output_signal_defined(void)
{
COMMENT("Linux signal numbers.");
@ -284,6 +293,7 @@ void output_signal_defined(void)
}
#ifdef CONFIG_CPU_CAVIUM_OCTEON
void output_octeon_cop2_state_defines(void);
void output_octeon_cop2_state_defines(void)
{
COMMENT("Octeon specific octeon_cop2_state offsets.");
@ -315,6 +325,7 @@ void output_octeon_cop2_state_defines(void)
#endif
#ifdef CONFIG_HIBERNATION
void output_pbe_defines(void);
void output_pbe_defines(void)
{
COMMENT(" Linux struct pbe offsets. ");
@ -327,6 +338,7 @@ void output_pbe_defines(void)
#endif
#ifdef CONFIG_CPU_PM
void output_pm_defines(void);
void output_pm_defines(void)
{
COMMENT(" PM offsets. ");
@ -341,6 +353,7 @@ void output_pm_defines(void)
#endif
#ifdef CONFIG_MIPS_FP_SUPPORT
void output_kvm_defines(void);
void output_kvm_defines(void)
{
COMMENT(" KVM/MIPS Specific offsets. ");
@ -385,6 +398,7 @@ void output_kvm_defines(void)
#endif
#ifdef CONFIG_MIPS_CPS
void output_cps_defines(void);
void output_cps_defines(void)
{
COMMENT(" MIPS CPS offsets. ");

15
arch/mips/kernel/smp-cps.c
View File

@ -25,24 +25,13 @@
#include <asm/time.h>
#include <asm/uasm.h>
static bool threads_disabled;
static DECLARE_BITMAP(core_power, NR_CPUS);
struct core_boot_config *mips_cps_core_bootcfg;
static int __init setup_nothreads(char *s)
static unsigned __init core_vpe_count(unsigned int cluster, unsigned core)
{
threads_disabled = true;
return 0;
}
early_param("nothreads", setup_nothreads);
static unsigned core_vpe_count(unsigned int cluster, unsigned core)
{
if (threads_disabled)
return 1;
return mips_cps_numvps(cluster, core);
return min(smp_max_threads, mips_cps_numvps(cluster, core));
}
static void __init cps_smp_setup(void)

3
arch/mips/kernel/smp-mt.c
View File

@ -46,7 +46,8 @@ static void __init smvp_copy_vpe_config(void)
static unsigned int __init smvp_vpe_init(unsigned int tc, unsigned int mvpconf0,
unsigned int ncpu)
{
if (tc > ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT))
if (tc >= smp_max_threads ||
(tc > ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT)))
return ncpu;
/* Deactivate all but VPE 0 */

18
arch/mips/kernel/smp.c
View File

@ -73,6 +73,24 @@ static cpumask_t cpu_core_setup_map;
cpumask_t cpu_coherent_mask;
unsigned int smp_max_threads __initdata = UINT_MAX;
static int __init early_nosmt(char *s)
{
smp_max_threads = 1;
return 0;
}
early_param("nosmt", early_nosmt);
static int __init early_smt(char *s)
{
get_option(&s, &smp_max_threads);
/* Ensure at least one thread is available */
smp_max_threads = clamp_val(smp_max_threads, 1U, UINT_MAX);
return 0;
}
early_param("smt", early_smt);
#ifdef CONFIG_GENERIC_IRQ_IPI
static struct irq_desc *call_desc;
static struct irq_desc *sched_desc;

41
arch/mips/kernel/unaligned.c
View File

@ -160,6 +160,47 @@ static void emulate_load_store_insn(struct pt_regs *regs,
* The remaining opcodes are the ones that are really of
* interest.
*/
#ifdef CONFIG_MACH_INGENIC
case spec2_op:
if (insn.mxu_lx_format.func != mxu_lx_op)
goto sigbus; /* other MXU instructions we don't care */
switch (insn.mxu_lx_format.op) {
case mxu_lxw_op:
if (user && !access_ok(addr, 4))
goto sigbus;
LoadW(addr, value, res);
if (res)
goto fault;
compute_return_epc(regs);
regs->regs[insn.mxu_lx_format.rd] = value;
break;
case mxu_lxh_op:
if (user && !access_ok(addr, 2))
goto sigbus;
LoadHW(addr, value, res);
if (res)
goto fault;
compute_return_epc(regs);
regs->regs[insn.dsp_format.rd] = value;
break;
case mxu_lxhu_op:
if (user && !access_ok(addr, 2))
goto sigbus;
LoadHWU(addr, value, res);
if (res)
goto fault;
compute_return_epc(regs);
regs->regs[insn.dsp_format.rd] = value;
break;
case mxu_lxb_op:
case mxu_lxbu_op:
goto sigbus;
default:
goto sigill;
}
break;
#endif
case spec3_op:
if (insn.dsp_format.func == lx_op) {
switch (insn.dsp_format.op) {

2
arch/mips/loongson32/common/Makefile
View File

@ -3,4 +3,4 @@
# Makefile for common code of loongson1 based machines.
#
obj-y += time.o irq.o platform.o prom.o reset.o setup.o
obj-y += time.o irq.o platform.o prom.o setup.o

51
arch/mips/loongson32/common/reset.c
View File

@ -1,51 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
*/
#include <linux/io.h>
#include <linux/pm.h>
#include <linux/sizes.h>
#include <asm/idle.h>
#include <asm/reboot.h>
#include <loongson1.h>
static void __iomem *wdt_reg_base;
static void ls1x_halt(void)
{
while (1) {
if (cpu_wait)
cpu_wait();
}
}
static void ls1x_restart(char *command)
{
__raw_writel(0x1, wdt_reg_base + WDT_EN);
__raw_writel(0x1, wdt_reg_base + WDT_TIMER);
__raw_writel(0x1, wdt_reg_base + WDT_SET);
ls1x_halt();
}
static void ls1x_power_off(void)
{
ls1x_halt();
}
static int __init ls1x_reboot_setup(void)
{
wdt_reg_base = ioremap(LS1X_WDT_BASE, (SZ_4 + SZ_8));
if (!wdt_reg_base)
panic("Failed to remap watchdog registers");
_machine_restart = ls1x_restart;
_machine_halt = ls1x_halt;
pm_power_off = ls1x_power_off;
return 0;
}
arch_initcall(ls1x_reboot_setup);

24
arch/mips/mm/tlbex.c
View File

@ -2123,16 +2123,8 @@ static void build_r4000_tlb_load_handler(void)
uasm_i_tlbr(&p);
switch (current_cpu_type()) {
case CPU_CAVIUM_OCTEON:
case CPU_CAVIUM_OCTEON_PLUS:
case CPU_CAVIUM_OCTEON2:
break;
default:
if (cpu_has_mips_r2_exec_hazard)
uasm_i_ehb(&p);
break;
}
if (cpu_has_mips_r2_exec_hazard)
uasm_i_ehb(&p);
/* Examine entrylo 0 or 1 based on ptr. */
if (use_bbit_insns()) {
@ -2197,16 +2189,8 @@ static void build_r4000_tlb_load_handler(void)
uasm_i_tlbr(&p);
switch (current_cpu_type()) {
case CPU_CAVIUM_OCTEON:
case CPU_CAVIUM_OCTEON_PLUS:
case CPU_CAVIUM_OCTEON2:
break;
default:
if (cpu_has_mips_r2_exec_hazard)
uasm_i_ehb(&p);
break;
}
if (cpu_has_mips_r2_exec_hazard)
uasm_i_ehb(&p);
/* Examine entrylo 0 or 1 based on ptr. */
if (use_bbit_insns()) {

7
arch/mips/pci/pci-mt7620.c
View File

@ -274,9 +274,6 @@ static int mt7628_pci_hw_init(struct platform_device *pdev)
val |= 0x50 << 8;
pci_config_write(NULL, 0, 0x70c, 4, val);
pci_config_read(NULL, 0, 0x70c, 4, &val);
dev_err(&pdev->dev, "Port 0 N_FTS = %x\n", (unsigned int) val);
return 0;
}
@ -330,7 +327,7 @@ static int mt7620_pci_probe(struct platform_device *pdev)
rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
if (ralink_soc == MT762X_SOC_MT7620A)
rt_sysc_m32(LC_CKDRVPD, PDRV_SW_SET, PPLL_DRV);
dev_err(&pdev->dev, "PCIE0 no card, disable it(RST&CLK)\n");
dev_info(&pdev->dev, "PCIE0 no card, disable it(RST&CLK)\n");
return -1;
}
@ -373,7 +370,7 @@ int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
dev->bus->number, slot);
return 0;
}
dev_err(&dev->dev, "card - bus=0x%x, slot = 0x%x irq=%d\n",
dev_info(&dev->dev, "card - bus=0x%x, slot = 0x%x irq=%d\n",
dev->bus->number, slot, irq);
/* configure the cache line size to 0x14 */

8
arch/mips/pci/pci-xtalk-bridge.c
View File

@ -733,7 +733,7 @@ err_remove_domain:
return err;
}
static int bridge_remove(struct platform_device *pdev)
static void bridge_remove(struct platform_device *pdev)
{
struct pci_bus *bus = platform_get_drvdata(pdev);
struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
@ -745,13 +745,11 @@ static int bridge_remove(struct platform_device *pdev)
pci_stop_root_bus(bus);
pci_remove_root_bus(bus);
pci_unlock_rescan_remove();
return 0;
}
static struct platform_driver bridge_driver = {
.probe = bridge_probe,
.remove = bridge_remove,
.probe = bridge_probe,
.remove_new = bridge_remove,
.driver = {
.name = "xtalk-bridge",
}

61
arch/mips/ralink/clk.c
View File

@ -11,29 +11,72 @@
#include <linux/clkdev.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <asm/mach-ralink/ralink_regs.h>
#include <asm/time.h>
#include "common.h"
void ralink_clk_add(const char *dev, unsigned long rate)
static const char *clk_cpu(int *idx)
{
struct clk *clk = clk_register_fixed_rate(NULL, dev, NULL, 0, rate);
if (!clk)
panic("failed to add clock");
clkdev_create(clk, NULL, "%s", dev);
switch (ralink_soc) {
case RT2880_SOC:
*idx = 0;
return "ralink,rt2880-sysc";
case RT3883_SOC:
*idx = 0;
return "ralink,rt3883-sysc";
case RT305X_SOC_RT3050:
*idx = 0;
return "ralink,rt3050-sysc";
case RT305X_SOC_RT3052:
*idx = 0;
return "ralink,rt3052-sysc";
case RT305X_SOC_RT3350:
*idx = 1;
return "ralink,rt3350-sysc";
case RT305X_SOC_RT3352:
*idx = 1;
return "ralink,rt3352-sysc";
case RT305X_SOC_RT5350:
*idx = 1;
return "ralink,rt5350-sysc";
case MT762X_SOC_MT7620A:
*idx = 2;
return "ralink,mt7620-sysc";
case MT762X_SOC_MT7620N:
*idx = 2;
return "ralink,mt7620-sysc";
case MT762X_SOC_MT7628AN:
*idx = 1;
return "ralink,mt7628-sysc";
case MT762X_SOC_MT7688:
*idx = 1;
return "ralink,mt7688-sysc";
default:
*idx = -1;
return "invalid";
}
}
void __init plat_time_init(void)
{
struct of_phandle_args clkspec;
const char *compatible;
struct clk *clk;
int cpu_clk_idx;
ralink_of_remap();
ralink_clk_init();
clk = clk_get_sys("cpu", NULL);
compatible = clk_cpu(&cpu_clk_idx);
if (cpu_clk_idx == -1)
panic("unable to get CPU clock index");
of_clk_init(NULL);
clkspec.np = of_find_compatible_node(NULL, NULL, compatible);
clkspec.args_count = 1;
clkspec.args[0] = cpu_clk_idx;
clk = of_clk_get_from_provider(&clkspec);
if (IS_ERR(clk))
panic("unable to get CPU clock, err=%ld", PTR_ERR(clk));
pr_info("CPU Clock: %ldMHz\n", clk_get_rate(clk) / 1000000);

7
arch/mips/ralink/common.h
View File

@ -23,13 +23,6 @@ extern struct ralink_soc_info soc_info;
extern void ralink_of_remap(void);
extern void ralink_clk_init(void);
extern void ralink_clk_add(const char *dev, unsigned long rate);
extern void ralink_rst_init(void);
extern void __init prom_soc_init(struct ralink_soc_info *soc_info);
__iomem void *plat_of_remap_node(const char *node);
#endif /* _RALINK_COMMON_H__ */

235
arch/mips/ralink/mt7620.c
View File

@ -36,12 +36,6 @@
#define PMU1_CFG 0x8C
#define DIG_SW_SEL BIT(25)
/* clock scaling */
#define CLKCFG_FDIV_MASK 0x1f00
#define CLKCFG_FDIV_USB_VAL 0x0300
#define CLKCFG_FFRAC_MASK 0x001f
#define CLKCFG_FFRAC_USB_VAL 0x0003
/* EFUSE bits */
#define EFUSE_MT7688 0x100000
@ -53,235 +47,6 @@ static int dram_type;
static struct ralink_soc_info *soc_info_ptr;
static __init u32
mt7620_calc_rate(u32 ref_rate, u32 mul, u32 div)
{
u64 t;
t = ref_rate;
t *= mul;
do_div(t, div);
return t;
}
#define MHZ(x) ((x) * 1000 * 1000)
static __init unsigned long
mt7620_get_xtal_rate(void)
{
u32 reg;
reg = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0);
if (reg & SYSCFG0_XTAL_FREQ_SEL)
return MHZ(40);
return MHZ(20);
}
static __init unsigned long
mt7620_get_periph_rate(unsigned long xtal_rate)
{
u32 reg;
reg = rt_sysc_r32(SYSC_REG_CLKCFG0);
if (reg & CLKCFG0_PERI_CLK_SEL)
return xtal_rate;
return MHZ(40);
}
static const u32 mt7620_clk_divider[] __initconst = { 2, 3, 4, 8 };
static __init unsigned long
mt7620_get_cpu_pll_rate(unsigned long xtal_rate)
{
u32 reg;
u32 mul;
u32 div;
reg = rt_sysc_r32(SYSC_REG_CPLL_CONFIG0);
if (reg & CPLL_CFG0_BYPASS_REF_CLK)
return xtal_rate;
if ((reg & CPLL_CFG0_SW_CFG) == 0)
return MHZ(600);
mul = (reg >> CPLL_CFG0_PLL_MULT_RATIO_SHIFT) &
CPLL_CFG0_PLL_MULT_RATIO_MASK;
mul += 24;
if (reg & CPLL_CFG0_LC_CURFCK)
mul *= 2;
div = (reg >> CPLL_CFG0_PLL_DIV_RATIO_SHIFT) &
CPLL_CFG0_PLL_DIV_RATIO_MASK;
WARN_ON(div >= ARRAY_SIZE(mt7620_clk_divider));
return mt7620_calc_rate(xtal_rate, mul, mt7620_clk_divider[div]);
}
static __init unsigned long
mt7620_get_pll_rate(unsigned long xtal_rate, unsigned long cpu_pll_rate)
{
u32 reg;
reg = rt_sysc_r32(SYSC_REG_CPLL_CONFIG1);
if (reg & CPLL_CFG1_CPU_AUX1)
return xtal_rate;
if (reg & CPLL_CFG1_CPU_AUX0)
return MHZ(480);
return cpu_pll_rate;
}
static __init unsigned long
mt7620_get_cpu_rate(unsigned long pll_rate)
{
u32 reg;
u32 mul;
u32 div;
reg = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG);
mul = reg & CPU_SYS_CLKCFG_CPU_FFRAC_MASK;
div = (reg >> CPU_SYS_CLKCFG_CPU_FDIV_SHIFT) &
CPU_SYS_CLKCFG_CPU_FDIV_MASK;
return mt7620_calc_rate(pll_rate, mul, div);
}
static const u32 mt7620_ocp_dividers[16] __initconst = {
[CPU_SYS_CLKCFG_OCP_RATIO_2] = 2,
[CPU_SYS_CLKCFG_OCP_RATIO_3] = 3,
[CPU_SYS_CLKCFG_OCP_RATIO_4] = 4,
[CPU_SYS_CLKCFG_OCP_RATIO_5] = 5,
[CPU_SYS_CLKCFG_OCP_RATIO_10] = 10,
};
static __init unsigned long
mt7620_get_dram_rate(unsigned long pll_rate)
{
if (dram_type == SYSCFG0_DRAM_TYPE_SDRAM)
return pll_rate / 4;
return pll_rate / 3;
}
static __init unsigned long
mt7620_get_sys_rate(unsigned long cpu_rate)
{
u32 reg;
u32 ocp_ratio;
u32 div;
reg = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG);
ocp_ratio = (reg >> CPU_SYS_CLKCFG_OCP_RATIO_SHIFT) &
CPU_SYS_CLKCFG_OCP_RATIO_MASK;
if (WARN_ON(ocp_ratio >= ARRAY_SIZE(mt7620_ocp_dividers)))
return cpu_rate;
div = mt7620_ocp_dividers[ocp_ratio];
if (WARN(!div, "invalid divider for OCP ratio %u", ocp_ratio))
return cpu_rate;
return cpu_rate / div;
}
void __init ralink_clk_init(void)
{
unsigned long xtal_rate;
unsigned long cpu_pll_rate;
unsigned long pll_rate;
unsigned long cpu_rate;
unsigned long sys_rate;
unsigned long dram_rate;
unsigned long periph_rate;
unsigned long pcmi2s_rate;
xtal_rate = mt7620_get_xtal_rate();
#define RFMT(label) label ":%lu.%03luMHz "
#define RINT(x) ((x) / 1000000)
#define RFRAC(x) (((x) / 1000) % 1000)
if (is_mt76x8()) {
if (xtal_rate == MHZ(40))
cpu_rate = MHZ(580);
else
cpu_rate = MHZ(575);
dram_rate = sys_rate = cpu_rate / 3;
periph_rate = MHZ(40);
pcmi2s_rate = MHZ(480);
ralink_clk_add("10000d00.uartlite", periph_rate);
ralink_clk_add("10000e00.uartlite", periph_rate);
} else {
cpu_pll_rate = mt7620_get_cpu_pll_rate(xtal_rate);
pll_rate = mt7620_get_pll_rate(xtal_rate, cpu_pll_rate);
cpu_rate = mt7620_get_cpu_rate(pll_rate);
dram_rate = mt7620_get_dram_rate(pll_rate);
sys_rate = mt7620_get_sys_rate(cpu_rate);
periph_rate = mt7620_get_periph_rate(xtal_rate);
pcmi2s_rate = periph_rate;
pr_debug(RFMT("XTAL") RFMT("CPU_PLL") RFMT("PLL"),
RINT(xtal_rate), RFRAC(xtal_rate),
RINT(cpu_pll_rate), RFRAC(cpu_pll_rate),
RINT(pll_rate), RFRAC(pll_rate));
ralink_clk_add("10000500.uart", periph_rate);
}
pr_debug(RFMT("CPU") RFMT("DRAM") RFMT("SYS") RFMT("PERIPH"),
RINT(cpu_rate), RFRAC(cpu_rate),
RINT(dram_rate), RFRAC(dram_rate),
RINT(sys_rate), RFRAC(sys_rate),
RINT(periph_rate), RFRAC(periph_rate));
#undef RFRAC
#undef RINT
#undef RFMT
ralink_clk_add("cpu", cpu_rate);
ralink_clk_add("10000100.timer", periph_rate);
ralink_clk_add("10000120.watchdog", periph_rate);
ralink_clk_add("10000900.i2c", periph_rate);
ralink_clk_add("10000a00.i2s", pcmi2s_rate);
ralink_clk_add("10000b00.spi", sys_rate);
ralink_clk_add("10000b40.spi", sys_rate);
ralink_clk_add("10000c00.uartlite", periph_rate);
ralink_clk_add("10000d00.uart1", periph_rate);
ralink_clk_add("10000e00.uart2", periph_rate);
ralink_clk_add("10180000.wmac", xtal_rate);
if (IS_ENABLED(CONFIG_USB) && !is_mt76x8()) {
/*
* When the CPU goes into sleep mode, the BUS clock will be
* too low for USB to function properly. Adjust the busses
* fractional divider to fix this
*/
u32 val = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG);
val &= ~(CLKCFG_FDIV_MASK | CLKCFG_FFRAC_MASK);
val |= CLKCFG_FDIV_USB_VAL | CLKCFG_FFRAC_USB_VAL;
rt_sysc_w32(val, SYSC_REG_CPU_SYS_CLKCFG);
}
}
void __init ralink_of_remap(void)
{
rt_sysc_membase = plat_of_remap_node("ralink,mt7620a-sysc");
rt_memc_membase = plat_of_remap_node("ralink,mt7620a-memc");
if (!rt_sysc_membase || !rt_memc_membase)
panic("Failed to remap core resources");
}
static __init void
mt7620_dram_init(struct ralink_soc_info *soc_info)
{

9
arch/mips/ralink/mt7621.c
View File

@ -89,15 +89,6 @@ static void __init mt7621_memory_detect(void)
memblock_add(MT7621_HIGHMEM_BASE, MT7621_HIGHMEM_SIZE);
}
void __init ralink_of_remap(void)
{
rt_sysc_membase = plat_of_remap_node("mediatek,mt7621-sysc");
rt_memc_membase = plat_of_remap_node("mediatek,mt7621-memc");
if (!rt_sysc_membase || !rt_memc_membase)
panic("Failed to remap core resources");
}
static unsigned int __init mt7621_get_soc_name0(void)
{
return __raw_readl(MT7621_SYSC_BASE + SYSC_REG_CHIP_NAME0);

51
arch/mips/ralink/of.c
View File

@ -29,28 +29,61 @@ __iomem void *rt_sysc_membase;
__iomem void *rt_memc_membase;
EXPORT_SYMBOL_GPL(rt_sysc_membase);
__iomem void *plat_of_remap_node(const char *node)
static const struct of_device_id mtmips_memc_match[] = {
{ .compatible = "mediatek,mt7621-memc" },
{ .compatible = "ralink,mt7620a-memc" },
{ .compatible = "ralink,rt2880-memc" },
{ .compatible = "ralink,rt3050-memc" },
{ .compatible = "ralink,rt3883-memc" },
{}
};
static const struct of_device_id mtmips_sysc_match[] = {
{ .compatible = "mediatek,mt7621-sysc" },
{ .compatible = "ralink,mt7620-sysc" },
{ .compatible = "ralink,mt7628-sysc" },
{ .compatible = "ralink,mt7688-sysc" },
{ .compatible = "ralink,rt2880-sysc" },
{ .compatible = "ralink,rt3050-sysc" },
{ .compatible = "ralink,rt3052-sysc" },
{ .compatible = "ralink,rt3352-sysc" },
{ .compatible = "ralink,rt3883-sysc" },
{ .compatible = "ralink,rt5350-sysc" },
{}
};
static __iomem void *
mtmips_of_remap_node(const struct of_device_id *match, const char *type)
{
struct resource res;
struct device_node *np;
np = of_find_compatible_node(NULL, NULL, node);
np = of_find_matching_node(NULL, match);
if (!np)
panic("Failed to find %s node", node);
panic("Failed to find %s controller node", type);
if (of_address_to_resource(np, 0, &res))
panic("Failed to get resource for %s", node);
of_node_put(np);
panic("Failed to get resource for %s node", np->name);
if (!request_mem_region(res.start,
resource_size(&res),
res.name))
panic("Failed to request resources for %s", node);
panic("Failed to request resources for %s node", np->name);
of_node_put(np);
return ioremap(res.start, resource_size(&res));
}
void __init ralink_of_remap(void)
{
rt_sysc_membase = mtmips_of_remap_node(mtmips_sysc_match, "system");
rt_memc_membase = mtmips_of_remap_node(mtmips_memc_match, "memory");
if (!rt_sysc_membase || !rt_memc_membase)
panic("Failed to remap core resources");
}
void __init plat_mem_setup(void)
{
void *dtb;
@ -81,10 +114,6 @@ static int __init plat_of_setup(void)
{
__dt_register_buses(soc_info.compatible, "palmbus");
/* make sure that the reset controller is setup early */
if (ralink_soc != MT762X_SOC_MT7621AT)
ralink_rst_init();
return 0;
}

61
arch/mips/ralink/reset.c
View File

@ -10,7 +10,6 @@
#include <linux/io.h>
#include <linux/of.h>
#include <linux/delay.h>
#include <linux/reset-controller.h>
#include <asm/reboot.h>
@ -22,66 +21,6 @@
#define RSTCTL_RESET_PCI BIT(26)
#define RSTCTL_RESET_SYSTEM BIT(0)
static int ralink_assert_device(struct reset_controller_dev *rcdev,
unsigned long id)
{
u32 val;
if (id == 0)
return -1;
val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
val |= BIT(id);
rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
return 0;
}
static int ralink_deassert_device(struct reset_controller_dev *rcdev,
unsigned long id)
{
u32 val;
if (id == 0)
return -1;
val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
val &= ~BIT(id);
rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
return 0;
}
static int ralink_reset_device(struct reset_controller_dev *rcdev,
unsigned long id)
{
ralink_assert_device(rcdev, id);
return ralink_deassert_device(rcdev, id);
}
static const struct reset_control_ops reset_ops = {
.reset = ralink_reset_device,
.assert = ralink_assert_device,
.deassert = ralink_deassert_device,
};
static struct reset_controller_dev reset_dev = {
.ops = &reset_ops,
.owner = THIS_MODULE,
.nr_resets = 32,
.of_reset_n_cells = 1,
};
void ralink_rst_init(void)
{
reset_dev.of_node = of_find_compatible_node(NULL, NULL,
"ralink,rt2880-reset");
if (!reset_dev.of_node)
pr_err("Failed to find reset controller node");
else
reset_controller_register(&reset_dev);
}
static void ralink_restart(char *command)
{
if (IS_ENABLED(CONFIG_PCI)) {

40
arch/mips/ralink/rt288x.c
View File

@ -21,46 +21,6 @@
static struct ralink_soc_info *soc_info_ptr;
void __init ralink_clk_init(void)
{
unsigned long cpu_rate, wmac_rate = 40000000;
u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
t = ((t >> SYSTEM_CONFIG_CPUCLK_SHIFT) & SYSTEM_CONFIG_CPUCLK_MASK);
switch (t) {
case SYSTEM_CONFIG_CPUCLK_250:
cpu_rate = 250000000;
break;
case SYSTEM_CONFIG_CPUCLK_266:
cpu_rate = 266666667;
break;
case SYSTEM_CONFIG_CPUCLK_280:
cpu_rate = 280000000;
break;
case SYSTEM_CONFIG_CPUCLK_300:
cpu_rate = 300000000;
break;
}
ralink_clk_add("cpu", cpu_rate);
ralink_clk_add("300100.timer", cpu_rate / 2);
ralink_clk_add("300120.watchdog", cpu_rate / 2);
ralink_clk_add("300500.uart", cpu_rate / 2);
ralink_clk_add("300900.i2c", cpu_rate / 2);
ralink_clk_add("300c00.uartlite", cpu_rate / 2);
ralink_clk_add("400000.ethernet", cpu_rate / 2);
ralink_clk_add("480000.wmac", wmac_rate);
}
void __init ralink_of_remap(void)
{
rt_sysc_membase = plat_of_remap_node("ralink,rt2880-sysc");
rt_memc_membase = plat_of_remap_node("ralink,rt2880-memc");
if (!rt_sysc_membase || !rt_memc_membase)
panic("Failed to remap core resources");
}
static unsigned int __init rt2880_get_soc_name0(void)
{
return __raw_readl(RT2880_SYSC_BASE + SYSC_REG_CHIP_NAME0);

87
arch/mips/ralink/rt305x.c
View File

@ -56,93 +56,6 @@ static unsigned long rt5350_get_mem_size(void)
return ret;
}
void __init ralink_clk_init(void)
{
unsigned long cpu_rate, sys_rate, wdt_rate, uart_rate;
unsigned long wmac_rate = 40000000;
u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
if (soc_is_rt305x() || soc_is_rt3350()) {
t = (t >> RT305X_SYSCFG_CPUCLK_SHIFT) &
RT305X_SYSCFG_CPUCLK_MASK;
switch (t) {
case RT305X_SYSCFG_CPUCLK_LOW:
cpu_rate = 320000000;
break;
case RT305X_SYSCFG_CPUCLK_HIGH:
cpu_rate = 384000000;
break;
}
sys_rate = uart_rate = wdt_rate = cpu_rate / 3;
} else if (soc_is_rt3352()) {
t = (t >> RT3352_SYSCFG0_CPUCLK_SHIFT) &
RT3352_SYSCFG0_CPUCLK_MASK;
switch (t) {
case RT3352_SYSCFG0_CPUCLK_LOW:
cpu_rate = 384000000;
break;
case RT3352_SYSCFG0_CPUCLK_HIGH:
cpu_rate = 400000000;
break;
}
sys_rate = wdt_rate = cpu_rate / 3;
uart_rate = 40000000;
} else if (soc_is_rt5350()) {
t = (t >> RT5350_SYSCFG0_CPUCLK_SHIFT) &
RT5350_SYSCFG0_CPUCLK_MASK;
switch (t) {
case RT5350_SYSCFG0_CPUCLK_360:
cpu_rate = 360000000;
sys_rate = cpu_rate / 3;
break;
case RT5350_SYSCFG0_CPUCLK_320:
cpu_rate = 320000000;
sys_rate = cpu_rate / 4;
break;
case RT5350_SYSCFG0_CPUCLK_300:
cpu_rate = 300000000;
sys_rate = cpu_rate / 3;
break;
default:
BUG();
}
uart_rate = 40000000;
wdt_rate = sys_rate;
} else {
BUG();
}
if (soc_is_rt3352() || soc_is_rt5350()) {
u32 val = rt_sysc_r32(RT3352_SYSC_REG_SYSCFG0);
if (!(val & RT3352_CLKCFG0_XTAL_SEL))
wmac_rate = 20000000;
}
ralink_clk_add("cpu", cpu_rate);
ralink_clk_add("sys", sys_rate);
ralink_clk_add("10000900.i2c", uart_rate);
ralink_clk_add("10000a00.i2s", uart_rate);
ralink_clk_add("10000b00.spi", sys_rate);
ralink_clk_add("10000b40.spi", sys_rate);
ralink_clk_add("10000100.timer", wdt_rate);
ralink_clk_add("10000120.watchdog", wdt_rate);
ralink_clk_add("10000500.uart", uart_rate);
ralink_clk_add("10000c00.uartlite", uart_rate);
ralink_clk_add("10100000.ethernet", sys_rate);
ralink_clk_add("10180000.wmac", wmac_rate);
}
void __init ralink_of_remap(void)
{
rt_sysc_membase = plat_of_remap_node("ralink,rt3050-sysc");
rt_memc_membase = plat_of_remap_node("ralink,rt3050-memc");
if (!rt_sysc_membase || !rt_memc_membase)
panic("Failed to remap core resources");
}
static unsigned int __init rt305x_get_soc_name0(void)
{
return __raw_readl(RT305X_SYSC_BASE + SYSC_REG_CHIP_NAME0);

53
arch/mips/ralink/rt3883.c
View File

@ -21,59 +21,6 @@
static struct ralink_soc_info *soc_info_ptr;
void __init ralink_clk_init(void)
{
unsigned long cpu_rate, sys_rate;
u32 syscfg0;
u32 clksel;
u32 ddr2;
syscfg0 = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG0);
clksel = ((syscfg0 >> RT3883_SYSCFG0_CPUCLK_SHIFT) &
RT3883_SYSCFG0_CPUCLK_MASK);
ddr2 = syscfg0 & RT3883_SYSCFG0_DRAM_TYPE_DDR2;
switch (clksel) {
case RT3883_SYSCFG0_CPUCLK_250:
cpu_rate = 250000000;
sys_rate = (ddr2) ? 125000000 : 83000000;
break;
case RT3883_SYSCFG0_CPUCLK_384:
cpu_rate = 384000000;
sys_rate = (ddr2) ? 128000000 : 96000000;
break;
case RT3883_SYSCFG0_CPUCLK_480:
cpu_rate = 480000000;
sys_rate = (ddr2) ? 160000000 : 120000000;
break;
case RT3883_SYSCFG0_CPUCLK_500:
cpu_rate = 500000000;
sys_rate = (ddr2) ? 166000000 : 125000000;
break;
}
ralink_clk_add("cpu", cpu_rate);
ralink_clk_add("10000100.timer", sys_rate);
ralink_clk_add("10000120.watchdog", sys_rate);
ralink_clk_add("10000500.uart", 40000000);
ralink_clk_add("10000900.i2c", 40000000);
ralink_clk_add("10000a00.i2s", 40000000);
ralink_clk_add("10000b00.spi", sys_rate);
ralink_clk_add("10000b40.spi", sys_rate);
ralink_clk_add("10000c00.uartlite", 40000000);
ralink_clk_add("10100000.ethernet", sys_rate);
ralink_clk_add("10180000.wmac", 40000000);
}
void __init ralink_of_remap(void)
{
rt_sysc_membase = plat_of_remap_node("ralink,rt3883-sysc");
rt_memc_membase = plat_of_remap_node("ralink,rt3883-memc");
if (!rt_sysc_membase || !rt_memc_membase)
panic("Failed to remap core resources");
}
static unsigned int __init rt3883_get_soc_name0(void)
{
return __raw_readl(RT3883_SYSC_BASE + RT3883_SYSC_REG_CHIPID0_3);

14
arch/mips/sibyte/swarm/platform.c
View File

@ -88,15 +88,15 @@ device_initcall(swarm_pata_init);
#define sb1250_dev_struct(num) \
static struct resource sb1250_res##num = { \
.name = "SB1250 MAC " __stringify(num), \
.flags = IORESOURCE_MEM, \
.start = A_MAC_CHANNEL_BASE(num), \
.end = A_MAC_CHANNEL_BASE(num + 1) -1, \
.flags = IORESOURCE_MEM, \
.start = A_MAC_CHANNEL_BASE(num), \
.end = A_MAC_CHANNEL_BASE(num + 1) - 1, \
};\
static struct platform_device sb1250_dev##num = { \
.name = "sb1250-mac", \
.id = num, \
.resource = &sb1250_res##num, \
.num_resources = 1, \
.name = "sb1250-mac", \
.id = num, \
.resource = &sb1250_res##num, \
.num_resources = 1, \
}
sb1250_dev_struct(0);

7
drivers/char/mem.c
View File

@ -90,13 +90,6 @@ static inline int range_is_allowed(unsigned long pfn, unsigned long size)
}
#endif
#ifndef unxlate_dev_mem_ptr
#define unxlate_dev_mem_ptr unxlate_dev_mem_ptr
void __weak unxlate_dev_mem_ptr(phys_addr_t phys, void *addr)
{
}
#endif
static inline bool should_stop_iteration(void)
{
if (need_resched())

7
drivers/clk/ralink/Kconfig
View File

@ -9,3 +9,10 @@ config CLK_MT7621
select MFD_SYSCON
help
This driver supports MediaTek MT7621 basic clocks.
config CLK_MTMIPS
bool "Clock driver for MTMIPS SoCs"
depends on SOC_RT305X || SOC_RT288X || SOC_RT3883 || SOC_MT7620 || COMPILE_TEST
select MFD_SYSCON
help
This driver supports MTMIPS basic clocks.

1
drivers/clk/ralink/Makefile
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@ -1,2 +1,3 @@
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_CLK_MT7621) += clk-mt7621.o
obj-$(CONFIG_CLK_MTMIPS) += clk-mtmips.o

1117
drivers/clk/ralink/clk-mtmips.c Normal file
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