tg3: Fix link down notify failure when EEE disabled
Occasionally, when the network cable is removed after a successful autonegotiation, the device will not send a link down interrupt to the driver. This happens because of a bad interaction of an EEE workaround. The fix is to adjust the code so that the root cause condition does not happen. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Reviewed-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -1858,6 +1858,12 @@ static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up)
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}
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if (!tp->setlpicnt) {
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if (current_link_up == 1 &&
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!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
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tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000);
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TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
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}
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val = tr32(TG3_CPMU_EEE_MODE);
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tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
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}
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@ -1872,7 +1878,9 @@ static void tg3_phy_eee_enable(struct tg3 *tp)
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
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!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
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tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0003);
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val = MII_TG3_DSP_TAP26_ALNOKO |
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MII_TG3_DSP_TAP26_RMRXSTO;
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tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
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TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
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}
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@ -3128,21 +3136,6 @@ static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl)
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if (!err) {
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u32 err2;
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switch (GET_ASIC_REV(tp->pci_chip_rev_id)) {
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case ASIC_REV_5717:
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case ASIC_REV_57765:
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case ASIC_REV_5719:
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val = MII_TG3_DSP_TAP26_ALNOKO |
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MII_TG3_DSP_TAP26_RMRXSTO |
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MII_TG3_DSP_TAP26_OPCSINPT;
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tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
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/* Fall through */
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case ASIC_REV_5720:
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if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
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tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val |
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MII_TG3_DSP_CH34TP2_HIBW01);
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}
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val = 0;
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/* Advertise 100-BaseTX EEE ability */
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if (advertise & ADVERTISED_100baseT_Full)
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@ -3151,6 +3144,25 @@ static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl)
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if (advertise & ADVERTISED_1000baseT_Full)
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val |= MDIO_AN_EEE_ADV_1000T;
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err = tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
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if (err)
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val = 0;
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switch (GET_ASIC_REV(tp->pci_chip_rev_id)) {
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case ASIC_REV_5717:
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case ASIC_REV_57765:
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case ASIC_REV_5719:
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/* If we advertised any eee advertisements above... */
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if (val)
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val = MII_TG3_DSP_TAP26_ALNOKO |
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MII_TG3_DSP_TAP26_RMRXSTO |
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MII_TG3_DSP_TAP26_OPCSINPT;
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tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
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/* Fall through */
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case ASIC_REV_5720:
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if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
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tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val |
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MII_TG3_DSP_CH34TP2_HIBW01);
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}
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err2 = TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
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if (!err)
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