media: rkisp1: isp: Move input configuration to rkisp1_config_isp()
The ISP_ACQ_PROP register is set twice, once in rkisp1_config_isp() for most of its fields, and once in rkisp1_config_dvp() (called from rkisp1_config_path()) to configure the input selection field. Move the latter to rkisp1_config_isp() to write the register once only, and drop the now empty rkisp1_config_dvp() function. Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Paul Elder <paul.elder@ideasonboard.com> Reviewed-by: Dafna Hirschfeld <dafna@fastmail.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
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@ -141,7 +141,7 @@ static int rkisp1_config_isp(struct rkisp1_isp *isp,
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enum v4l2_mbus_type mbus_type, u32 mbus_flags)
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{
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struct rkisp1_device *rkisp1 = isp->rkisp1;
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u32 isp_ctrl = 0, irq_mask = 0, acq_mult = 0, signal = 0;
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u32 isp_ctrl = 0, irq_mask = 0, acq_mult = 0, signal = 0, input_sel = 0;
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const struct rkisp1_mbus_info *src_fmt, *sink_fmt;
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struct v4l2_mbus_framefmt *sink_frm;
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struct v4l2_rect *sink_crop;
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@ -189,6 +189,22 @@ static int rkisp1_config_isp(struct rkisp1_isp *isp,
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if (mbus_type == V4L2_MBUS_BT656 || mbus_type == V4L2_MBUS_PARALLEL) {
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if (mbus_flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
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signal = RKISP1_CIF_ISP_ACQ_PROP_POS_EDGE;
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switch (sink_fmt->bus_width) {
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case 8:
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input_sel = RKISP1_CIF_ISP_ACQ_PROP_IN_SEL_8B_ZERO;
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break;
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case 10:
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input_sel = RKISP1_CIF_ISP_ACQ_PROP_IN_SEL_10B_ZERO;
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break;
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case 12:
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input_sel = RKISP1_CIF_ISP_ACQ_PROP_IN_SEL_12B;
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break;
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default:
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dev_err(rkisp1->dev, "Invalid bus width %u\n",
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sink_fmt->bus_width);
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return -EINVAL;
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}
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}
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if (mbus_type == V4L2_MBUS_PARALLEL) {
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@ -201,7 +217,7 @@ static int rkisp1_config_isp(struct rkisp1_isp *isp,
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rkisp1_write(rkisp1, RKISP1_CIF_ISP_CTRL, isp_ctrl);
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rkisp1_write(rkisp1, RKISP1_CIF_ISP_ACQ_PROP,
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signal | sink_fmt->yuv_seq |
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signal | sink_fmt->yuv_seq | input_sel |
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RKISP1_CIF_ISP_ACQ_PROP_BAYER_PAT(sink_fmt->bayer_pat) |
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RKISP1_CIF_ISP_ACQ_PROP_FIELD_SEL_ALL);
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rkisp1_write(rkisp1, RKISP1_CIF_ISP_ACQ_NR_FRAMES, 0);
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@ -238,52 +254,19 @@ static int rkisp1_config_isp(struct rkisp1_isp *isp,
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return 0;
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}
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static int rkisp1_config_dvp(struct rkisp1_isp *isp)
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{
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struct rkisp1_device *rkisp1 = isp->rkisp1;
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const struct rkisp1_mbus_info *sink_fmt = isp->sink_fmt;
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u32 val, input_sel;
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switch (sink_fmt->bus_width) {
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case 8:
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input_sel = RKISP1_CIF_ISP_ACQ_PROP_IN_SEL_8B_ZERO;
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break;
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case 10:
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input_sel = RKISP1_CIF_ISP_ACQ_PROP_IN_SEL_10B_ZERO;
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break;
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case 12:
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input_sel = RKISP1_CIF_ISP_ACQ_PROP_IN_SEL_12B;
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break;
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default:
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dev_err(rkisp1->dev, "Invalid bus width\n");
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return -EINVAL;
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}
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val = rkisp1_read(rkisp1, RKISP1_CIF_ISP_ACQ_PROP);
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rkisp1_write(rkisp1, RKISP1_CIF_ISP_ACQ_PROP, val | input_sel);
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return 0;
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}
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/* Configure MUX */
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static int rkisp1_config_path(struct rkisp1_isp *isp,
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enum v4l2_mbus_type mbus_type)
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static void rkisp1_config_path(struct rkisp1_isp *isp,
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enum v4l2_mbus_type mbus_type)
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{
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struct rkisp1_device *rkisp1 = isp->rkisp1;
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u32 dpcl = rkisp1_read(rkisp1, RKISP1_CIF_VI_DPCL);
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int ret = 0;
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if (mbus_type == V4L2_MBUS_BT656 ||
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mbus_type == V4L2_MBUS_PARALLEL) {
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ret = rkisp1_config_dvp(isp);
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if (mbus_type == V4L2_MBUS_BT656 || mbus_type == V4L2_MBUS_PARALLEL)
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dpcl |= RKISP1_CIF_VI_DPCL_IF_SEL_PARALLEL;
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} else if (mbus_type == V4L2_MBUS_CSI2_DPHY) {
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else if (mbus_type == V4L2_MBUS_CSI2_DPHY)
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dpcl |= RKISP1_CIF_VI_DPCL_IF_SEL_MIPI;
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}
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rkisp1_write(rkisp1, RKISP1_CIF_VI_DPCL, dpcl);
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return ret;
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}
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/* Hardware configure Entry */
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@ -295,9 +278,8 @@ static int rkisp1_config_cif(struct rkisp1_isp *isp,
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ret = rkisp1_config_isp(isp, mbus_type, mbus_flags);
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if (ret)
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return ret;
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ret = rkisp1_config_path(isp, mbus_type);
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if (ret)
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return ret;
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rkisp1_config_path(isp, mbus_type);
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rkisp1_config_ism(isp);
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return 0;
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