drm/i915: Be optimistic about future display engines having 7 WM levels
As we're doing throughout the code, being optimistic that platform n + 1 will mostly reuse the same things as platform n allows us to minimize the enabling work needed. This time, it's about the number of WM levels. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -1946,7 +1946,7 @@ static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
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int ilk_wm_max_level(const struct drm_device *dev)
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{
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/* how many WM levels are we expecting */
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if (IS_GEN9(dev))
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if (INTEL_INFO(dev)->gen >= 9)
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return 7;
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else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
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return 4;
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