Staging: emxx_udc: emxx_udc: Add space around operator.
Add space around operator.This patch is found by checkpatch.pl script. Signed-off-by: Sandhya Bankar <bankarsandhya512@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Sandhya Bankar
Greg Kroah-Hartman
parent
abe3417445
commit
b6d3b4577e
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@ -97,7 +97,7 @@
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#define BIT30 0x40000000
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#define BIT31 0x80000000
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#define TEST_FORCE_ENABLE (BIT18+BIT16)
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#define TEST_FORCE_ENABLE (BIT18 + BIT16)
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#define INT_SEL BIT10
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#define CONSTFS BIT09
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@ -125,15 +125,15 @@
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/*------- (0x0008) USB Address Register */
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#define USB_ADDR 0x007F0000
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#define SOF_STATUS BIT15
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#define UFRAME (BIT14+BIT13+BIT12)
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#define UFRAME (BIT14 + BIT13 + BIT12)
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#define FRAME 0x000007FF
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#define USB_ADRS_SHIFT 16
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/*------- (0x000C) UTMI Characteristic 1 Register */
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#define SQUSET (BIT07+BIT06+BIT05+BIT04)
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#define SQUSET (BIT07 + BIT06 + BIT05 + BIT04)
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#define USB_SQUSET (BIT06+BIT05+BIT04)
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#define USB_SQUSET (BIT06 + BIT05 + BIT04)
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/*------- (0x0010) TEST Control Register */
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#define FORCEHS BIT02
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@ -196,7 +196,7 @@
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#define RSUM_EN BIT01
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#define USB_INT_EN_BIT \
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(EP0_EN|SPEED_MODE_EN|USB_RST_EN|SPND_EN|RSUM_EN)
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(EP0_EN | SPEED_MODE_EN | USB_RST_EN | SPND_EN | RSUM_EN)
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/*------- (0x0028) EP0 Control Register */
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#define EP0_STGSEL BIT18
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@ -205,9 +205,9 @@
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#define EP0_PIDCLR BIT09
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#define EP0_BCLR BIT08
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#define EP0_DEND BIT07
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#define EP0_DW (BIT06+BIT05)
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#define EP0_DW (BIT06 + BIT05)
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#define EP0_DW4 0
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#define EP0_DW3 (BIT06+BIT05)
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#define EP0_DW3 (BIT06 + BIT05)
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#define EP0_DW2 BIT06
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#define EP0_DW1 BIT05
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@ -238,7 +238,7 @@
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#define STG_START_INT BIT01
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#define SETUP_INT BIT00
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#define EP0_STATUS_RW_BIT (BIT16|BIT15|BIT11|0xFF)
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#define EP0_STATUS_RW_BIT (BIT16 | BIT15 | BIT11 | 0xFF)
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/*------- (0x0030) EP0 Interrupt Enable Register */
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#define EP0_PERR_NAK_EN BIT16
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@ -256,7 +256,7 @@
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#define SETUP_EN BIT00
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#define EP0_INT_EN_BIT \
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(EP0_OUT_OR_EN|EP0_OUT_EN|EP0_IN_EN|STG_END_EN|SETUP_EN)
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(EP0_OUT_OR_EN | EP0_OUT_EN | EP0_IN_EN | STG_END_EN | SETUP_EN)
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/*------- (0x0034) EP0 Length Register */
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#define EP0_LDATA 0x0000007F
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@ -270,7 +270,7 @@
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#define EPn_BUF_SINGLE BIT30
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#define EPn_DIR0 BIT26
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#define EPn_MODE (BIT25+BIT24)
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#define EPn_MODE (BIT25 + BIT24)
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#define EPn_BULK 0
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#define EPn_INTERRUPT BIT24
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#define EPn_ISO BIT25
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@ -283,9 +283,9 @@
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#define EPn_BCLR BIT09
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#define EPn_CBCLR BIT08
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#define EPn_DEND BIT07
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#define EPn_DW (BIT06+BIT05)
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#define EPn_DW (BIT06 + BIT05)
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#define EPn_DW4 0
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#define EPn_DW3 (BIT06+BIT05)
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#define EPn_DW3 (BIT06 + BIT05)
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#define EPn_DW2 BIT06
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#define EPn_DW1 BIT05
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@ -324,7 +324,7 @@
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#define EPn_IN_EMPTY BIT00 /* R */
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#define EPn_INT_EN \
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(EPn_OUT_END_INT|EPn_OUT_INT|EPn_IN_END_INT|EPn_IN_INT)
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(EPn_OUT_END_INT | EPn_OUT_INT | EPn_IN_END_INT | EPn_IN_INT)
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/*------- (0x0048:) EPn Interrupt Enable Register */
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#define EPn_OUT_END_EN BIT23 /* RW */
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@ -368,7 +368,7 @@
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#define ARBITER_CTR BIT31 /* RW */
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#define MCYCLE_RST BIT12 /* RW */
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#define ENDIAN_CTR (BIT09+BIT08) /* RW */
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#define ENDIAN_CTR (BIT09 + BIT08) /* RW */
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#define ENDIAN_BYTE_SWAP BIT09
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#define ENDIAN_HALF_WORD_SWAP ENDIAN_CTR
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@ -376,7 +376,7 @@
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#define HTRANS_MODE BIT04 /* RW */
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#define WBURST_TYPE BIT02 /* RW */
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#define BURST_TYPE (BIT01+BIT00) /* RW */
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#define BURST_TYPE (BIT01 + BIT00) /* RW */
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#define BURST_MAX_16 0
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#define BURST_MAX_8 BIT00
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#define BURST_MAX_4 BIT01
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@ -412,7 +412,7 @@
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#define EPC_RST BIT00 /* RW */
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/*------- (0x1014) USBF_EPTEST Register */
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#define LINESTATE (BIT09+BIT08) /* R */
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#define LINESTATE (BIT09 + BIT08) /* R */
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#define DM_LEVEL BIT09 /* R */
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#define DP_LEVEL BIT08 /* R */
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@ -485,7 +485,7 @@ struct fc_regs {
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struct ep_regs EP_REGS[REG_EP_NUM]; /* Endpoint Register */
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u8 Reserved220[0x1000-0x220]; /* (0x0220:0x0FFF) Reserved */
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u8 Reserved220[0x1000 - 0x220]; /* (0x0220:0x0FFF) Reserved */
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u32 AHBSCTR; /* (0x1000) AHBSCTR */
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u32 AHBMCTR; /* (0x1004) AHBMCTR */
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@ -494,16 +494,16 @@ struct fc_regs {
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u32 EPCTR; /* (0x1010) EPCTR */
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u32 USBF_EPTEST; /* (0x1014) USBF_EPTEST */
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u8 Reserved1018[0x20-0x18]; /* (0x1018:0x101F) Reserved */
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u8 Reserved1018[0x20 - 0x18]; /* (0x1018:0x101F) Reserved */
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u32 USBSSVER; /* (0x1020) USBSSVER */
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u32 USBSSCONF; /* (0x1024) USBSSCONF */
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u8 Reserved1028[0x110-0x28]; /* (0x1028:0x110F) Reserved */
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u8 Reserved1028[0x110 - 0x28]; /* (0x1028:0x110F) Reserved */
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struct ep_dcr EP_DCR[REG_EP_NUM]; /* */
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u8 Reserved1200[0x1000-0x200]; /* Reserved */
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u8 Reserved1200[0x1000 - 0x200]; /* Reserved */
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} __aligned(32);
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#define EP0_PACKETSIZE 64
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