spi: pxa2xx: Remove cr0 variable from struct chip_data
There hasn't been need to carry chip->cr0 after SPI core started to validate speed_hz and bits_per_word transfer parameters. That effectively caused that pump_transfers() always recalculated it and practically chip->cr0 is used locally in setup() for debug prints only. Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -1101,6 +1101,7 @@ static int setup(struct spi_device *spi)
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struct driver_data *drv_data = spi_master_get_devdata(spi->master);
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struct driver_data *drv_data = spi_master_get_devdata(spi->master);
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unsigned int clk_div;
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unsigned int clk_div;
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uint tx_thres, tx_hi_thres, rx_thres;
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uint tx_thres, tx_hi_thres, rx_thres;
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u32 cr0;
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switch (drv_data->ssp_type) {
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switch (drv_data->ssp_type) {
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case QUARK_X1000_SSP:
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case QUARK_X1000_SSP:
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@ -1193,8 +1194,6 @@ static int setup(struct spi_device *spi)
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clk_div = pxa2xx_ssp_get_clk_div(drv_data, chip, spi->max_speed_hz);
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clk_div = pxa2xx_ssp_get_clk_div(drv_data, chip, spi->max_speed_hz);
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chip->cr0 = pxa2xx_configure_sscr0(drv_data, clk_div,
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spi->bits_per_word);
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switch (drv_data->ssp_type) {
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switch (drv_data->ssp_type) {
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case QUARK_X1000_SSP:
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case QUARK_X1000_SSP:
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chip->threshold = (QUARK_X1000_SSCR1_RxTresh(rx_thres)
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chip->threshold = (QUARK_X1000_SSCR1_RxTresh(rx_thres)
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@ -1216,15 +1215,16 @@ static int setup(struct spi_device *spi)
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chip->cr1 |= SSCR1_LBM;
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chip->cr1 |= SSCR1_LBM;
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/* NOTE: PXA25x_SSP _could_ use external clocking ... */
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/* NOTE: PXA25x_SSP _could_ use external clocking ... */
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cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, spi->bits_per_word);
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if (!pxa25x_ssp_comp(drv_data))
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if (!pxa25x_ssp_comp(drv_data))
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dev_dbg(&spi->dev, "%ld Hz actual, %s\n",
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dev_dbg(&spi->dev, "%ld Hz actual, %s\n",
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drv_data->max_clk_rate
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drv_data->max_clk_rate
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/ (1 + ((chip->cr0 & SSCR0_SCR(0xfff)) >> 8)),
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/ (1 + ((cr0 & SSCR0_SCR(0xfff)) >> 8)),
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chip->enable_dma ? "DMA" : "PIO");
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chip->enable_dma ? "DMA" : "PIO");
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else
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else
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dev_dbg(&spi->dev, "%ld Hz actual, %s\n",
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dev_dbg(&spi->dev, "%ld Hz actual, %s\n",
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drv_data->max_clk_rate / 2
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drv_data->max_clk_rate / 2
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/ (1 + ((chip->cr0 & SSCR0_SCR(0x0ff)) >> 8)),
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/ (1 + ((cr0 & SSCR0_SCR(0x0ff)) >> 8)),
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chip->enable_dma ? "DMA" : "PIO");
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chip->enable_dma ? "DMA" : "PIO");
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if (spi->bits_per_word <= 8) {
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if (spi->bits_per_word <= 8) {
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@ -1236,8 +1236,6 @@ static int setup(struct spi_device *spi)
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chip->read = u16_reader;
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chip->read = u16_reader;
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chip->write = u16_writer;
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chip->write = u16_writer;
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} else if (spi->bits_per_word <= 32) {
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} else if (spi->bits_per_word <= 32) {
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if (!is_quark_x1000_ssp(drv_data))
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chip->cr0 |= SSCR0_EDSS;
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chip->n_bytes = 4;
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chip->n_bytes = 4;
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chip->read = u32_reader;
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chip->read = u32_reader;
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chip->write = u32_writer;
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chip->write = u32_writer;
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@ -86,7 +86,6 @@ struct driver_data {
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};
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};
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struct chip_data {
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struct chip_data {
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u32 cr0;
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u32 cr1;
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u32 cr1;
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u32 dds_rate;
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u32 dds_rate;
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u32 psp;
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u32 psp;
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