- qcom : enable support for ipq8074, sm1850 and sm7180.
add child device node for qcs404.
misc fixes.
- mediatek : enable support for mt8183.
misc rejig of cmdq driver.
new client-reg dt property.
- armada: use device-managed registration api
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Merge tag 'mailbox-v5.4' of git://git.linaro.org/landing-teams/working/fujitsu/integration
Pull mailbox updates from Jassi Brar:
- qcom:
- enable support for ipq8074, sm1850 and sm7180
- add child device node for qcs404
- misc fixes
- mediatek:
- enable support for mt8183
- misc rejig of cmdq driver
- new client-reg dt property
- armada:
- use device-managed registration api
* tag 'mailbox-v5.4' of git://git.linaro.org/landing-teams/working/fujitsu/integration:
mailbox: qcom-apcs: fix max_register value
mailbox: qcom: Add support for IPQ8074 APCS
dt-bindings: mailbox: qom: Add ipq8074 APPS compatible
mailbox: qcom: Add support for Qualcomm SM8150 and SC7180 SoCs
dt-bindings: mailbox: Add APSS shared for SM8150 and SC7180 SoCs
mbox: qcom: replace integer with valid macro
mbox: qcom: add APCS child device for QCS404
mailbox: mediatek: cmdq: clear the event in cmdq initial flow
mailbox: mediatek: cmdq: support mt8183 gce function
mailbox: mediatek: cmdq: move the CMDQ_IRQ_MASK into cmdq driver data
dt-binding: gce: add binding for gce client reg property
dt-binding: gce: add gce header file for mt8183
dt-binding: gce: remove thread-num property
mailbox: armada-37xx-rwtm: Use device-managed registration API
This commit is contained in:
Linus Torvalds
commit
b682242f60
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|
@ -9,7 +9,7 @@ CMDQ driver uses mailbox framework for communication. Please refer to
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mailbox.txt for generic information about mailbox device-tree bindings.
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Required properties:
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- compatible: Must be "mediatek,mt8173-gce"
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- compatible: can be "mediatek,mt8173-gce" or "mediatek,mt8183-gce"
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- reg: Address range of the GCE unit
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- interrupts: The interrupt signal from the GCE block
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- clock: Clocks according to the common clock binding
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@ -25,11 +25,19 @@ Required properties:
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Required properties for a client device:
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- mboxes: Client use mailbox to communicate with GCE, it should have this
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property and list of phandle, mailbox specifiers.
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- mediatek,gce-subsys: u32, specify the sub-system id which is corresponding
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Optional properties for a client device:
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- mediatek,gce-client-reg: Specify the sub-system id which is corresponding
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to the register address, it should have this property and list of phandle,
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sub-system specifiers.
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<&phandle subsys_number start_offset size>
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phandle: Label name of a gce node.
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subsys_number: specify the sub-system id which is corresponding
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to the register address.
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start_offset: the start offset of register address that GCE can access.
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size: the total size of register address that GCE can access.
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Some vaules of properties are defined in 'dt-bindings/gce/mt8173-gce.h'. Such as
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sub-system ids, thread priority, event ids.
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Some vaules of properties are defined in 'dt-bindings/gce/mt8173-gce.h'
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or 'dt-binding/gce/mt8183-gce.h'. Such as sub-system ids, thread priority, event ids.
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Example:
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@ -39,7 +47,6 @@ Example:
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interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&infracfg CLK_INFRA_GCE>;
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clock-names = "gce";
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thread-num = CMDQ_THR_MAX_COUNT;
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#mbox-cells = <3>;
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};
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@ -49,9 +56,9 @@ Example for a client device:
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compatible = "mediatek,mt8173-mmsys";
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mboxes = <&gce 0 CMDQ_THR_PRIO_LOWEST 1>,
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<&gce 1 CMDQ_THR_PRIO_LOWEST 1>;
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mediatek,gce-subsys = <SUBSYS_1400XXXX>;
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mutex-event-eof = <CMDQ_EVENT_MUTEX0_STREAM_EOF
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CMDQ_EVENT_MUTEX1_STREAM_EOF>;
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mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 0x1000>,
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<&gce SUBSYS_1401XXXX 0x2000 0x100>;
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...
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};
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@ -12,7 +12,10 @@ platforms.
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"qcom,msm8996-apcs-hmss-global"
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"qcom,msm8998-apcs-hmss-global"
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"qcom,qcs404-apcs-apps-global"
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"qcom,sc7180-apss-shared"
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"qcom,sdm845-apss-shared"
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"qcom,sm8150-apss-shared"
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"qcom,ipq8074-apcs-apps-global"
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- reg:
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Usage: required
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@ -180,7 +180,7 @@ static int armada_37xx_mbox_probe(struct platform_device *pdev)
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mbox->controller.ops = &a37xx_mbox_ops;
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mbox->controller.txdone_irq = true;
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ret = mbox_controller_register(&mbox->controller);
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ret = devm_mbox_controller_register(mbox->dev, &mbox->controller);
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if (ret) {
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dev_err(&pdev->dev, "Could not register mailbox controller\n");
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return ret;
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@ -190,17 +190,6 @@ static int armada_37xx_mbox_probe(struct platform_device *pdev)
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return ret;
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}
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static int armada_37xx_mbox_remove(struct platform_device *pdev)
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{
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struct a37xx_mbox *mbox = platform_get_drvdata(pdev);
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if (!mbox)
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return -EINVAL;
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mbox_controller_unregister(&mbox->controller);
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return 0;
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}
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static const struct of_device_id armada_37xx_mbox_match[] = {
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{ .compatible = "marvell,armada-3700-rwtm-mailbox" },
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@ -211,7 +200,6 @@ MODULE_DEVICE_TABLE(of, armada_37xx_mbox_match);
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static struct platform_driver armada_37xx_mbox_driver = {
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.probe = armada_37xx_mbox_probe,
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.remove = armada_37xx_mbox_remove,
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.driver = {
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.name = DRIVER_NAME,
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.of_match_table = armada_37xx_mbox_match,
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|
|
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@ -18,10 +18,10 @@
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#include <linux/of_device.h>
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#define CMDQ_OP_CODE_MASK (0xff << CMDQ_OP_CODE_SHIFT)
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#define CMDQ_IRQ_MASK 0xffff
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#define CMDQ_NUM_CMD(t) (t->cmd_buf_size / CMDQ_INST_SIZE)
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#define CMDQ_CURR_IRQ_STATUS 0x10
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#define CMDQ_SYNC_TOKEN_UPDATE 0x68
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#define CMDQ_THR_SLOT_CYCLES 0x30
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#define CMDQ_THR_BASE 0x100
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#define CMDQ_THR_SIZE 0x80
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@ -72,6 +72,7 @@ struct cmdq {
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void __iomem *base;
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u32 irq;
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u32 thread_nr;
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u32 irq_mask;
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struct cmdq_thread *thread;
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struct clk *clock;
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bool suspended;
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@ -104,8 +105,12 @@ static void cmdq_thread_resume(struct cmdq_thread *thread)
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static void cmdq_init(struct cmdq *cmdq)
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{
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int i;
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WARN_ON(clk_enable(cmdq->clock) < 0);
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writel(CMDQ_THR_ACTIVE_SLOT_CYCLES, cmdq->base + CMDQ_THR_SLOT_CYCLES);
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for (i = 0; i <= CMDQ_MAX_EVENT; i++)
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writel(i, cmdq->base + CMDQ_SYNC_TOKEN_UPDATE);
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clk_disable(cmdq->clock);
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}
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@ -285,11 +290,11 @@ static irqreturn_t cmdq_irq_handler(int irq, void *dev)
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unsigned long irq_status, flags = 0L;
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int bit;
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irq_status = readl(cmdq->base + CMDQ_CURR_IRQ_STATUS) & CMDQ_IRQ_MASK;
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if (!(irq_status ^ CMDQ_IRQ_MASK))
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irq_status = readl(cmdq->base + CMDQ_CURR_IRQ_STATUS) & cmdq->irq_mask;
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if (!(irq_status ^ cmdq->irq_mask))
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return IRQ_NONE;
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for_each_clear_bit(bit, &irq_status, fls(CMDQ_IRQ_MASK)) {
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for_each_clear_bit(bit, &irq_status, cmdq->thread_nr) {
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struct cmdq_thread *thread = &cmdq->thread[bit];
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spin_lock_irqsave(&thread->chan->lock, flags);
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@ -473,6 +478,9 @@ static int cmdq_probe(struct platform_device *pdev)
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dev_err(dev, "failed to get irq\n");
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return -EINVAL;
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}
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cmdq->thread_nr = (u32)(unsigned long)of_device_get_match_data(dev);
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cmdq->irq_mask = GENMASK(cmdq->thread_nr - 1, 0);
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err = devm_request_irq(dev, cmdq->irq, cmdq_irq_handler, IRQF_SHARED,
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"mtk_cmdq", cmdq);
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if (err < 0) {
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@ -489,7 +497,6 @@ static int cmdq_probe(struct platform_device *pdev)
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return PTR_ERR(cmdq->clock);
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}
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cmdq->thread_nr = (u32)(unsigned long)of_device_get_match_data(dev);
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cmdq->mbox.dev = dev;
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cmdq->mbox.chans = devm_kcalloc(dev, cmdq->thread_nr,
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sizeof(*cmdq->mbox.chans), GFP_KERNEL);
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|
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@ -537,6 +544,7 @@ static const struct dev_pm_ops cmdq_pm_ops = {
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static const struct of_device_id cmdq_of_ids[] = {
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{.compatible = "mediatek,mt8173-gce", .data = (void *)16},
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{.compatible = "mediatek,mt8183-gce", .data = (void *)24},
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{}
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};
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|
|
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|||
|
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@ -28,7 +28,7 @@ static const struct regmap_config apcs_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.max_register = 0x1000,
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.max_register = 0xFFC,
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.fast_io = true,
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};
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|
|
@ -47,7 +47,6 @@ static const struct mbox_chan_ops qcom_apcs_ipc_ops = {
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static int qcom_apcs_ipc_probe(struct platform_device *pdev)
|
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{
|
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struct device_node *np = pdev->dev.of_node;
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struct qcom_apcs_ipc *apcs;
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struct regmap *regmap;
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struct resource *res;
|
||||
|
|
@ -55,6 +54,11 @@ static int qcom_apcs_ipc_probe(struct platform_device *pdev)
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void __iomem *base;
|
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unsigned long i;
|
||||
int ret;
|
||||
const struct of_device_id apcs_clk_match_table[] = {
|
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{ .compatible = "qcom,msm8916-apcs-kpss-global", },
|
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{ .compatible = "qcom,qcs404-apcs-apps-global", },
|
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{}
|
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};
|
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|
||||
apcs = devm_kzalloc(&pdev->dev, sizeof(*apcs), GFP_KERNEL);
|
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if (!apcs)
|
||||
|
|
@ -89,10 +93,11 @@ static int qcom_apcs_ipc_probe(struct platform_device *pdev)
|
|||
return ret;
|
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}
|
||||
|
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if (of_device_is_compatible(np, "qcom,msm8916-apcs-kpss-global")) {
|
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if (of_match_device(apcs_clk_match_table, &pdev->dev)) {
|
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apcs->clk = platform_device_register_data(&pdev->dev,
|
||||
"qcom-apcs-msm8916-clk",
|
||||
-1, NULL, 0);
|
||||
PLATFORM_DEVID_NONE,
|
||||
NULL, 0);
|
||||
if (IS_ERR(apcs->clk))
|
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dev_err(&pdev->dev, "failed to register APCS clk\n");
|
||||
}
|
||||
|
|
@ -118,7 +123,10 @@ static const struct of_device_id qcom_apcs_ipc_of_match[] = {
|
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{ .compatible = "qcom,msm8996-apcs-hmss-global", .data = (void *)16 },
|
||||
{ .compatible = "qcom,msm8998-apcs-hmss-global", .data = (void *)8 },
|
||||
{ .compatible = "qcom,qcs404-apcs-apps-global", .data = (void *)8 },
|
||||
{ .compatible = "qcom,sc7180-apss-shared", .data = (void *)12 },
|
||||
{ .compatible = "qcom,sdm845-apss-shared", .data = (void *)12 },
|
||||
{ .compatible = "qcom,sm8150-apss-shared", .data = (void *)12 },
|
||||
{ .compatible = "qcom,ipq8074-apcs-apps-global", .data = (void *)8 },
|
||||
{}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, qcom_apcs_ipc_of_match);
|
||||
|
|
|
|||
|
|
@ -0,0 +1,175 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2019 MediaTek Inc.
|
||||
* Author: Bibby Hsieh <bibby.hsieh@mediatek.com>
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_GCE_MT8183_H
|
||||
#define _DT_BINDINGS_GCE_MT8183_H
|
||||
|
||||
#define CMDQ_NO_TIMEOUT 0xffffffff
|
||||
|
||||
/* GCE HW thread priority */
|
||||
#define CMDQ_THR_PRIO_LOWEST 0
|
||||
#define CMDQ_THR_PRIO_HIGHEST 1
|
||||
|
||||
/* GCE SUBSYS */
|
||||
#define SUBSYS_1300XXXX 0
|
||||
#define SUBSYS_1400XXXX 1
|
||||
#define SUBSYS_1401XXXX 2
|
||||
#define SUBSYS_1402XXXX 3
|
||||
#define SUBSYS_1502XXXX 4
|
||||
#define SUBSYS_1880XXXX 5
|
||||
#define SUBSYS_1881XXXX 6
|
||||
#define SUBSYS_1882XXXX 7
|
||||
#define SUBSYS_1883XXXX 8
|
||||
#define SUBSYS_1884XXXX 9
|
||||
#define SUBSYS_1000XXXX 10
|
||||
#define SUBSYS_1001XXXX 11
|
||||
#define SUBSYS_1002XXXX 12
|
||||
#define SUBSYS_1003XXXX 13
|
||||
#define SUBSYS_1004XXXX 14
|
||||
#define SUBSYS_1005XXXX 15
|
||||
#define SUBSYS_1020XXXX 16
|
||||
#define SUBSYS_1028XXXX 17
|
||||
#define SUBSYS_1700XXXX 18
|
||||
#define SUBSYS_1701XXXX 19
|
||||
#define SUBSYS_1702XXXX 20
|
||||
#define SUBSYS_1703XXXX 21
|
||||
#define SUBSYS_1800XXXX 22
|
||||
#define SUBSYS_1801XXXX 23
|
||||
#define SUBSYS_1802XXXX 24
|
||||
#define SUBSYS_1804XXXX 25
|
||||
#define SUBSYS_1805XXXX 26
|
||||
#define SUBSYS_1808XXXX 27
|
||||
#define SUBSYS_180aXXXX 28
|
||||
#define SUBSYS_180bXXXX 29
|
||||
|
||||
#define CMDQ_EVENT_DISP_RDMA0_SOF 0
|
||||
#define CMDQ_EVENT_DISP_RDMA1_SOF 1
|
||||
#define CMDQ_EVENT_MDP_RDMA0_SOF 2
|
||||
#define CMDQ_EVENT_MDP_RSZ0_SOF 4
|
||||
#define CMDQ_EVENT_MDP_RSZ1_SOF 5
|
||||
#define CMDQ_EVENT_MDP_TDSHP_SOF 6
|
||||
#define CMDQ_EVENT_MDP_WROT0_SOF 7
|
||||
#define CMDQ_EVENT_MDP_WDMA0_SOF 8
|
||||
#define CMDQ_EVENT_DISP_OVL0_SOF 9
|
||||
#define CMDQ_EVENT_DISP_OVL0_2L_SOF 10
|
||||
#define CMDQ_EVENT_DISP_OVL1_2L_SOF 11
|
||||
#define CMDQ_EVENT_DISP_WDMA0_SOF 12
|
||||
#define CMDQ_EVENT_DISP_COLOR0_SOF 13
|
||||
#define CMDQ_EVENT_DISP_CCORR0_SOF 14
|
||||
#define CMDQ_EVENT_DISP_AAL0_SOF 15
|
||||
#define CMDQ_EVENT_DISP_GAMMA0_SOF 16
|
||||
#define CMDQ_EVENT_DISP_DITHER0_SOF 17
|
||||
#define CMDQ_EVENT_DISP_PWM0_SOF 18
|
||||
#define CMDQ_EVENT_DISP_DSI0_SOF 19
|
||||
#define CMDQ_EVENT_DISP_DPI0_SOF 20
|
||||
#define CMDQ_EVENT_DISP_RSZ_SOF 22
|
||||
#define CMDQ_EVENT_MDP_AAL_SOF 23
|
||||
#define CMDQ_EVENT_MDP_CCORR_SOF 24
|
||||
#define CMDQ_EVENT_DISP_DBI_SOF 25
|
||||
#define CMDQ_EVENT_DISP_RDMA0_EOF 26
|
||||
#define CMDQ_EVENT_DISP_RDMA1_EOF 27
|
||||
#define CMDQ_EVENT_MDP_RDMA0_EOF 28
|
||||
#define CMDQ_EVENT_MDP_RSZ0_EOF 30
|
||||
#define CMDQ_EVENT_MDP_RSZ1_EOF 31
|
||||
#define CMDQ_EVENT_MDP_TDSHP_EOF 32
|
||||
#define CMDQ_EVENT_MDP_WROT0_EOF 33
|
||||
#define CMDQ_EVENT_MDP_WDMA0_EOF 34
|
||||
#define CMDQ_EVENT_DISP_OVL0_EOF 35
|
||||
#define CMDQ_EVENT_DISP_OVL0_2L_EOF 36
|
||||
#define CMDQ_EVENT_DISP_OVL1_2L_EOF 37
|
||||
#define CMDQ_EVENT_DISP_WDMA0_EOF 38
|
||||
#define CMDQ_EVENT_DISP_COLOR0_EOF 39
|
||||
#define CMDQ_EVENT_DISP_CCORR0_EOF 40
|
||||
#define CMDQ_EVENT_DISP_AAL0_EOF 41
|
||||
#define CMDQ_EVENT_DISP_GAMMA0_EOF 42
|
||||
#define CMDQ_EVENT_DISP_DITHER0_EOF 43
|
||||
#define CMDQ_EVENT_DSI0_EOF 44
|
||||
#define CMDQ_EVENT_DPI0_EOF 45
|
||||
#define CMDQ_EVENT_DISP_RSZ_EOF 47
|
||||
#define CMDQ_EVENT_MDP_AAL_EOF 48
|
||||
#define CMDQ_EVENT_MDP_CCORR_EOF 49
|
||||
#define CMDQ_EVENT_DBI_EOF 50
|
||||
#define CMDQ_EVENT_MUTEX_STREAM_DONE0 130
|
||||
#define CMDQ_EVENT_MUTEX_STREAM_DONE1 131
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||||
#define CMDQ_EVENT_MUTEX_STREAM_DONE2 132
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||||
#define CMDQ_EVENT_MUTEX_STREAM_DONE3 133
|
||||
#define CMDQ_EVENT_MUTEX_STREAM_DONE4 134
|
||||
#define CMDQ_EVENT_MUTEX_STREAM_DONE5 135
|
||||
#define CMDQ_EVENT_MUTEX_STREAM_DONE6 136
|
||||
#define CMDQ_EVENT_MUTEX_STREAM_DONE7 137
|
||||
#define CMDQ_EVENT_MUTEX_STREAM_DONE8 138
|
||||
#define CMDQ_EVENT_MUTEX_STREAM_DONE9 139
|
||||
#define CMDQ_EVENT_MUTEX_STREAM_DONE10 140
|
||||
#define CMDQ_EVENT_MUTEX_STREAM_DONE11 141
|
||||
#define CMDQ_EVENT_DISP_RDMA0_BUF_UNDERRUN_EVEN 142
|
||||
#define CMDQ_EVENT_DISP_RDMA1_BUF_UNDERRUN_EVEN 143
|
||||
#define CMDQ_EVENT_DSI0_TE_EVENT 144
|
||||
#define CMDQ_EVENT_DSI0_IRQ_EVENT 145
|
||||
#define CMDQ_EVENT_DSI0_DONE_EVENT 146
|
||||
#define CMDQ_EVENT_DISP_WDMA0_SW_RST_DONE 150
|
||||
#define CMDQ_EVENT_MDP_WDMA_SW_RST_DONE 151
|
||||
#define CMDQ_EVENT_MDP_WROT0_SW_RST_DONE 152
|
||||
#define CMDQ_EVENT_MDP_RDMA0_SW_RST_DONE 154
|
||||
#define CMDQ_EVENT_DISP_OVL0_FRAME_RST_DONE_PULE 155
|
||||
#define CMDQ_EVENT_DISP_OVL0_2L_FRAME_RST_DONE_ULSE 156
|
||||
#define CMDQ_EVENT_DISP_OVL1_2L_FRAME_RST_DONE_ULSE 157
|
||||
#define CMDQ_EVENT_ISP_FRAME_DONE_P2_0 257
|
||||
#define CMDQ_EVENT_ISP_FRAME_DONE_P2_1 258
|
||||
#define CMDQ_EVENT_ISP_FRAME_DONE_P2_2 259
|
||||
#define CMDQ_EVENT_ISP_FRAME_DONE_P2_3 260
|
||||
#define CMDQ_EVENT_ISP_FRAME_DONE_P2_4 261
|
||||
#define CMDQ_EVENT_ISP_FRAME_DONE_P2_5 262
|
||||
#define CMDQ_EVENT_ISP_FRAME_DONE_P2_6 263
|
||||
#define CMDQ_EVENT_ISP_FRAME_DONE_P2_7 264
|
||||
#define CMDQ_EVENT_ISP_FRAME_DONE_P2_8 265
|
||||
#define CMDQ_EVENT_ISP_FRAME_DONE_P2_9 266
|
||||
#define CMDQ_EVENT_ISP_FRAME_DONE_P2_10 267
|
||||
#define CMDQ_EVENT_ISP_FRAME_DONE_P2_11 268
|
||||
#define CMDQ_EVENT_ISP_FRAME_DONE_P2_12 269
|
||||
#define CMDQ_EVENT_ISP_FRAME_DONE_P2_13 270
|
||||
#define CMDQ_EVENT_ISP_FRAME_DONE_P2_14 271
|
||||
#define CMDQ_EVENT_ISP_FRAME_DONE_P2_15 272
|
||||
#define CMDQ_EVENT_ISP_FRAME_DONE_P2_16 273
|
||||
#define CMDQ_EVENT_ISP_FRAME_DONE_P2_17 274
|
||||
#define CMDQ_EVENT_ISP_FRAME_DONE_P2_18 275
|
||||
#define CMDQ_EVENT_AMD_FRAME_DONE 276
|
||||
#define CMDQ_EVENT_DVE_DONE 277
|
||||
#define CMDQ_EVENT_WMFE_DONE 278
|
||||
#define CMDQ_EVENT_RSC_DONE 279
|
||||
#define CMDQ_EVENT_MFB_DONE 280
|
||||
#define CMDQ_EVENT_WPE_A_DONE 281
|
||||
#define CMDQ_EVENT_SPE_B_DONE 282
|
||||
#define CMDQ_EVENT_OCC_DONE 283
|
||||
#define CMDQ_EVENT_VENC_CMDQ_FRAME_DONE 289
|
||||
#define CMDQ_EVENT_JPG_ENC_CMDQ_DONE 290
|
||||
#define CMDQ_EVENT_JPG_DEC_CMDQ_DONE 291
|
||||
#define CMDQ_EVENT_VENC_CMDQ_MB_DONE 292
|
||||
#define CMDQ_EVENT_VENC_CMDQ_128BYTE_DONE 293
|
||||
#define CMDQ_EVENT_ISP_FRAME_DONE_A 321
|
||||
#define CMDQ_EVENT_ISP_FRAME_DONE_B 322
|
||||
#define CMDQ_EVENT_CAMSV0_PASS1_DONE 323
|
||||
#define CMDQ_EVENT_CAMSV1_PASS1_DONE 324
|
||||
#define CMDQ_EVENT_CAMSV2_PASS1_DONE 325
|
||||
#define CMDQ_EVENT_TSF_DONE 326
|
||||
#define CMDQ_EVENT_SENINF_CAM0_FIFO_FULL 327
|
||||
#define CMDQ_EVENT_SENINF_CAM1_FIFO_FULL 328
|
||||
#define CMDQ_EVENT_SENINF_CAM2_FIFO_FULL 329
|
||||
#define CMDQ_EVENT_SENINF_CAM3_FIFO_FULL 330
|
||||
#define CMDQ_EVENT_SENINF_CAM4_FIFO_FULL 331
|
||||
#define CMDQ_EVENT_SENINF_CAM5_FIFO_FULL 332
|
||||
#define CMDQ_EVENT_SENINF_CAM6_FIFO_FULL 333
|
||||
#define CMDQ_EVENT_SENINF_CAM7_FIFO_FULL 334
|
||||
#define CMDQ_EVENT_IPU_CORE0_DONE0 353
|
||||
#define CMDQ_EVENT_IPU_CORE0_DONE1 354
|
||||
#define CMDQ_EVENT_IPU_CORE0_DONE2 355
|
||||
#define CMDQ_EVENT_IPU_CORE0_DONE3 356
|
||||
#define CMDQ_EVENT_IPU_CORE1_DONE0 385
|
||||
#define CMDQ_EVENT_IPU_CORE1_DONE1 386
|
||||
#define CMDQ_EVENT_IPU_CORE1_DONE2 387
|
||||
#define CMDQ_EVENT_IPU_CORE1_DONE3 388
|
||||
|
||||
#endif
|
||||
|
|
@ -20,6 +20,9 @@
|
|||
#define CMDQ_WFE_WAIT BIT(15)
|
||||
#define CMDQ_WFE_WAIT_VALUE 0x1
|
||||
|
||||
/** cmdq event maximum */
|
||||
#define CMDQ_MAX_EVENT 0x3ff
|
||||
|
||||
/*
|
||||
* CMDQ_CODE_MASK:
|
||||
* set write mask
|
||||
|
|
|
|||
|
|
@ -13,9 +13,6 @@
|
|||
|
||||
#define CMDQ_NO_TIMEOUT 0xffffffffu
|
||||
|
||||
/** cmdq event maximum */
|
||||
#define CMDQ_MAX_EVENT 0x3ff
|
||||
|
||||
struct cmdq_pkt;
|
||||
|
||||
struct cmdq_client {
|
||||
|
|
|
|||
Loading…
Reference in New Issue