ARM: dts: aspeed: Add LPC and child devices
Ensure the ordering is correct and add all of the children in the SoC device trees for the ast2400 and ast2500. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
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@ -225,6 +225,41 @@
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status = "disabled";
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};
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lpc: lpc@1e789000 {
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compatible = "aspeed,ast2400-lpc", "simple-mfd";
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reg = <0x1e789000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x1e789000 0x1000>;
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lpc_bmc: lpc-bmc@0 {
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compatible = "aspeed,ast2400-lpc-bmc";
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reg = <0x0 0x80>;
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};
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lpc_host: lpc-host@80 {
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compatible = "aspeed,ast2400-lpc-host", "simple-mfd", "syscon";
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reg = <0x80 0x1e0>;
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reg-io-width = <4>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x80 0x1e0>;
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lpc_ctrl: lpc-ctrl@0 {
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compatible = "aspeed,ast2400-lpc-ctrl";
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reg = <0x0 0x80>;
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status = "disabled";
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};
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lhc: lhc@20 {
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compatible = "aspeed,ast2400-lhc";
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reg = <0x20 0x24 0x48 0x8>;
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};
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};
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};
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uart2: serial@1e78d000 {
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compatible = "ns16550a";
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reg = <0x1e78d000 0x20>;
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@ -265,6 +265,16 @@
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status = "disabled";
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};
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vuart: serial@1e787000 {
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compatible = "aspeed,ast2500-vuart";
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reg = <0x1e787000 0x40>;
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reg-shift = <2>;
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interrupts = <10>;
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clocks = <&clk_uart>;
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no-loopback-test;
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status = "disabled";
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};
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lpc: lpc@1e789000 {
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compatible = "aspeed,ast2500-lpc", "simple-mfd";
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reg = <0x1e789000 0x1000>;
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@ -288,6 +298,13 @@
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reg-io-width = <4>;
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lpc_ctrl: lpc-ctrl@0 {
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compatible = "aspeed,ast2500-lpc-ctrl";
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reg = <0x0 0x80>;
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status = "disabled";
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};
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lhc: lhc@20 {
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compatible = "aspeed,ast2500-lhc";
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reg = <0x20 0x24 0x48 0x8>;
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@ -295,16 +312,6 @@
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};
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};
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vuart: serial@1e787000 {
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compatible = "aspeed,ast2500-vuart";
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reg = <0x1e787000 0x40>;
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reg-shift = <2>;
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interrupts = <10>;
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clocks = <&clk_uart>;
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no-loopback-test;
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status = "disabled";
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};
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uart2: serial@1e78d000 {
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compatible = "ns16550a";
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reg = <0x1e78d000 0x20>;
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