staging: brcm80211: further simplified register access macro's
The SELECT_BUS_READ and SELECT_BUS_WRITE macro's always select a (sdio) bus operation for fullmac, and a memory operation for softmac. Thus they can be removed by expanding them in place. Signed-off-by: Roland Vossen <rvossen@broadcom.com> Reviewed-by: Arend van Spriel <arend@broadcom.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Roland Vossen
Greg Kroah-Hartman
parent
4489518533
commit
b61a4be59b
|
|
@ -39,102 +39,30 @@
|
|||
#endif
|
||||
#endif
|
||||
|
||||
#if defined(BCMSDIO)
|
||||
#define SELECT_BUS_WRITE(mmap_op, bus_op) bus_op
|
||||
#define SELECT_BUS_READ(mmap_op, bus_op) bus_op
|
||||
#else
|
||||
#define SELECT_BUS_WRITE(mmap_op, bus_op) mmap_op
|
||||
#define SELECT_BUS_READ(mmap_op, bus_op) mmap_op
|
||||
#endif
|
||||
|
||||
/* register access macros */
|
||||
#ifndef __BIG_ENDIAN
|
||||
#ifndef __mips__
|
||||
#define R_REG(r) (\
|
||||
SELECT_BUS_READ(sizeof(*(r)) == sizeof(u8) ? \
|
||||
readb((volatile u8*)(r)) : \
|
||||
sizeof(*(r)) == sizeof(u16) ? readw((volatile u16*)(r)) : \
|
||||
readl((volatile u32*)(r)), bcmsdh_reg_read(NULL, (unsigned long)r, sizeof(*r))) \
|
||||
)
|
||||
#define R_REG(r) \
|
||||
bcmsdh_reg_read(NULL, (unsigned long)r, sizeof(*r))
|
||||
#else /* __mips__ */
|
||||
#define R_REG(r) (\
|
||||
SELECT_BUS_READ( \
|
||||
({ \
|
||||
__typeof(*(r)) __osl_v; \
|
||||
__asm__ __volatile__("sync"); \
|
||||
switch (sizeof(*(r))) { \
|
||||
case sizeof(u8): \
|
||||
__osl_v = readb((volatile u8*)(r)); \
|
||||
break; \
|
||||
case sizeof(u16): \
|
||||
__osl_v = readw((volatile u16*)(r)); \
|
||||
break; \
|
||||
case sizeof(u32): \
|
||||
__osl_v = \
|
||||
readl((volatile u32*)(r)); \
|
||||
break; \
|
||||
} \
|
||||
__asm__ __volatile__("sync"); \
|
||||
__osl_v; \
|
||||
}), \
|
||||
({ \
|
||||
__typeof(*(r)) __osl_v; \
|
||||
__asm__ __volatile__("sync"); \
|
||||
__osl_v = bcmsdh_reg_read(NULL, (unsigned long)r, sizeof(*r)); \
|
||||
__asm__ __volatile__("sync"); \
|
||||
__osl_v; \
|
||||
})) \
|
||||
)
|
||||
#define R_REG(r) \
|
||||
({ \
|
||||
__typeof(*(r)) __osl_v; \
|
||||
__asm__ __volatile__("sync"); \
|
||||
__osl_v = bcmsdh_reg_read(NULL, (unsigned long)r, sizeof(*r)); \
|
||||
__asm__ __volatile__("sync"); \
|
||||
__osl_v; \
|
||||
})
|
||||
#endif /* __mips__ */
|
||||
|
||||
#define W_REG(r, v) do { \
|
||||
SELECT_BUS_WRITE( \
|
||||
switch (sizeof(*(r))) { \
|
||||
case sizeof(u8): \
|
||||
writeb((u8)(v), (volatile u8*)(r)); break; \
|
||||
case sizeof(u16): \
|
||||
writew((u16)(v), (volatile u16*)(r)); break; \
|
||||
case sizeof(u32): \
|
||||
writel((u32)(v), (volatile u32*)(r)); break; \
|
||||
}, \
|
||||
bcmsdh_reg_write(NULL, (unsigned long)r, sizeof(*r), (v))); \
|
||||
bcmsdh_reg_write(NULL, (unsigned long)r, sizeof(*r), (v)); \
|
||||
} while (0)
|
||||
#else /* __BIG_ENDIAN */
|
||||
#define R_REG(r) (\
|
||||
SELECT_BUS_READ( \
|
||||
({ \
|
||||
__typeof(*(r)) __osl_v; \
|
||||
switch (sizeof(*(r))) { \
|
||||
case sizeof(u8): \
|
||||
__osl_v = \
|
||||
readb((volatile u8*)((r)^3)); \
|
||||
break; \
|
||||
case sizeof(u16): \
|
||||
__osl_v = \
|
||||
readw((volatile u16*)((r)^2)); \
|
||||
break; \
|
||||
case sizeof(u32): \
|
||||
__osl_v = readl((volatile u32*)(r)); \
|
||||
break; \
|
||||
} \
|
||||
__osl_v; \
|
||||
}), \
|
||||
bcmsdh_reg_read(NULL, (unsigned long)r, sizeof(*r))) \
|
||||
)
|
||||
#define R_REG(r) \
|
||||
bcmsdh_reg_read(NULL, (unsigned long)r, sizeof(*r))
|
||||
#define W_REG(r, v) do { \
|
||||
SELECT_BUS_WRITE( \
|
||||
switch (sizeof(*(r))) { \
|
||||
case sizeof(u8): \
|
||||
writeb((u8)(v), \
|
||||
(volatile u8*)((r)^3)); break; \
|
||||
case sizeof(u16): \
|
||||
writew((u16)(v), \
|
||||
(volatile u16*)((r)^2)); break; \
|
||||
case sizeof(u32): \
|
||||
writel((u32)(v), \
|
||||
(volatile u32*)(r)); break; \
|
||||
}, \
|
||||
bcmsdh_reg_write(NULL, (unsigned long)r, sizeof(*r), v)); \
|
||||
bcmsdh_reg_write(NULL, (unsigned long)r, sizeof(*r), v); \
|
||||
} while (0)
|
||||
#endif /* __BIG_ENDIAN */
|
||||
|
||||
|
|
@ -155,8 +83,6 @@
|
|||
#define SET_REG(r, mask, val) \
|
||||
W_REG((r), ((R_REG(r) & ~(mask)) | (val)))
|
||||
|
||||
|
||||
|
||||
#ifdef DHD_DEBUG
|
||||
|
||||
/* ARM trap handling */
|
||||
|
|
|
|||
|
|
@ -48,56 +48,39 @@ do { \
|
|||
#endif
|
||||
#endif
|
||||
|
||||
#if defined(BCMSDIO)
|
||||
#define SELECT_BUS_WRITE(mmap_op, bus_op) bus_op
|
||||
#define SELECT_BUS_READ(mmap_op, bus_op) bus_op
|
||||
#else
|
||||
#define SELECT_BUS_WRITE(mmap_op, bus_op) mmap_op
|
||||
#define SELECT_BUS_READ(mmap_op, bus_op) mmap_op
|
||||
#endif
|
||||
|
||||
/* register access macros */
|
||||
#ifndef __BIG_ENDIAN
|
||||
#ifndef __mips__
|
||||
#define R_REG(r) (\
|
||||
SELECT_BUS_READ(sizeof(*(r)) == sizeof(u8) ? \
|
||||
readb((volatile u8*)(r)) : \
|
||||
sizeof(*(r)) == sizeof(u16) ? readw((volatile u16*)(r)) : \
|
||||
readl((volatile u32*)(r)), bcmsdh_reg_read(NULL, (unsigned long)r, sizeof(*r))) \
|
||||
)
|
||||
#define R_REG(r) \
|
||||
({\
|
||||
sizeof(*(r)) == sizeof(u8) ? \
|
||||
readb((volatile u8*)(r)) : \
|
||||
sizeof(*(r)) == sizeof(u16) ? readw((volatile u16*)(r)) : \
|
||||
readl((volatile u32*)(r)); \
|
||||
})
|
||||
#else /* __mips__ */
|
||||
#define R_REG(r) (\
|
||||
SELECT_BUS_READ( \
|
||||
({ \
|
||||
__typeof(*(r)) __osl_v; \
|
||||
__asm__ __volatile__("sync"); \
|
||||
switch (sizeof(*(r))) { \
|
||||
case sizeof(u8): \
|
||||
__osl_v = readb((volatile u8*)(r)); \
|
||||
break; \
|
||||
case sizeof(u16): \
|
||||
__osl_v = readw((volatile u16*)(r)); \
|
||||
break; \
|
||||
case sizeof(u32): \
|
||||
__osl_v = \
|
||||
readl((volatile u32*)(r)); \
|
||||
break; \
|
||||
} \
|
||||
__asm__ __volatile__("sync"); \
|
||||
__osl_v; \
|
||||
}), \
|
||||
({ \
|
||||
__typeof(*(r)) __osl_v; \
|
||||
__asm__ __volatile__("sync"); \
|
||||
__osl_v = bcmsdh_reg_read(NULL, (unsigned long)r, sizeof(*r)); \
|
||||
__asm__ __volatile__("sync"); \
|
||||
__osl_v; \
|
||||
})) \
|
||||
)
|
||||
#define R_REG(r) \
|
||||
({ \
|
||||
__typeof(*(r)) __osl_v; \
|
||||
__asm__ __volatile__("sync"); \
|
||||
switch (sizeof(*(r))) { \
|
||||
case sizeof(u8): \
|
||||
__osl_v = readb((volatile u8*)(r)); \
|
||||
break; \
|
||||
case sizeof(u16): \
|
||||
__osl_v = readw((volatile u16*)(r)); \
|
||||
break; \
|
||||
case sizeof(u32): \
|
||||
__osl_v = \
|
||||
readl((volatile u32*)(r)); \
|
||||
break; \
|
||||
} \
|
||||
__asm__ __volatile__("sync"); \
|
||||
__osl_v; \
|
||||
})
|
||||
#endif /* __mips__ */
|
||||
|
||||
#define W_REG(r, v) do { \
|
||||
SELECT_BUS_WRITE( \
|
||||
switch (sizeof(*(r))) { \
|
||||
case sizeof(u8): \
|
||||
writeb((u8)(v), (volatile u8*)(r)); break; \
|
||||
|
|
@ -105,33 +88,29 @@ do { \
|
|||
writew((u16)(v), (volatile u16*)(r)); break; \
|
||||
case sizeof(u32): \
|
||||
writel((u32)(v), (volatile u32*)(r)); break; \
|
||||
}, \
|
||||
bcmsdh_reg_write(NULL, (unsigned long)r, sizeof(*r), (v))); \
|
||||
}; \
|
||||
} while (0)
|
||||
#else /* __BIG_ENDIAN */
|
||||
#define R_REG(r) (\
|
||||
SELECT_BUS_READ( \
|
||||
({ \
|
||||
__typeof(*(r)) __osl_v; \
|
||||
switch (sizeof(*(r))) { \
|
||||
case sizeof(u8): \
|
||||
__osl_v = \
|
||||
readb((volatile u8*)((r)^3)); \
|
||||
break; \
|
||||
case sizeof(u16): \
|
||||
__osl_v = \
|
||||
readw((volatile u16*)((r)^2)); \
|
||||
break; \
|
||||
case sizeof(u32): \
|
||||
__osl_v = readl((volatile u32*)(r)); \
|
||||
break; \
|
||||
} \
|
||||
__osl_v; \
|
||||
}), \
|
||||
bcmsdh_reg_read(NULL, (unsigned long)r, sizeof(*r))) \
|
||||
)
|
||||
#define R_REG(r) \
|
||||
({ \
|
||||
__typeof(*(r)) __osl_v; \
|
||||
switch (sizeof(*(r))) { \
|
||||
case sizeof(u8): \
|
||||
__osl_v = \
|
||||
readb((volatile u8*)((r)^3)); \
|
||||
break; \
|
||||
case sizeof(u16): \
|
||||
__osl_v = \
|
||||
readw((volatile u16*)((r)^2)); \
|
||||
break; \
|
||||
case sizeof(u32): \
|
||||
__osl_v = readl((volatile u32*)(r)); \
|
||||
break; \
|
||||
} \
|
||||
__osl_v; \
|
||||
})
|
||||
|
||||
#define W_REG(r, v) do { \
|
||||
SELECT_BUS_WRITE( \
|
||||
switch (sizeof(*(r))) { \
|
||||
case sizeof(u8): \
|
||||
writeb((u8)(v), \
|
||||
|
|
@ -142,8 +121,7 @@ do { \
|
|||
case sizeof(u32): \
|
||||
writel((u32)(v), \
|
||||
(volatile u32*)(r)); break; \
|
||||
}, \
|
||||
bcmsdh_reg_write(NULL, (unsigned long)r, sizeof(*r), v)); \
|
||||
} \
|
||||
} while (0)
|
||||
#endif /* __BIG_ENDIAN */
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue