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tree-wide: fix comment/printk typos 

"gadget", "through", "command", "maintain", "maintain", "controller", "address",
"between", "initiali[zs]e", "instead", "function", "select", "already",
"equal", "access", "management", "hierarchy", "registration", "interest",
"relative", "memory", "offset", "already",

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Jiri Kosina <jkosina@suse.cz>
This commit is contained in:
Uwe Kleine-König 2010-11-01 15:38:34 -04:00 committed by Jiri Kosina
parent 6aaccece1c
commit b595076a18
207 changed files with 261 additions and 261 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Documentation/DocBook/mtdnand.tmpl
View File

@ -250,7 +250,7 @@ static void board_hwcontrol(struct mtd_info *mtd, int cmd)
<title>Device ready function</title>
<para>
If the hardware interface has the ready busy pin of the NAND chip connected to a
GPIO or other accesible I/O pin, this function is used to read back the state of the
GPIO or other accessible I/O pin, this function is used to read back the state of the
pin. The function has no arguments and should return 0, if the device is busy (R/B pin
is low) and 1, if the device is ready (R/B pin is high).
If the hardware interface does not give access to the ready busy pin, then

2
Documentation/cgroups/cgroup_event_listener.c
View File

@ -91,7 +91,7 @@ int main(int argc, char **argv)
if (ret == -1) {
perror("cgroup.event_control "
"is not accessable any more");
"is not accessible any more");
break;
}

2
Documentation/cgroups/memcg_test.txt
View File

@ -398,7 +398,7 @@ Under below explanation, we assume CONFIG_MEM_RES_CTRL_SWAP=y.
written to move_charge_at_immigrate.
9.10 Memory thresholds
Memory controler implements memory thresholds using cgroups notification
Memory controller implements memory thresholds using cgroups notification
API. You can use Documentation/cgroups/cgroup_event_listener.c to test
it.

2
Documentation/kprobes.txt
View File

@ -598,7 +598,7 @@ a 5-byte jump instruction. So there are several limitations.
a) The instructions in DCR must be relocatable.
b) The instructions in DCR must not include a call instruction.
c) JTPR must not be targeted by any jump or call instruction.
d) DCR must not straddle the border betweeen functions.
d) DCR must not straddle the border between functions.
Anyway, these limitations are checked by the in-kernel instruction
decoder, so you don't need to worry about that.

2
Documentation/kvm/api.txt
View File

@ -874,7 +874,7 @@ Possible values are:
- KVM_MP_STATE_HALTED: the vcpu has executed a HLT instruction and
is waiting for an interrupt
- KVM_MP_STATE_SIPI_RECEIVED: the vcpu has just received a SIPI (vector
accesible via KVM_GET_VCPU_EVENTS)
accessible via KVM_GET_VCPU_EVENTS)
This ioctl is only useful after KVM_CREATE_IRQCHIP. Without an in-kernel
irqchip, the multiprocessing state must be maintained by userspace.

2
Documentation/networking/caif/spi_porting.txt
View File

@ -32,7 +32,7 @@ the physical hardware, both with regard to SPI and to GPIOs.
This function is called by the CAIF SPI interface to give
you a chance to set up your hardware to be ready to receive
a stream of data from the master. The xfer structure contains
both physical and logical adresses, as well as the total length
both physical and logical addresses, as well as the total length
of the transfer in both directions.The dev parameter can be used
to map to different CAIF SPI slave devices.

2
Documentation/powerpc/booting-without-of.txt
View File

@ -1098,7 +1098,7 @@ supported currently at the toplevel.
* an arbitrary array of bytes
*/
childnode@addresss { /* define a child node named "childnode"
childnode@address { /* define a child node named "childnode"
* whose unit name is "childnode at
* address"
*/

2
Documentation/scsi/ChangeLog.lpfc
View File

@ -573,7 +573,7 @@ Changes from 20041018 to 20041123
* Backround nodev_timeout processing to DPC This enables us to
unblock (stop dev_loss_tmo) when appopriate.
* Fix array discovery with multiple luns. The max_luns was 0 at
the time the host structure was intialized. lpfc_cfg_params
the time the host structure was initialized. lpfc_cfg_params
then set the max_luns to the correct value afterwards.
* Remove unused define LPFC_MAX_LUN and set the default value of
lpfc_max_lun parameter to 512.

2
Documentation/timers/timer_stats.txt
View File

@ -19,7 +19,7 @@ Linux system over a sample period:
- the pid of the task(process) which initialized the timer
- the name of the process which initialized the timer
- the function where the timer was intialized
- the function where the timer was initialized
- the callback function which is associated to the timer
- the number of events (callbacks)

2
arch/arm/common/it8152.c
View File

@ -236,7 +236,7 @@ static struct resource it8152_mem = {
/*
* The following functions are needed for DMA bouncing.
* ITE8152 chip can addrees up to 64MByte, so all the devices
* ITE8152 chip can address up to 64MByte, so all the devices
* connected to ITE8152 (PCI and USB) should have limited DMA window
*/

2
arch/arm/common/vic.c
View File

@ -70,7 +70,7 @@ static inline struct vic_device *to_vic(struct sys_device *sys)
* vic_init2 - common initialisation code
* @base: Base of the VIC.
*
* Common initialisation code for registeration
* Common initialisation code for registration
* and resume.
*/
static void vic_init2(void __iomem *base)

6
arch/arm/mach-at91/board-ecbat91.c
View File

@ -128,17 +128,17 @@ static struct spi_board_info __initdata ecb_at91spi_devices[] = {
.platform_data = &my_flash0_platform,
#endif
},
{ /* User accessable spi - cs1 (250KHz) */
{ /* User accessible spi - cs1 (250KHz) */
.modalias = "spi-cs1",
.chip_select = 1,
.max_speed_hz = 250 * 1000,
},
{ /* User accessable spi - cs2 (1MHz) */
{ /* User accessible spi - cs2 (1MHz) */
.modalias = "spi-cs2",
.chip_select = 2,
.max_speed_hz = 1 * 1000 * 1000,
},
{ /* User accessable spi - cs3 (10MHz) */
{ /* User accessible spi - cs3 (10MHz) */
.modalias = "spi-cs3",
.chip_select = 3,
.max_speed_hz = 10 * 1000 * 1000,

2
arch/arm/mach-bcmring/csp/chipc/chipcHw.c
View File

@ -757,7 +757,7 @@ static int chipcHw_divide(int num, int denom)
t = t << 1;
}
/* Intialize the result */
/* Initialize the result */
r = 0;
do {

2
arch/arm/mach-bcmring/csp/dmac/dmacHw.c
View File

@ -893,7 +893,7 @@ int dmacHw_setDataDescriptor(dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration
*/
/****************************************************************************/
uint32_t dmacHw_getDmaControllerAttribute(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */
dmacHw_CONTROLLER_ATTRIB_e attr /* [ IN ] DMA Controler attribute of type dmacHw_CONTROLLER_ATTRIB_e */
dmacHw_CONTROLLER_ATTRIB_e attr /* [ IN ] DMA Controller attribute of type dmacHw_CONTROLLER_ATTRIB_e */
) {
dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);

2
arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c
View File

@ -316,7 +316,7 @@ static void DisplayDescRing(void *pDescriptor, /* [ IN ] Descriptor buffer */
/**
* @brief Check if DMA channel is the flow controller
*
* @return 1 : If DMA is a flow controler
* @return 1 : If DMA is a flow controller
* 0 : Peripheral is the flow controller
*
* @note

2
arch/arm/mach-bcmring/csp/tmr/tmrHw.c
View File

@ -558,7 +558,7 @@ static int tmrHw_divide(int num, int denom)
t = t << 1;
}
/* Intialize the result */
/* Initialize the result */
r = 0;
do {

2
arch/arm/mach-bcmring/dma.c
View File

@ -671,7 +671,7 @@ static int ConfigChannel(DMA_Handle_t handle)
/****************************************************************************/
/**
* Intializes all of the data structures associated with the DMA.
* Initializes all of the data structures associated with the DMA.
* @return
* >= 0 - Initialization was successfull.
*

2
arch/arm/mach-bcmring/include/csp/dmacHw.h
View File

@ -590,7 +590,7 @@ void dmacHw_printDebugInfo(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle
*/
/****************************************************************************/
uint32_t dmacHw_getDmaControllerAttribute(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */
dmacHw_CONTROLLER_ATTRIB_e attr /* [ IN ] DMA Controler attribute of type dmacHw_CONTROLLER_ATTRIB_e */
dmacHw_CONTROLLER_ATTRIB_e attr /* [ IN ] DMA Controller attribute of type dmacHw_CONTROLLER_ATTRIB_e */
);
#endif /* _DMACHW_H */

2
arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h
View File

@ -28,7 +28,7 @@
/* Data type for DMA Link List Item */
typedef struct {
uint32_t sar; /* Source Adress Register.
uint32_t sar; /* Source Address Register.
Address must be aligned to CTLx.SRC_TR_WIDTH. */
uint32_t dar; /* Destination Address Register.
Address must be aligned to CTLx.DST_TR_WIDTH. */

2
arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h
View File

@ -35,7 +35,7 @@ typedef struct {
/* Data type representing DMA channel registers */
typedef struct {
dmacHw_REG64_t ChannelSar; /* Source Adress Register. 64 bits (upper 32 bits are reserved)
dmacHw_REG64_t ChannelSar; /* Source Address Register. 64 bits (upper 32 bits are reserved)
Address must be aligned to CTLx.SRC_TR_WIDTH.
*/
dmacHw_REG64_t ChannelDar; /* Destination Address Register.64 bits (upper 32 bits are reserved)

2
arch/arm/mach-gemini/include/mach/hardware.h
View File

@ -33,7 +33,7 @@
#define GEMINI_LPC_HOST_BASE 0x47000000
#define GEMINI_LPC_IO_BASE 0x47800000
#define GEMINI_INTERRUPT_BASE 0x48000000
/* TODO: Different interrupt controlers when SMP
/* TODO: Different interrupt controllers when SMP
* #define GEMINI_INTERRUPT0_BASE 0x48000000
* #define GEMINI_INTERRUPT1_BASE 0x49000000
*/

2
arch/arm/mach-msm/io.c
View File

@ -153,7 +153,7 @@ __msm_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype)
{
if (mtype == MT_DEVICE) {
/* The peripherals in the 88000000 - D0000000 range
* are only accessable by type MT_DEVICE_NONSHARED.
* are only accessible by type MT_DEVICE_NONSHARED.
* Adjust mtype as necessary to make this "just work."
*/
if ((phys_addr >= 0x88000000) && (phys_addr < 0xD0000000))

2
arch/arm/mach-omap2/cpuidle34xx.c
View File

@ -252,7 +252,7 @@ static int omap3_enter_idle_bm(struct cpuidle_device *dev,
* FIXME: we currently manage device-specific idle states
* for PER and CORE in combination with CPU-specific
* idle states. This is wrong, and device-specific
* idle managment needs to be separated out into
* idle management needs to be separated out into
* its own code.
*/

2
arch/arm/mach-omap2/serial.c
View File

@ -843,7 +843,7 @@ void __init omap_serial_init_port(int port)
}
/**
* omap_serial_init() - intialize all supported serial ports
* omap_serial_init() - initialize all supported serial ports
*
* Initializes all available UARTs as serial ports. Platforms
* can call this function when they want to have default behaviour

2
arch/arm/mach-pxa/mxm8x10.c
View File

@ -337,7 +337,7 @@ void __init mxm_8x10_mmc_init(void)
}
#endif
/* USB Open Host Controler Interface */
/* USB Open Host Controller Interface */
static struct pxaohci_platform_data mxm_8x10_ohci_platform_data = {
.port_mode = PMM_NPS_MODE,
.flags = ENABLE_PORT_ALL

2
arch/arm/mach-s3c64xx/dma.c
View File

@ -740,7 +740,7 @@ static int __init s3c64xx_dma_init(void)
/* Set all DMA configuration to be DMA, not SDMA */
writel(0xffffff, S3C_SYSREG(0x110));
/* Register standard DMA controlers */
/* Register standard DMA controllers */
s3c64xx_dma_init1(0, DMACH_UART0, IRQ_DMA0, 0x75000000);
s3c64xx_dma_init1(8, DMACH_PCM1_TX, IRQ_DMA1, 0x75100000);

4
arch/arm/mach-spear3xx/spear300.c
View File

@ -371,7 +371,7 @@ struct pmx_driver pmx_driver = {
};
/* Add spear300 specific devices here */
/* arm gpio1 device registeration */
/* arm gpio1 device registration */
static struct pl061_platform_data gpio1_plat_data = {
.gpio_base = 8,
.irq_base = SPEAR_GPIO1_INT_BASE,
@ -451,7 +451,7 @@ void __init spear300_init(void)
/* call spear3xx family common init function */
spear3xx_init();
/* shared irq registeration */
/* shared irq registration */
shirq_ras1.regs.base =
ioremap(SPEAR300_TELECOM_BASE, SPEAR300_TELECOM_REG_SIZE);
if (shirq_ras1.regs.base) {

2
arch/arm/mach-spear3xx/spear310.c
View File

@ -266,7 +266,7 @@ void __init spear310_init(void)
/* call spear3xx family common init function */
spear3xx_init();
/* shared irq registeration */
/* shared irq registration */
base = ioremap(SPEAR310_SOC_CONFIG_BASE, SPEAR310_SOC_CONFIG_SIZE);
if (base) {
/* shirq 1 */

2
arch/arm/mach-spear3xx/spear320.c
View File

@ -519,7 +519,7 @@ void __init spear320_init(void)
/* call spear3xx family common init function */
spear3xx_init();
/* shared irq registeration */
/* shared irq registration */
base = ioremap(SPEAR320_SOC_CONFIG_BASE, SPEAR320_SOC_CONFIG_SIZE);
if (base) {
/* shirq 1 */

6
arch/arm/mach-spear3xx/spear3xx.c
View File

@ -22,7 +22,7 @@
#include <mach/spear.h>
/* Add spear3xx machines common devices here */
/* gpio device registeration */
/* gpio device registration */
static struct pl061_platform_data gpio_plat_data = {
.gpio_base = 0,
.irq_base = SPEAR_GPIO_INT_BASE,
@ -41,7 +41,7 @@ struct amba_device gpio_device = {
.irq = {IRQ_BASIC_GPIO, NO_IRQ},
};
/* uart device registeration */
/* uart device registration */
struct amba_device uart_device = {
.dev = {
.init_name = "uart",
@ -543,6 +543,6 @@ void spear_pmx_init(struct pmx_driver *pmx_driver, uint base, uint size)
pmx_fail:
if (ret)
printk(KERN_ERR "padmux: registeration failed. err no: %d\n",
printk(KERN_ERR "padmux: registration failed. err no: %d\n",
ret);
}

4
arch/arm/mach-spear6xx/spear6xx.c
View File

@ -23,7 +23,7 @@
#include <mach/spear.h>
/* Add spear6xx machines common devices here */
/* uart device registeration */
/* uart device registration */
struct amba_device uart_device[] = {
{
.dev = {
@ -50,7 +50,7 @@ struct amba_device uart_device[] = {
}
};
/* gpio device registeration */
/* gpio device registration */
static struct pl061_platform_data gpio_plat_data[] = {
{
.gpio_base = 0,

2
arch/arm/mach-u300/Kconfig
View File

@ -64,7 +64,7 @@ config MACH_U300_DUAL_RAM
bool "Dual RAM"
help
Select this if you want support for Dual RAM phones.
This is two RAM memorys on different EMIFs.
This is two RAM memories on different EMIFs.
endchoice
config U300_DEBUG

4
arch/arm/mach-u300/include/mach/coh901318.h
View File

@ -24,7 +24,7 @@
* @src_addr: transfer source address
* @dst_addr: transfer destination address
* @link_addr: physical address to next lli
* @virt_link_addr: virtual addres of next lli (only used by pool_free)
* @virt_link_addr: virtual address of next lli (only used by pool_free)
* @phy_this: physical address of current lli (only used by pool_free)
*/
struct coh901318_lli {
@ -90,7 +90,7 @@ struct powersave {
* struct coh901318_platform - platform arch structure
* @chans_slave: specifying dma slave channels
* @chans_memcpy: specifying dma memcpy channels
* @access_memory_state: requesting DMA memeory access (on / off)
* @access_memory_state: requesting DMA memory access (on / off)
* @chan_conf: dma channel configurations
* @max_channels: max number of dma chanenls
*/

2
arch/arm/plat-mxc/include/mach/irqs.h
View File

@ -66,7 +66,7 @@ extern int imx_irq_set_priority(unsigned char irq, unsigned char prio);
/* all normal IRQs can be FIQs */
#define FIQ_START 0
/* switch betwean IRQ and FIQ */
/* switch between IRQ and FIQ */
extern int mxc_set_irq_fiq(unsigned int irq, unsigned int type);
#endif /* __ASM_ARCH_MXC_IRQS_H__ */

2
arch/arm/plat-omap/include/plat/omap_hwmod.h
View File

@ -339,7 +339,7 @@ struct omap_hwmod_omap2_prcm {
/**
* struct omap_hwmod_omap4_prcm - OMAP4-specific PRCM data
* @clkctrl_reg: PRCM address of the clock control register
* @rstctrl_reg: adress of the XXX_RSTCTRL register located in the PRM
* @rstctrl_reg: address of the XXX_RSTCTRL register located in the PRM
* @submodule_wkdep_bit: bit shift of the WKDEP range
*/
struct omap_hwmod_omap4_prcm {

2
arch/blackfin/mach-bf518/include/mach/defBF51x_base.h
View File

@ -1197,7 +1197,7 @@
#define SADD_LEN 0x0002 /* Slave Address Length */
#define STDVAL 0x0004 /* Slave Transmit Data Valid */
#define NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */
#define GEN 0x0010 /* General Call Adrress Matching Enabled */
#define GEN 0x0010 /* General Call Address Matching Enabled */
/* TWI_SLAVE_STAT Masks */
#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */

2
arch/blackfin/mach-bf527/include/mach/defBF52x_base.h
View File

@ -1206,7 +1206,7 @@
#define SADD_LEN 0x0002 /* Slave Address Length */
#define STDVAL 0x0004 /* Slave Transmit Data Valid */
#define NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */
#define GEN 0x0010 /* General Call Adrress Matching Enabled */
#define GEN 0x0010 /* General Call Address Matching Enabled */
/* TWI_SLAVE_STAT Masks */
#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */

2
arch/blackfin/mach-bf537/include/mach/defBF534.h
View File

@ -1523,7 +1523,7 @@
#define SADD_LEN 0x0002 /* Slave Address Length */
#define STDVAL 0x0004 /* Slave Transmit Data Valid */
#define NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */
#define GEN 0x0010 /* General Call Adrress Matching Enabled */
#define GEN 0x0010 /* General Call Address Matching Enabled */
/* TWI_SLAVE_STAT Masks */
#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */

2
arch/blackfin/mach-bf538/include/mach/defBF539.h
View File

@ -2185,7 +2185,7 @@
#define SADD_LEN 0x0002 /* Slave Address Length */
#define STDVAL 0x0004 /* Slave Transmit Data Valid */
#define NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */
#define GEN 0x0010 /* General Call Adrress Matching Enabled */
#define GEN 0x0010 /* General Call Address Matching Enabled */
/* TWIx_SLAVE_STAT Masks */
#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */

2
arch/cris/arch-v32/lib/nand_init.S
View File

@ -139,7 +139,7 @@ copy_nand_to_ram:
lsrq 8, $r4
move.b $r4, [$r1] ; Row address
lsrq 8, $r4
move.b $r4, [$r1] ; Row adddress
move.b $r4, [$r1] ; Row address
moveq 20, $r4
2: bne 2b
subq 1, $r4

2
arch/cris/include/asm/etraxgpio.h
View File

@ -1,5 +1,5 @@
/*
* The following devices are accessable using this driver using
* The following devices are accessible using this driver using
* GPIO_MAJOR (120) and a couple of minor numbers.
*
* For ETRAX 100LX (CONFIG_ETRAX_ARCH_V10):

2
arch/h8300/Kconfig.debug
View File

@ -48,7 +48,7 @@ config DEFAULT_CMDLINE
builtin kernel commandline enabled.
config KERNEL_COMMAND
string "Buildin commmand string"
string "Buildin command string"
depends on DEFAULT_CMDLINE
help
builtin kernel commandline strings.

2
arch/ia64/kvm/mmio.c
View File

@ -130,7 +130,7 @@ static void mmio_access(struct kvm_vcpu *vcpu, u64 src_pa, u64 *dest,
local_irq_save(psr);
/*Intercept the acces for PIB range*/
/*Intercept the access for PIB range*/
if (iot == GPFN_PIB) {
if (!dir)
lsapic_write(vcpu, src_pa, s, *dest);

2
arch/mips/alchemy/common/power.c
View File

@ -130,7 +130,7 @@ static void restore_core_regs(void)
au_writel(sleep_usb[1], USBD_ENABLE);
au_sync();
#else
/* enable accces to OTG memory */
/* enable access to OTG memory */
au_writel(au_readl(USB_MSR_BASE + 4) | (1 << 6), USB_MSR_BASE + 4);
au_sync();

2
arch/mips/include/asm/mach-powertv/ioremap.h
View File

@ -88,7 +88,7 @@ static inline dma_addr_t _dma_to_phys_offset_raw(dma_addr_t dma)
}
/* These are not portable and should not be used in drivers. Drivers should
* be using ioremap() and friends to map physical addreses to virtual
* be using ioremap() and friends to map physical addresses to virtual
* addresses and dma_map*() and friends to map virtual addresses into DMA
* addresses and back.
*/

4
arch/mips/jz4740/board-qi_lb60.c
View File

@ -65,7 +65,7 @@ static struct nand_ecclayout qi_lb60_ecclayout_1gb = {
/* Early prototypes of the QI LB60 had only 1GB of NAND.
* In order to support these devices aswell the partition and ecc layout is
* initalized depending on the NAND size */
* initialized depending on the NAND size */
static struct mtd_partition qi_lb60_partitions_1gb[] = {
{
.name = "NAND BOOT partition",
@ -464,7 +464,7 @@ static int __init qi_lb60_board_setup(void)
board_gpio_setup();
if (qi_lb60_init_platform_devices())
panic("Failed to initalize platform devices\n");
panic("Failed to initialize platform devices\n");
return 0;
}

2
arch/mips/jz4740/gpio.c
View File

@ -546,7 +546,7 @@ static int __init jz4740_gpio_init(void)
for (i = 0; i < ARRAY_SIZE(jz4740_gpio_chips); ++i)
jz4740_gpio_chip_init(&jz4740_gpio_chips[i], i);
printk(KERN_INFO "JZ4740 GPIO initalized\n");
printk(KERN_INFO "JZ4740 GPIO initialized\n");
return 0;
}

2
arch/mips/mti-malta/malta-memory.c
View File

@ -43,7 +43,7 @@ static struct prom_pmemblock mdesc[PROM_MAX_PMEMBLOCKS];
static char *mtypes[3] = {
"Dont use memory",
"YAMON PROM memory",
"Free memmory",
"Free memory",
};
#endif

2
arch/mips/pci/pcie-octeon.c
View File

@ -900,7 +900,7 @@ static int cvmx_pcie_rc_initialize(int pcie_port)
mem_access_subid.s.ror = 0;
/* Disable Relaxed Ordering for Writes. */
mem_access_subid.s.row = 0;
/* PCIe Adddress Bits <63:34>. */
/* PCIe Address Bits <63:34>. */
mem_access_subid.s.ba = 0;
/*

2
arch/mips/powertv/memory.c
View File

@ -57,7 +57,7 @@
unsigned long ptv_memsize;
/*
* struct low_mem_reserved - Items in low memmory that are reserved
* struct low_mem_reserved - Items in low memory that are reserved
* @start: Physical address of item
* @size: Size, in bytes, of this item
* @is_aliased: True if this is RAM aliased from another location. If false,

2
arch/mips/txx9/generic/pci.c
View File

@ -107,7 +107,7 @@ int txx9_pci_mem_high __initdata;
/*
* allocate pci_controller and resources.
* mem_base, io_base: physical addresss. 0 for auto assignment.
* mem_base, io_base: physical address. 0 for auto assignment.
* mem_size and io_size means max size on auto assignment.
* pcic must be &txx9_primary_pcic or NULL.
*/

4
arch/powerpc/include/asm/8xx_immap.h
View File

@ -93,7 +93,7 @@ typedef struct mem_ctlr {
} memctl8xx_t;
/*-----------------------------------------------------------------------
* BR - Memory Controler: Base Register 16-9
* BR - Memory Controller: Base Register 16-9
*/
#define BR_BA_MSK 0xffff8000 /* Base Address Mask */
#define BR_AT_MSK 0x00007000 /* Address Type Mask */
@ -110,7 +110,7 @@ typedef struct mem_ctlr {
#define BR_V 0x00000001 /* Bank Valid */
/*-----------------------------------------------------------------------
* OR - Memory Controler: Option Register 16-11
* OR - Memory Controller: Option Register 16-11
*/
#define OR_AM_MSK 0xffff8000 /* Address Mask Mask */
#define OR_ATM_MSK 0x00007000 /* Address Type Mask Mask */

2
arch/powerpc/oprofile/op_model_cell.c
View File

@ -1469,7 +1469,7 @@ static int cell_global_start(struct op_counter_config *ctr)
* The pm_interval register is setup to write the SPU PC value into the
* trace buffer at the maximum rate possible. The trace buffer is configured
* to store the PCs, wrapping when it is full. The performance counter is
* intialized to the max hardware count minus the number of events, N, between
* initialized to the max hardware count minus the number of events, N, between
* samples. Once the N events have occured, a HW counter overflow occurs
* causing the generation of a HW counter interrupt which also stops the
* writing of the SPU PC values to the trace buffer. Hence the last PC

6
arch/powerpc/platforms/83xx/suspend-asm.S
View File

@ -231,7 +231,7 @@ _GLOBAL(mpc83xx_enter_deep_sleep)
ori r4, r4, 0x002a
mtspr SPRN_DBAT0L, r4
lis r8, TMP_VIRT_IMMR@h
ori r4, r8, 0x001e /* 1 MByte accessable from Kernel Space only */
ori r4, r8, 0x001e /* 1 MByte accessible from Kernel Space only */
mtspr SPRN_DBAT0U, r4
isync
@ -241,7 +241,7 @@ _GLOBAL(mpc83xx_enter_deep_sleep)
ori r4, r4, 0x002a
mtspr SPRN_DBAT1L, r4
lis r9, (TMP_VIRT_IMMR + 0x01000000)@h
ori r4, r9, 0x001e /* 1 MByte accessable from Kernel Space only */
ori r4, r9, 0x001e /* 1 MByte accessible from Kernel Space only */
mtspr SPRN_DBAT1U, r4
isync
@ -253,7 +253,7 @@ _GLOBAL(mpc83xx_enter_deep_sleep)
li r4, 0x0002
mtspr SPRN_DBAT2L, r4
lis r4, KERNELBASE@h
ori r4, r4, 0x001e /* 1 MByte accessable from Kernel Space only */
ori r4, r4, 0x001e /* 1 MByte accessible from Kernel Space only */
mtspr SPRN_DBAT2U, r4
isync

4
arch/powerpc/platforms/ps3/device-init.c
View File

@ -566,10 +566,10 @@ static int ps3_setup_dynamic_device(const struct ps3_repository_device *repo)
case PS3_DEV_TYPE_STOR_DISK:
result = ps3_setup_storage_dev(repo, PS3_MATCH_ID_STOR_DISK);
/* Some devices are not accessable from the Other OS lpar. */
/* Some devices are not accessible from the Other OS lpar. */
if (result == -ENODEV) {
result = 0;
pr_debug("%s:%u: not accessable\n", __func__,
pr_debug("%s:%u: not accessible\n", __func__,
__LINE__);
}

2
arch/powerpc/platforms/ps3/interrupt.c
View File

@ -44,7 +44,7 @@
* @lock:
* @ipi_debug_brk_mask:
*
* The HV mantains per SMT thread mappings of HV outlet to HV plug on
* The HV maintains per SMT thread mappings of HV outlet to HV plug on
* behalf of the guest. These mappings are implemented as 256 bit guest
* supplied bitmaps indexed by plug number. The addresses of the bitmaps
* are registered with the HV through lv1_configure_irq_state_bitmap().

2
arch/sh/mm/cache-sh5.c
View File

@ -568,7 +568,7 @@ static void sh5_flush_dcache_page(void *page)
}
/*
* Flush the range [start,end] of kernel virtual adddress space from
* Flush the range [start,end] of kernel virtual address space from
* the I-cache. The corresponding range must be purged from the
* D-cache also because the SH-5 doesn't have cache snooping between
* the caches. The addresses will be visible through the superpage

2
arch/sparc/kernel/traps_64.c
View File

@ -622,7 +622,7 @@ static const char CHAFSR_PERR_msg[] =
static const char CHAFSR_IERR_msg[] =
"Internal processor error";
static const char CHAFSR_ISAP_msg[] =
"System request parity error on incoming addresss";
"System request parity error on incoming address";
static const char CHAFSR_UCU_msg[] =
"Uncorrectable E-cache ECC error for ifetch/data";
static const char CHAFSR_UCC_msg[] =

2
arch/x86/include/asm/pgalloc.h
View File

@ -92,7 +92,7 @@ static inline void pmd_free(struct mm_struct *mm, pmd_t *pmd)
extern void ___pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmd);
static inline void __pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmd,
unsigned long adddress)
unsigned long address)
{
___pmd_free_tlb(tlb, pmd);
}

2
arch/x86/include/asm/processor.h
View File

@ -902,7 +902,7 @@ extern unsigned long thread_saved_pc(struct task_struct *tsk);
/*
* The below -8 is to reserve 8 bytes on top of the ring0 stack.
* This is necessary to guarantee that the entire "struct pt_regs"
* is accessable even if the CPU haven't stored the SS/ESP registers
* is accessible even if the CPU haven't stored the SS/ESP registers
* on the stack (interrupt gate does not save these registers
* when switching to the same priv ring).
* Therefore beware: accessing the ss/esp fields of the

4
arch/x86/kernel/amd_iommu.c
View File

@ -1086,7 +1086,7 @@ static int alloc_new_range(struct dma_ops_domain *dma_dom,
dma_dom->aperture_size += APERTURE_RANGE_SIZE;
/* Intialize the exclusion range if necessary */
/* Initialize the exclusion range if necessary */
for_each_iommu(iommu) {
if (iommu->exclusion_start &&
iommu->exclusion_start >= dma_dom->aperture[index]->offset
@ -1353,7 +1353,7 @@ static void dma_ops_domain_free(struct dma_ops_domain *dom)
/*
* Allocates a new protection domain usable for the dma_ops functions.
* It also intializes the page table and the address allocator data
* It also initializes the page table and the address allocator data
* structures required for the dma_ops interface
*/
static struct dma_ops_domain *dma_ops_domain_alloc(void)

2
arch/x86/kernel/early_printk_mrst.c
View File

@ -103,7 +103,7 @@ struct dw_spi_reg {
static unsigned long mrst_spi_paddr = MRST_REGBASE_SPI0;
static u32 *pclk_spi0;
/* Always contains an accessable address, start with 0 */
/* Always contains an accessible address, start with 0 */
static struct dw_spi_reg *pspi;
static struct kmsg_dumper dw_dumper;

2
arch/x86/kernel/head_32.S
View File

@ -124,7 +124,7 @@ ENTRY(startup_32)
movsl
movl pa(boot_params) + NEW_CL_POINTER,%esi
andl %esi,%esi
jz 1f # No comand line
jz 1f # No command line
movl $pa(boot_command_line),%edi
movl $(COMMAND_LINE_SIZE/4),%ecx
rep

2
block/cfq-iosched.c
View File

@ -1030,7 +1030,7 @@ cfq_find_alloc_cfqg(struct cfq_data *cfqd, struct cgroup *cgroup, int create)
/*
* Add group onto cgroup list. It might happen that bdi->dev is
* not initiliazed yet. Initialize this new group without major
* not initialized yet. Initialize this new group without major
* and minor info and this info will be filled in once a new thread
* comes for IO. See code above.
*/

2
drivers/acpi/acpica/acobject.h
View File

@ -93,7 +93,7 @@
#define AOPOBJ_AML_CONSTANT 0x01 /* Integer is an AML constant */
#define AOPOBJ_STATIC_POINTER 0x02 /* Data is part of an ACPI table, don't delete */
#define AOPOBJ_DATA_VALID 0x04 /* Object is intialized and data is valid */
#define AOPOBJ_DATA_VALID 0x04 /* Object is initialized and data is valid */
#define AOPOBJ_OBJECT_INITIALIZED 0x08 /* Region is initialized, _REG was run */
#define AOPOBJ_SETUP_COMPLETE 0x10 /* Region setup is complete */
#define AOPOBJ_INVALID 0x20 /* Host OS won't allow a Region address */

4
drivers/ata/libata-core.c
View File

@ -2240,7 +2240,7 @@ int ata_dev_configure(struct ata_device *dev)
if (id[ATA_ID_CFA_KEY_MGMT] & 1)
ata_dev_printk(dev, KERN_WARNING,
"supports DRM functions and may "
"not be fully accessable.\n");
"not be fully accessible.\n");
snprintf(revbuf, 7, "CFA");
} else {
snprintf(revbuf, 7, "ATA-%d", ata_id_major_version(id));
@ -2248,7 +2248,7 @@ int ata_dev_configure(struct ata_device *dev)
if (ata_id_has_tpm(id))
ata_dev_printk(dev, KERN_WARNING,
"supports DRM functions and may "
"not be fully accessable.\n");
"not be fully accessible.\n");
}
dev->n_sectors = ata_id_n_sectors(id);

2
drivers/ata/sata_vsc.c
View File

@ -370,7 +370,7 @@ static int __devinit vsc_sata_init_one(struct pci_dev *pdev,
if (pci_resource_len(pdev, 0) == 0)
return -ENODEV;
/* map IO regions and intialize host accordingly */
/* map IO regions and initialize host accordingly */
rc = pcim_iomap_regions(pdev, 1 << VSC_MMIO_BAR, DRV_NAME);
if (rc == -EBUSY)
pcim_pin_device(pdev);

2
drivers/atm/idt77252.h
View File

@ -572,7 +572,7 @@ struct idt77252_dev
#define SAR_STAT_TSQF 0x00001000 /* Transmit Status Queue full */
#define SAR_STAT_TMROF 0x00000800 /* Timer overflow */
#define SAR_STAT_PHYI 0x00000400 /* PHY device Interrupt flag */
#define SAR_STAT_CMDBZ 0x00000200 /* ABR SAR Comand Busy Flag */
#define SAR_STAT_CMDBZ 0x00000200 /* ABR SAR Command Busy Flag */
#define SAR_STAT_FBQ3A 0x00000100 /* Free Buffer Queue 3 Attention */
#define SAR_STAT_FBQ2A 0x00000080 /* Free Buffer Queue 2 Attention */
#define SAR_STAT_RSQF 0x00000040 /* Receive Status Queue full */

4
drivers/atm/iphase.c
View File

@ -2063,7 +2063,7 @@ static int tx_init(struct atm_dev *dev)
- UBR Table size is 4K
- UBR wait queue is 4K
since the table and wait queues are contiguous, all the bytes
can be initialized by one memeset.
can be initialized by one memeset.
*/
vcsize_sel = 0;
@ -2089,7 +2089,7 @@ static int tx_init(struct atm_dev *dev)
- ABR Table size is 2K
- ABR wait queue is 2K
since the table and wait queues are contiguous, all the bytes
can be intialized by one memeset.
can be initialized by one memeset.
*/
i = ABR_SCHED_TABLE * iadev->memSize;
writew((i >> 11) & 0xffff, iadev->seg_reg+ABR_SBPTR_BASE);

2
drivers/base/power/main.c
View File

@ -8,7 +8,7 @@
*
*
* The driver model core calls device_pm_add() when a device is registered.
* This will intialize the embedded device_pm_info object in the device
* This will initialize the embedded device_pm_info object in the device
* and add it to the list of power-controlled devices. sysfs entries for
* controlling device power management will also be added.
*

6
drivers/dma/intel_mid_dma.c
View File

@ -1060,8 +1060,8 @@ static irqreturn_t intel_mid_dma_interrupt2(int irq, void *data)
* mid_setup_dma - Setup the DMA controller
* @pdev: Controller PCI device structure
*
* Initilize the DMA controller, channels, registers with DMA engine,
* ISR. Initilize DMA controller channels.
* Initialize the DMA controller, channels, registers with DMA engine,
* ISR. Initialize DMA controller channels.
*/
static int mid_setup_dma(struct pci_dev *pdev)
{
@ -1219,7 +1219,7 @@ static void middma_shutdown(struct pci_dev *pdev)
* @pdev: Controller PCI device structure
* @id: pci device id structure
*
* Initilize the PCI device, map BARs, query driver data.
* Initialize the PCI device, map BARs, query driver data.
* Call setup_dma to complete contoller and chan initilzation
*/
static int __devinit intel_mid_dma_probe(struct pci_dev *pdev,

2
drivers/edac/amd8131_edac.h
View File

@ -99,7 +99,7 @@ struct amd8131_dev_info {
/*
* AMD8131 chipset has two pairs of PCIX Bridge and related IOAPIC
* Controler, and ATCA-6101 has two AMD8131 chipsets, so there are
* Controller, and ATCA-6101 has two AMD8131 chipsets, so there are
* four PCIX Bridges on ATCA-6101 altogether.
*
* These PCIX Bridges share the same PCI Device ID and are all of

4
drivers/edac/cell_edac.c
View File

@ -47,7 +47,7 @@ static void cell_edac_count_ce(struct mem_ctl_info *mci, int chan, u64 ar)
offset = address & ~PAGE_MASK;
syndrome = (ar & 0x000000001fe00000ul) >> 21;
/* TODO: Decoding of the error addresss */
/* TODO: Decoding of the error address */
edac_mc_handle_ce(mci, csrow->first_page + pfn, offset,
syndrome, 0, chan, "");
}
@ -68,7 +68,7 @@ static void cell_edac_count_ue(struct mem_ctl_info *mci, int chan, u64 ar)
pfn = address >> PAGE_SHIFT;
offset = address & ~PAGE_MASK;
/* TODO: Decoding of the error addresss */
/* TODO: Decoding of the error address */
edac_mc_handle_ue(mci, csrow->first_page + pfn, offset, 0, "");
}

2
drivers/edac/edac_core.h
View File

@ -258,7 +258,7 @@ enum scrub_type {
* for single channel are 64 bits, for dual channel 128
* bits.
*
* Single-Ranked stick: A Single-ranked stick has 1 chip-select row of memmory.
* Single-Ranked stick: A Single-ranked stick has 1 chip-select row of memory.
* Motherboards commonly drive two chip-select pins to
* a memory stick. A single-ranked stick, will occupy
* only one of those rows. The other will be unused.

6
drivers/edac/ppc4xx_edac.c
View File

@ -873,7 +873,7 @@ ppc4xx_edac_get_mtype(u32 mcopt1)
}
/**
* ppc4xx_edac_init_csrows - intialize driver instance rows
* ppc4xx_edac_init_csrows - initialize driver instance rows
* @mci: A pointer to the EDAC memory controller instance
* associated with the ibm,sdram-4xx-ddr2 controller for which
* the csrows (i.e. banks/ranks) are being initialized.
@ -881,7 +881,7 @@ ppc4xx_edac_get_mtype(u32 mcopt1)
* currently set for the controller, from which bank width
* and memory typ information is derived.
*
* This routine intializes the virtual "chip select rows" associated
* This routine initializes the virtual "chip select rows" associated
* with the EDAC memory controller instance. An ibm,sdram-4xx-ddr2
* controller bank/rank is mapped to a row.
*
@ -992,7 +992,7 @@ ppc4xx_edac_init_csrows(struct mem_ctl_info *mci, u32 mcopt1)
}
/**
* ppc4xx_edac_mc_init - intialize driver instance
* ppc4xx_edac_mc_init - initialize driver instance
* @mci: A pointer to the EDAC memory controller instance being
* initialized.
* @op: A pointer to the OpenFirmware device tree node associated

2
drivers/gpu/drm/radeon/atombios.h
View File

@ -1314,7 +1314,7 @@ typedef struct _GET_ENGINE_CLOCK_PARAMETERS
typedef struct _READ_EDID_FROM_HW_I2C_DATA_PARAMETERS
{
USHORT usPrescale; //Ratio between Engine clock and I2C clock
USHORT usVRAMAddress; //Adress in Frame Buffer where to pace raw EDID
USHORT usVRAMAddress; //Address in Frame Buffer where to pace raw EDID
USHORT usStatus; //When use output: lower byte EDID checksum, high byte hardware status
//WHen use input: lower byte as 'byte to read':currently limited to 128byte or 1byte
UCHAR ucSlaveAddr; //Read from which slave

4
drivers/i2c/busses/i2c-nomadik.c
View File

@ -434,7 +434,7 @@ static int read_i2c(struct nmk_i2c_dev *dev)
}
if (timeout == 0) {
/* controler has timedout, re-init the h/w */
/* controller has timedout, re-init the h/w */
dev_err(&dev->pdev->dev, "controller timed out, re-init h/w\n");
(void) init_hw(dev);
status = -ETIMEDOUT;
@ -498,7 +498,7 @@ static int write_i2c(struct nmk_i2c_dev *dev)
}
if (timeout == 0) {
/* controler has timedout, re-init the h/w */
/* controller has timedout, re-init the h/w */
dev_err(&dev->pdev->dev, "controller timed out, re-init h/w\n");
(void) init_hw(dev);
status = -ETIMEDOUT;

2
drivers/infiniband/hw/cxgb3/cxio_wr.h
View File

@ -689,7 +689,7 @@ struct t3_swrq {
* A T3 WQ implements both the SQ and RQ.
*/
struct t3_wq {
union t3_wr *queue; /* DMA accessable memory */
union t3_wr *queue; /* DMA accessible memory */
dma_addr_t dma_addr; /* DMA address for HW */
DEFINE_DMA_UNMAP_ADDR(mapping); /* unmap kruft */
u32 error; /* 1 once we go to ERROR */

2
drivers/infiniband/hw/qib/qib_iba7322.c
View File

@ -314,7 +314,7 @@ MODULE_PARM_DESC(txselect, \
#define krp_serdesctrl KREG_IBPORT_IDX(IBSerdesCtrl)
/*
* Per-context kernel registers. Acess only with qib_read_kreg_ctxt()
* Per-context kernel registers. Access only with qib_read_kreg_ctxt()
* or qib_write_kreg_ctxt()
*/
#define krc_rcvhdraddr KREG_IDX(RcvHdrAddr0)

2
drivers/input/touchscreen/Kconfig
View File

@ -610,7 +610,7 @@ config TOUCHSCREEN_USB_ZYTRONIC
config TOUCHSCREEN_USB_ETT_TC45USB
default y
bool "ET&T USB series TC4UM/TC5UH touchscreen controler support" if EMBEDDED
bool "ET&T USB series TC4UM/TC5UH touchscreen controller support" if EMBEDDED
depends on TOUCHSCREEN_USB_COMPOSITE
config TOUCHSCREEN_USB_NEXIO

4
drivers/isdn/gigaset/bas-gigaset.c
View File

@ -2318,7 +2318,7 @@ static int gigaset_probe(struct usb_interface *interface,
__func__, le16_to_cpu(udev->descriptor.idVendor),
le16_to_cpu(udev->descriptor.idProduct));
/* allocate memory for our device state and intialize it */
/* allocate memory for our device state and initialize it */
cs = gigaset_initcs(driver, BAS_CHANNELS, 0, 0, cidmode,
GIGASET_MODULENAME);
if (!cs)
@ -2576,7 +2576,7 @@ static int __init bas_gigaset_init(void)
{
int result;
/* allocate memory for our driver state and intialize it */
/* allocate memory for our driver state and initialize it */
driver = gigaset_initdriver(GIGASET_MINOR, GIGASET_MINORS,
GIGASET_MODULENAME, GIGASET_DEVNAME,
&gigops, THIS_MODULE);

4
drivers/isdn/gigaset/ser-gigaset.c
View File

@ -513,7 +513,7 @@ gigaset_tty_open(struct tty_struct *tty)
return -ENODEV;
}
/* allocate memory for our device state and intialize it */
/* allocate memory for our device state and initialize it */
cs = gigaset_initcs(driver, 1, 1, 0, cidmode, GIGASET_MODULENAME);
if (!cs)
goto error;
@ -771,7 +771,7 @@ static int __init ser_gigaset_init(void)
return rc;
}
/* allocate memory for our driver state and intialize it */
/* allocate memory for our driver state and initialize it */
driver = gigaset_initdriver(GIGASET_MINOR, GIGASET_MINORS,
GIGASET_MODULENAME, GIGASET_DEVNAME,
&ops, THIS_MODULE);

4
drivers/isdn/gigaset/usb-gigaset.c
View File

@ -695,7 +695,7 @@ static int gigaset_probe(struct usb_interface *interface,
dev_info(&udev->dev, "%s: Device matched ... !\n", __func__);
/* allocate memory for our device state and intialize it */
/* allocate memory for our device state and initialize it */
cs = gigaset_initcs(driver, 1, 1, 0, cidmode, GIGASET_MODULENAME);
if (!cs)
return -ENODEV;
@ -894,7 +894,7 @@ static int __init usb_gigaset_init(void)
{
int result;
/* allocate memory for our driver state and intialize it */
/* allocate memory for our driver state and initialize it */
driver = gigaset_initdriver(GIGASET_MINOR, GIGASET_MINORS,
GIGASET_MODULENAME, GIGASET_DEVNAME,
&ops, THIS_MODULE);

4
drivers/isdn/hardware/mISDN/ipac.h
View File

@ -29,7 +29,7 @@ struct isac_hw {
u32 type;
u32 off; /* offset to isac regs */
char *name;
spinlock_t *hwlock; /* lock HW acccess */
spinlock_t *hwlock; /* lock HW access */
read_reg_func *read_reg;
write_reg_func *write_reg;
fifo_func *read_fifo;
@ -70,7 +70,7 @@ struct ipac_hw {
struct hscx_hw hscx[2];
char *name;
void *hw;
spinlock_t *hwlock; /* lock HW acccess */
spinlock_t *hwlock; /* lock HW access */
struct module *owner;
u32 type;
read_reg_func *read_reg;

2
drivers/isdn/hardware/mISDN/isar.h
View File

@ -44,7 +44,7 @@ struct isar_ch {
struct isar_hw {
struct isar_ch ch[2];
void *hw;
spinlock_t *hwlock; /* lock HW acccess */
spinlock_t *hwlock; /* lock HW access */
char *name;
struct module *owner;
read_reg_func *read_reg;

4
drivers/isdn/hisax/isar.c
View File

@ -1427,8 +1427,8 @@ modeisar(struct BCState *bcs, int mode, int bc)
&bcs->hw.isar.reg->Flags))
bcs->hw.isar.dpath = 1;
else {
printk(KERN_WARNING"isar modeisar analog funktions only with DP1\n");
debugl1(cs, "isar modeisar analog funktions only with DP1");
printk(KERN_WARNING"isar modeisar analog functions only with DP1\n");
debugl1(cs, "isar modeisar analog functions only with DP1");
return(1);
}
break;

2
drivers/media/video/cx25840/cx25840-ir.c
View File

@ -261,7 +261,7 @@ static u16 ns_to_pulse_width_count(u32 ns, u16 divider)
u32 rem;
/*
* The 2 lsb's of the pulse width timer count are not accessable, hence
* The 2 lsb's of the pulse width timer count are not accessible, hence
* the (1 << 2)
*/
n = ((u64) ns) * CX25840_IR_REFCLK_FREQ / 1000000; /* millicycles */

2
drivers/media/video/davinci/vpif.h
View File

@ -33,7 +33,7 @@ extern spinlock_t vpif_lock;
#define regr(reg) readl((reg) + vpif_base)
#define regw(value, reg) writel(value, (reg + vpif_base))
/* Register Addresss Offsets */
/* Register Address Offsets */
#define VPIF_PID (0x0000)
#define VPIF_CH0_CTRL (0x0004)
#define VPIF_CH1_CTRL (0x0008)

2
drivers/media/video/davinci/vpss.c
View File

@ -85,7 +85,7 @@ enum vpss_platform_type {
/*
* vpss operations. Depends on platform. Not all functions are available
* on all platforms. The api, first check if a functio is available before
* invoking it. In the probe, the function ptrs are intialized based on
* invoking it. In the probe, the function ptrs are initialized based on
* vpss name. vpss name can be "dm355_vpss", "dm644x_vpss" etc.
*/
struct vpss_hw_ops {

2
drivers/media/video/omap/omap_vout.c
View File

@ -1286,7 +1286,7 @@ static int omap_vout_release(struct file *file)
videobuf_mmap_free(q);
/* Even if apply changes fails we should continue
freeing allocated memeory */
freeing allocated memory */
if (vout->streaming) {
u32 mask = 0;

4
drivers/media/video/saa7164/saa7164-core.c
View File

@ -653,8 +653,8 @@ static irqreturn_t saa7164_irq(int irq, void *dev_id)
goto out;
}
/* Check that the hardware is accessable. If the status bytes are
* 0xFF then the device is not accessable, the the IRQ belongs
/* Check that the hardware is accessible. If the status bytes are
* 0xFF then the device is not accessible, the the IRQ belongs
* to another driver.
* 4 x u32 interrupt registers.
*/

2
drivers/media/video/sn9c102/sn9c102_sensor.h
View File

@ -147,7 +147,7 @@ enum sn9c102_i2c_interface {
struct sn9c102_sensor {
char name[32], /* sensor name */
maintainer[64]; /* name of the mantainer <email> */
maintainer[64]; /* name of the maintainer <email> */
enum sn9c102_bridge supported_bridge; /* supported SN9C1xx bridges */

2
drivers/media/video/zoran/zoran.h
View File

@ -95,7 +95,7 @@ struct zoran_params {
int quality; /* Measure for quality of compressed images.
* Scales linearly with the size of the compressed images.
* Must be beetween 0 and 100, 100 is a compression
* Must be between 0 and 100, 100 is a compression
* ratio of 1:4 */
int odd_even; /* Which field should come first ??? */

2
drivers/message/fusion/lsi/mpi_log_sas.h
View File

@ -268,7 +268,7 @@
/* Compatibility Error : IR Disabled */
#define IR_LOGINFO_COMPAT_ERROR_RAID_DISABLED (0x00010030)
/* Compatibility Error : Inquiry Comand failed */
/* Compatibility Error : Inquiry Command failed */
#define IR_LOGINFO_COMPAT_ERROR_INQUIRY_FAILED (0x00010031)
/* Compatibility Error : Device not direct access device */
#define IR_LOGINFO_COMPAT_ERROR_NOT_DIRECT_ACCESS (0x00010032)

2
drivers/message/fusion/mptbase.c
View File

@ -7977,7 +7977,7 @@ mpt_spi_log_info(MPT_ADAPTER *ioc, u32 log_info)
NULL, /* 2Eh */
NULL, /* 2Fh */
"Compatibility Error: IR Disabled", /* 30h */
"Compatibility Error: Inquiry Comand Failed", /* 31h */
"Compatibility Error: Inquiry Command Failed", /* 31h */
"Compatibility Error: Device not Direct Access "
"Device ", /* 32h */
"Compatibility Error: Removable Device Found", /* 33h */

2
drivers/message/fusion/mptsas.c
View File

@ -1146,7 +1146,7 @@ mptsas_target_reset_queue(MPT_ADAPTER *ioc,
*
* This function will delete scheduled target reset from the list and
* try to send next target reset. This will be called from completion
* context of any Task managment command.
* context of any Task management command.
*/
void

2
drivers/message/i2o/i2o_block.c
View File

@ -309,7 +309,7 @@ static inline void i2o_block_request_free(struct i2o_block_request *ireq)
* @ireq: I2O block request
* @mptr: message body pointer
*
* Builds the SG list and map it to be accessable by the controller.
* Builds the SG list and map it to be accessible by the controller.
*
* Returns 0 on failure or 1 on success.
*/

2
drivers/misc/arm-charlcd.c
View File

@ -313,7 +313,7 @@ static int __init charlcd_probe(struct platform_device *pdev)
INIT_DELAYED_WORK(&lcd->init_work, charlcd_init_work);
schedule_delayed_work(&lcd->init_work, 0);
dev_info(&pdev->dev, "initalized ARM character LCD at %08x\n",
dev_info(&pdev->dev, "initialized ARM character LCD at %08x\n",
lcd->phybase);
return 0;

2
drivers/mmc/card/block.c
View File

@ -257,7 +257,7 @@ static u32 get_card_status(struct mmc_card *card, struct request *req)
cmd.flags = MMC_RSP_SPI_R2 | MMC_RSP_R1 | MMC_CMD_AC;
err = mmc_wait_for_cmd(card->host, &cmd, 0);
if (err)
printk(KERN_ERR "%s: error %d sending status comand",
printk(KERN_ERR "%s: error %d sending status command",
req->rq_disk->disk_name, err);
return cmd.resp[0];
}

2
drivers/mmc/host/Kconfig
View File

@ -462,7 +462,7 @@ config MMC_SH_MMCIF
tristate "SuperH Internal MMCIF support"
depends on MMC_BLOCK && (SUPERH || ARCH_SHMOBILE)
help
This selects the MMC Host Interface controler (MMCIF).
This selects the MMC Host Interface controller (MMCIF).
This driver supports MMCIF in sh7724/sh7757/sh7372.

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