Merge branch 'for-next/docs' into for-next/core
* for-next/docs: arm64/mte: Clarify mode reported by PR_GET_TAGGED_ADDR_CTRL arm64: booting.rst: Clarify on requiring non-secure EL2
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@ -10,9 +10,9 @@ This document is based on the ARM booting document by Russell King and
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is relevant to all public releases of the AArch64 Linux kernel.
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The AArch64 exception model is made up of a number of exception levels
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(EL0 - EL3), with EL0 and EL1 having a secure and a non-secure
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counterpart. EL2 is the hypervisor level and exists only in non-secure
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mode. EL3 is the highest priority level and exists only in secure mode.
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(EL0 - EL3), with EL0, EL1 and EL2 having a secure and a non-secure
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counterpart. EL2 is the hypervisor level, EL3 is the highest priority
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level and exists only in secure mode. Both are architecturally optional.
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For the purposes of this document, we will use the term `boot loader`
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simply to define all software that executes on the CPU(s) before control
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@ -167,8 +167,8 @@ Before jumping into the kernel, the following conditions must be met:
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All forms of interrupts must be masked in PSTATE.DAIF (Debug, SError,
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IRQ and FIQ).
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The CPU must be in either EL2 (RECOMMENDED in order to have access to
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the virtualisation extensions) or non-secure EL1.
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The CPU must be in non-secure state, either in EL2 (RECOMMENDED in order
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to have access to the virtualisation extensions), or in EL1.
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- Caches, MMUs
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@ -91,8 +91,9 @@ mode is specified, the program will run in that mode. If multiple
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modes are specified, the mode is selected as described in the "Per-CPU
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preferred tag checking modes" section below.
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The current tag check fault mode can be read using the
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``prctl(PR_GET_TAGGED_ADDR_CTRL, 0, 0, 0, 0)`` system call.
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The current tag check fault configuration can be read using the
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``prctl(PR_GET_TAGGED_ADDR_CTRL, 0, 0, 0, 0)`` system call. If
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multiple modes were requested then all will be reported.
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Tag checking can also be disabled for a user thread by setting the
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``PSTATE.TCO`` bit with ``MSR TCO, #1``.
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