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OpenCloudOS-Kernel
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Merge branch 'release' of git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux-2.6 

* 'release' of git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux-2.6:
  [IA64] SGI Altix : fix pcibr_dmamap_ate32() bug
  [IA64] Fix CPU freq displayed in /proc/cpuinfo
  [IA64] Fix wrong assumption about irq and vector in msi_ia64.c
  [IA64] BTE error timer fix
This commit is contained in:
Linus Torvalds 2007-04-10 17:21:57 -07:00
parent 90f30eccf4 2e0d232bff
commit b4dfd6bc35
5 changed files with 15 additions and 10 deletions
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4
arch/ia64/kernel/msi_ia64.c
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@ -76,7 +76,7 @@ int ia64_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
set_irq_msi(irq, desc); set_irq_msi(irq, desc);
dest_phys_id = cpu_physical_id(first_cpu(cpu_online_map)); dest_phys_id = cpu_physical_id(first_cpu(cpu_online_map));
vector = irq; vector = irq_to_vector(irq);
msg.address_hi = 0; msg.address_hi = 0;
msg.address_lo = msg.address_lo =
@ -110,7 +110,7 @@ static void ia64_ack_msi_irq(unsigned int irq)
static int ia64_msi_retrigger_irq(unsigned int irq) static int ia64_msi_retrigger_irq(unsigned int irq)
{ {
unsigned int vector = irq; unsigned int vector = irq_to_vector(irq);
ia64_resend_irq(vector); ia64_resend_irq(vector);
return 1; return 1;

2
arch/ia64/kernel/setup.c
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@ -640,7 +640,7 @@ show_cpuinfo (struct seq_file *m, void *v)
"features : %s\n" "features : %s\n"
"cpu number : %lu\n" "cpu number : %lu\n"
"cpu regs : %u\n" "cpu regs : %u\n"
"cpu MHz : %lu.%06lu\n" "cpu MHz : %lu.%03lu\n"
"itc MHz : %lu.%06lu\n" "itc MHz : %lu.%06lu\n"
"BogoMIPS : %lu.%02lu\n", "BogoMIPS : %lu.%02lu\n",
cpunum, c->vendor, c->family, c->model, cpunum, c->vendor, c->family, c->model,

6
arch/ia64/sn/kernel/bte_error.c
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@ -78,7 +78,7 @@ int shub1_bte_error_handler(unsigned long _nodepda)
* There are errors which still need to be cleaned up by * There are errors which still need to be cleaned up by
* hubiio_crb_error_handler * hubiio_crb_error_handler
*/ */
mod_timer(recovery_timer, HZ * 5); mod_timer(recovery_timer, jiffies + (HZ * 5));
BTE_PRINTK(("eh:%p:%d Marked Giving up\n", err_nodepda, BTE_PRINTK(("eh:%p:%d Marked Giving up\n", err_nodepda,
smp_processor_id())); smp_processor_id()));
return 1; return 1;
@ -95,7 +95,7 @@ int shub1_bte_error_handler(unsigned long _nodepda)
icrbd.ii_icrb0_d_regval = icrbd.ii_icrb0_d_regval =
REMOTE_HUB_L(nasid, IIO_ICRB_D(i)); REMOTE_HUB_L(nasid, IIO_ICRB_D(i));
if (icrbd.d_bteop) { if (icrbd.d_bteop) {
mod_timer(recovery_timer, HZ * 5); mod_timer(recovery_timer, jiffies + (HZ * 5));
BTE_PRINTK(("eh:%p:%d Valid %d, Giving up\n", BTE_PRINTK(("eh:%p:%d Valid %d, Giving up\n",
err_nodepda, smp_processor_id(), err_nodepda, smp_processor_id(),
i)); i));
@ -150,7 +150,7 @@ int shub2_bte_error_handler(unsigned long _nodepda)
status = BTE_LNSTAT_LOAD(bte); status = BTE_LNSTAT_LOAD(bte);
if ((status & IBLS_ERROR) || !(status & IBLS_BUSY)) if ((status & IBLS_ERROR) || !(status & IBLS_BUSY))
continue; continue;
mod_timer(recovery_timer, HZ * 5); mod_timer(recovery_timer, jiffies + (HZ * 5));
BTE_PRINTK(("eh:%p:%d Marked Giving up\n", err_nodepda, BTE_PRINTK(("eh:%p:%d Marked Giving up\n", err_nodepda,
smp_processor_id())); smp_processor_id()));
return 1; return 1;

8
arch/ia64/sn/pci/pcibr/pcibr_dma.c
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@ -96,10 +96,14 @@ pcibr_dmamap_ate32(struct pcidev_info *info,
} }
/* /*
* If we're mapping for MSI, set the MSI bit in the ATE * If we're mapping for MSI, set the MSI bit in the ATE. If it's a
* TIOCP based pci bus, we also need to set the PIO bit in the ATE.
*/ */
if (dma_flags & SN_DMA_MSI) if (dma_flags & SN_DMA_MSI) {
ate |= PCI32_ATE_MSI; ate |= PCI32_ATE_MSI;
if (IS_TIOCP_SOFT(pcibus_info))
ate |= PCI32_ATE_PIO;
}
ate_write(pcibus_info, ate_index, ate_count, ate); ate_write(pcibus_info, ate_index, ate_count, ate);

5
include/asm-ia64/sn/pcibr_provider.h
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@ -21,6 +21,7 @@
#define IS_PCI_BRIDGE_ASIC(asic) (asic == PCIIO_ASIC_TYPE_PIC || \ #define IS_PCI_BRIDGE_ASIC(asic) (asic == PCIIO_ASIC_TYPE_PIC || \
asic == PCIIO_ASIC_TYPE_TIOCP) asic == PCIIO_ASIC_TYPE_TIOCP)
#define IS_PIC_SOFT(ps) (ps->pbi_bridge_type == PCIBR_BRIDGETYPE_PIC) #define IS_PIC_SOFT(ps) (ps->pbi_bridge_type == PCIBR_BRIDGETYPE_PIC)
#define IS_TIOCP_SOFT(ps) (ps->pbi_bridge_type == PCIBR_BRIDGETYPE_TIOCP)
/* /*
@ -53,8 +54,8 @@
* Bridge PMU Address Transaltion Entry Attibutes * Bridge PMU Address Transaltion Entry Attibutes
*/ */
#define PCI32_ATE_V (0x1 << 0) #define PCI32_ATE_V (0x1 << 0)
#define PCI32_ATE_CO (0x1 << 1) #define PCI32_ATE_CO (0x1 << 1) /* PIC ASIC ONLY */
#define PCI32_ATE_PREC (0x1 << 2) #define PCI32_ATE_PIO (0x1 << 1) /* TIOCP ASIC ONLY */
#define PCI32_ATE_MSI (0x1 << 2) #define PCI32_ATE_MSI (0x1 << 2)
#define PCI32_ATE_PREF (0x1 << 3) #define PCI32_ATE_PREF (0x1 << 3)
#define PCI32_ATE_BAR (0x1 << 4) #define PCI32_ATE_BAR (0x1 << 4)