drm/i915: Use pci_iomap for remapping the MMIO registers.
Play safe and use the common routines which take care of the cachability of the memory when setting up the iomapping for the PCI registers. Whilst they should be cacheable for the current generations, actually honouring what the device requires is a better long term strategy. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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@ -1888,7 +1888,6 @@ EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
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int i915_driver_load(struct drm_device *dev, unsigned long flags)
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{
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struct drm_i915_private *dev_priv;
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resource_size_t base, size;
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int ret = 0, mmio_bar;
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uint32_t agp_size, prealloc_size;
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/* i915 has 4 more counters */
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@ -1906,11 +1905,6 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
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dev_priv->dev = dev;
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dev_priv->info = (struct intel_device_info *) flags;
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/* Add register map (needed for suspend/resume) */
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mmio_bar = IS_GEN2(dev) ? 1 : 0;
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base = pci_resource_start(dev->pdev, mmio_bar);
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size = pci_resource_len(dev->pdev, mmio_bar);
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if (i915_get_bridge_dev(dev)) {
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ret = -EIO;
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goto free_priv;
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@ -1920,6 +1914,14 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
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if (IS_GEN2(dev))
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dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
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mmio_bar = IS_GEN2(dev) ? 1 : 0;
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dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, 0);
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if (!dev_priv->regs) {
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DRM_ERROR("failed to map registers\n");
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ret = -EIO;
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goto put_bridge;
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}
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dev_priv->mm.gtt = intel_gtt_get();
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if (!dev_priv->mm.gtt) {
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DRM_ERROR("Failed to initialize GTT\n");
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@ -1930,13 +1932,6 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
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prealloc_size = dev_priv->mm.gtt->gtt_stolen_entries << PAGE_SHIFT;
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agp_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
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dev_priv->regs = ioremap(base, size);
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if (!dev_priv->regs) {
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DRM_ERROR("failed to map registers\n");
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ret = -EIO;
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goto put_bridge;
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}
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dev_priv->mm.gtt_mapping =
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io_mapping_create_wc(dev->agp->base, agp_size);
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if (dev_priv->mm.gtt_mapping == NULL) {
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