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drm/amd/powerplay: move dpm feature enablement checking to smu_cmn.c 

Considering it is shared by all ASICs and smu_cmn.c should be
the right place.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Evan Quan 2020-07-07 11:10:39 +08:00 committed by Alex Deucher
parent 4d942ae349
commit b4bb3aaf04
10 changed files with 95 additions and 87 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

23
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
View File

@ -540,29 +540,6 @@ static int smu_get_driver_allowed_feature_mask(struct smu_context *smu)
return ret; return ret;
} }
int smu_feature_is_enabled(struct smu_context *smu, enum smu_feature_mask mask)
{
struct smu_feature *feature = &smu->smu_feature;
int feature_id;
int ret = 0;
if (smu->is_apu)
return 1;
feature_id = smu_cmn_to_asic_specific_index(smu,
CMN2ASIC_MAPPING_FEATURE,
mask);
if (feature_id < 0)
return 0;
WARN_ON(feature_id > feature->feature_num);
mutex_lock(&feature->mutex);
ret = test_bit(feature_id, feature->enabled);
mutex_unlock(&feature->mutex);
return ret;
}
int smu_feature_set_enabled(struct smu_context *smu, enum smu_feature_mask mask, int smu_feature_set_enabled(struct smu_context *smu, enum smu_feature_mask mask,
bool enable) bool enable)
{ {

29
drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
View File

@ -280,7 +280,7 @@ static int arcturus_set_default_dpm_table(struct smu_context *smu)
/* socclk dpm table setup */ /* socclk dpm table setup */
dpm_table = &dpm_context->dpm_tables.soc_table; dpm_table = &dpm_context->dpm_tables.soc_table;
if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
ret = smu_v11_0_set_single_dpm_table(smu, ret = smu_v11_0_set_single_dpm_table(smu,
SMU_SOCCLK, SMU_SOCCLK,
dpm_table); dpm_table);
@ -298,7 +298,7 @@ static int arcturus_set_default_dpm_table(struct smu_context *smu)
/* gfxclk dpm table setup */ /* gfxclk dpm table setup */
dpm_table = &dpm_context->dpm_tables.gfx_table; dpm_table = &dpm_context->dpm_tables.gfx_table;
if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) { if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
ret = smu_v11_0_set_single_dpm_table(smu, ret = smu_v11_0_set_single_dpm_table(smu,
SMU_GFXCLK, SMU_GFXCLK,
dpm_table); dpm_table);
@ -316,7 +316,7 @@ static int arcturus_set_default_dpm_table(struct smu_context *smu)
/* memclk dpm table setup */ /* memclk dpm table setup */
dpm_table = &dpm_context->dpm_tables.uclk_table; dpm_table = &dpm_context->dpm_tables.uclk_table;
if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
ret = smu_v11_0_set_single_dpm_table(smu, ret = smu_v11_0_set_single_dpm_table(smu,
SMU_UCLK, SMU_UCLK,
dpm_table); dpm_table);
@ -334,7 +334,7 @@ static int arcturus_set_default_dpm_table(struct smu_context *smu)
/* fclk dpm table setup */ /* fclk dpm table setup */
dpm_table = &dpm_context->dpm_tables.fclk_table; dpm_table = &dpm_context->dpm_tables.fclk_table;
if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) { if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
ret = smu_v11_0_set_single_dpm_table(smu, ret = smu_v11_0_set_single_dpm_table(smu,
SMU_FCLK, SMU_FCLK,
dpm_table); dpm_table);
@ -650,31 +650,31 @@ static int arcturus_get_current_clk_freq_by_table(struct smu_context *smu,
* We can use Average_* for dpm disabled case. * We can use Average_* for dpm disabled case.
* But this is available for gfxclk/uclk/socclk/vclk/dclk. * But this is available for gfxclk/uclk/socclk/vclk/dclk.
*/ */
if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT))
member_type = METRICS_CURR_GFXCLK; member_type = METRICS_CURR_GFXCLK;
else else
member_type = METRICS_AVERAGE_GFXCLK; member_type = METRICS_AVERAGE_GFXCLK;
break; break;
case PPCLK_UCLK: case PPCLK_UCLK:
if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT))
member_type = METRICS_CURR_UCLK; member_type = METRICS_CURR_UCLK;
else else
member_type = METRICS_AVERAGE_UCLK; member_type = METRICS_AVERAGE_UCLK;
break; break;
case PPCLK_SOCCLK: case PPCLK_SOCCLK:
if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT))
member_type = METRICS_CURR_SOCCLK; member_type = METRICS_CURR_SOCCLK;
else else
member_type = METRICS_AVERAGE_SOCCLK; member_type = METRICS_AVERAGE_SOCCLK;
break; break;
case PPCLK_VCLK: case PPCLK_VCLK:
if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT))
member_type = METRICS_CURR_VCLK; member_type = METRICS_CURR_VCLK;
else else
member_type = METRICS_AVERAGE_VCLK; member_type = METRICS_AVERAGE_VCLK;
break; break;
case PPCLK_DCLK: case PPCLK_DCLK:
if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT))
member_type = METRICS_CURR_DCLK; member_type = METRICS_CURR_DCLK;
else else
member_type = METRICS_AVERAGE_DCLK; member_type = METRICS_AVERAGE_DCLK;
@ -820,7 +820,7 @@ static int arcturus_upload_dpm_level(struct smu_context *smu,
uint32_t freq; uint32_t freq;
int ret = 0; int ret = 0;
if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) && if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
(feature_mask & FEATURE_DPM_GFXCLK_MASK)) { (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
freq = dpm_context->dpm_tables.gfx_table.dpm_levels[level].value; freq = dpm_context->dpm_tables.gfx_table.dpm_levels[level].value;
ret = smu_send_smc_msg_with_param(smu, ret = smu_send_smc_msg_with_param(smu,
@ -834,7 +834,7 @@ static int arcturus_upload_dpm_level(struct smu_context *smu,
} }
} }
if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) && if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
(feature_mask & FEATURE_DPM_UCLK_MASK)) { (feature_mask & FEATURE_DPM_UCLK_MASK)) {
freq = dpm_context->dpm_tables.uclk_table.dpm_levels[level].value; freq = dpm_context->dpm_tables.uclk_table.dpm_levels[level].value;
ret = smu_send_smc_msg_with_param(smu, ret = smu_send_smc_msg_with_param(smu,
@ -848,7 +848,7 @@ static int arcturus_upload_dpm_level(struct smu_context *smu,
} }
} }
if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) && if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) &&
(feature_mask & FEATURE_DPM_SOCCLK_MASK)) { (feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
freq = dpm_context->dpm_tables.soc_table.dpm_levels[level].value; freq = dpm_context->dpm_tables.soc_table.dpm_levels[level].value;
ret = smu_send_smc_msg_with_param(smu, ret = smu_send_smc_msg_with_param(smu,
@ -1837,7 +1837,7 @@ static int arcturus_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
int ret = 0; int ret = 0;
if (enable) { if (enable) {
if (!smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) { if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
ret = smu_feature_set_enabled(smu, SMU_FEATURE_VCN_PG_BIT, 1); ret = smu_feature_set_enabled(smu, SMU_FEATURE_VCN_PG_BIT, 1);
if (ret) { if (ret) {
dev_err(smu->adev->dev, "[EnableVCNDPM] failed!\n"); dev_err(smu->adev->dev, "[EnableVCNDPM] failed!\n");
@ -1846,7 +1846,7 @@ static int arcturus_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
} }
power_gate->vcn_gated = false; power_gate->vcn_gated = false;
} else { } else {
if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) { if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
ret = smu_feature_set_enabled(smu, SMU_FEATURE_VCN_PG_BIT, 0); ret = smu_feature_set_enabled(smu, SMU_FEATURE_VCN_PG_BIT, 0);
if (ret) { if (ret) {
dev_err(smu->adev->dev, "[DisableVCNDPM] failed!\n"); dev_err(smu->adev->dev, "[DisableVCNDPM] failed!\n");
@ -2285,6 +2285,7 @@ static const struct pptable_funcs arcturus_ppt_funcs = {
.init_display_count = NULL, .init_display_count = NULL,
.set_allowed_mask = smu_v11_0_set_allowed_mask, .set_allowed_mask = smu_v11_0_set_allowed_mask,
.get_enabled_mask = smu_v11_0_get_enabled_mask, .get_enabled_mask = smu_v11_0_get_enabled_mask,
.feature_is_enabled = smu_cmn_feature_is_enabled,
.notify_display_change = NULL, .notify_display_change = NULL,
.set_power_limit = smu_v11_0_set_power_limit, .set_power_limit = smu_v11_0_set_power_limit,
.init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks, .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,

3
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
View File

@ -533,6 +533,7 @@ struct pptable_funcs {
int (*init_display_count)(struct smu_context *smu, uint32_t count); int (*init_display_count)(struct smu_context *smu, uint32_t count);
int (*set_allowed_mask)(struct smu_context *smu); int (*set_allowed_mask)(struct smu_context *smu);
int (*get_enabled_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num); int (*get_enabled_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num);
int (*feature_is_enabled)(struct smu_context *smu, enum smu_feature_mask mask);
int (*notify_display_change)(struct smu_context *smu); int (*notify_display_change)(struct smu_context *smu);
int (*set_power_limit)(struct smu_context *smu, uint32_t n); int (*set_power_limit)(struct smu_context *smu, uint32_t n);
int (*init_max_sustainable_clocks)(struct smu_context *smu); int (*init_max_sustainable_clocks)(struct smu_context *smu);
@ -728,8 +729,6 @@ extern const struct amd_ip_funcs smu_ip_funcs;
extern const struct amdgpu_ip_block_version smu_v11_0_ip_block; extern const struct amdgpu_ip_block_version smu_v11_0_ip_block;
extern const struct amdgpu_ip_block_version smu_v12_0_ip_block; extern const struct amdgpu_ip_block_version smu_v12_0_ip_block;
extern int smu_feature_is_enabled(struct smu_context *smu,
enum smu_feature_mask mask);
extern int smu_feature_set_enabled(struct smu_context *smu, extern int smu_feature_set_enabled(struct smu_context *smu,
enum smu_feature_mask mask, bool enable); enum smu_feature_mask mask, bool enable);

31
drivers/gpu/drm/amd/powerplay/navi10_ppt.c
View File

@ -601,7 +601,7 @@ static int navi10_set_default_dpm_table(struct smu_context *smu)
/* socclk dpm table setup */ /* socclk dpm table setup */
dpm_table = &dpm_context->dpm_tables.soc_table; dpm_table = &dpm_context->dpm_tables.soc_table;
if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
ret = smu_v11_0_set_single_dpm_table(smu, ret = smu_v11_0_set_single_dpm_table(smu,
SMU_SOCCLK, SMU_SOCCLK,
dpm_table); dpm_table);
@ -619,7 +619,7 @@ static int navi10_set_default_dpm_table(struct smu_context *smu)
/* gfxclk dpm table setup */ /* gfxclk dpm table setup */
dpm_table = &dpm_context->dpm_tables.gfx_table; dpm_table = &dpm_context->dpm_tables.gfx_table;
if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) { if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
ret = smu_v11_0_set_single_dpm_table(smu, ret = smu_v11_0_set_single_dpm_table(smu,
SMU_GFXCLK, SMU_GFXCLK,
dpm_table); dpm_table);
@ -637,7 +637,7 @@ static int navi10_set_default_dpm_table(struct smu_context *smu)
/* uclk dpm table setup */ /* uclk dpm table setup */
dpm_table = &dpm_context->dpm_tables.uclk_table; dpm_table = &dpm_context->dpm_tables.uclk_table;
if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
ret = smu_v11_0_set_single_dpm_table(smu, ret = smu_v11_0_set_single_dpm_table(smu,
SMU_UCLK, SMU_UCLK,
dpm_table); dpm_table);
@ -655,7 +655,7 @@ static int navi10_set_default_dpm_table(struct smu_context *smu)
/* vclk dpm table setup */ /* vclk dpm table setup */
dpm_table = &dpm_context->dpm_tables.vclk_table; dpm_table = &dpm_context->dpm_tables.vclk_table;
if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) { if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
ret = smu_v11_0_set_single_dpm_table(smu, ret = smu_v11_0_set_single_dpm_table(smu,
SMU_VCLK, SMU_VCLK,
dpm_table); dpm_table);
@ -673,7 +673,7 @@ static int navi10_set_default_dpm_table(struct smu_context *smu)
/* dclk dpm table setup */ /* dclk dpm table setup */
dpm_table = &dpm_context->dpm_tables.dclk_table; dpm_table = &dpm_context->dpm_tables.dclk_table;
if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) { if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
ret = smu_v11_0_set_single_dpm_table(smu, ret = smu_v11_0_set_single_dpm_table(smu,
SMU_DCLK, SMU_DCLK,
dpm_table); dpm_table);
@ -691,7 +691,7 @@ static int navi10_set_default_dpm_table(struct smu_context *smu)
/* dcefclk dpm table setup */ /* dcefclk dpm table setup */
dpm_table = &dpm_context->dpm_tables.dcef_table; dpm_table = &dpm_context->dpm_tables.dcef_table;
if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
ret = smu_v11_0_set_single_dpm_table(smu, ret = smu_v11_0_set_single_dpm_table(smu,
SMU_DCEFCLK, SMU_DCEFCLK,
dpm_table); dpm_table);
@ -709,7 +709,7 @@ static int navi10_set_default_dpm_table(struct smu_context *smu)
/* pixelclk dpm table setup */ /* pixelclk dpm table setup */
dpm_table = &dpm_context->dpm_tables.pixel_table; dpm_table = &dpm_context->dpm_tables.pixel_table;
if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
ret = smu_v11_0_set_single_dpm_table(smu, ret = smu_v11_0_set_single_dpm_table(smu,
SMU_PIXCLK, SMU_PIXCLK,
dpm_table); dpm_table);
@ -727,7 +727,7 @@ static int navi10_set_default_dpm_table(struct smu_context *smu)
/* displayclk dpm table setup */ /* displayclk dpm table setup */
dpm_table = &dpm_context->dpm_tables.display_table; dpm_table = &dpm_context->dpm_tables.display_table;
if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
ret = smu_v11_0_set_single_dpm_table(smu, ret = smu_v11_0_set_single_dpm_table(smu,
SMU_DISPCLK, SMU_DISPCLK,
dpm_table); dpm_table);
@ -745,7 +745,7 @@ static int navi10_set_default_dpm_table(struct smu_context *smu)
/* phyclk dpm table setup */ /* phyclk dpm table setup */
dpm_table = &dpm_context->dpm_tables.phy_table; dpm_table = &dpm_context->dpm_tables.phy_table;
if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
ret = smu_v11_0_set_single_dpm_table(smu, ret = smu_v11_0_set_single_dpm_table(smu,
SMU_PHYCLK, SMU_PHYCLK,
dpm_table); dpm_table);
@ -772,14 +772,14 @@ static int navi10_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
if (enable) { if (enable) {
/* vcn dpm on is a prerequisite for vcn power gate messages */ /* vcn dpm on is a prerequisite for vcn power gate messages */
if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) { if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 1, NULL); ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 1, NULL);
if (ret) if (ret)
return ret; return ret;
} }
power_gate->vcn_gated = false; power_gate->vcn_gated = false;
} else { } else {
if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) { if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownVcn, NULL); ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownVcn, NULL);
if (ret) if (ret)
return ret; return ret;
@ -797,14 +797,14 @@ static int navi10_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
int ret = 0; int ret = 0;
if (enable) { if (enable) {
if (smu_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) { if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
ret = smu_send_smc_msg(smu, SMU_MSG_PowerUpJpeg, NULL); ret = smu_send_smc_msg(smu, SMU_MSG_PowerUpJpeg, NULL);
if (ret) if (ret)
return ret; return ret;
} }
power_gate->jpeg_gated = false; power_gate->jpeg_gated = false;
} else { } else {
if (smu_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) { if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownJpeg, NULL); ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownJpeg, NULL);
if (ret) if (ret)
return ret; return ret;
@ -1249,7 +1249,7 @@ static int navi10_pre_display_config_changed(struct smu_context *smu)
if (ret) if (ret)
return ret; return ret;
if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &max_freq); ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &max_freq);
if (ret) if (ret)
return ret; return ret;
@ -1565,7 +1565,7 @@ static int navi10_notify_smc_display_config(struct smu_context *smu)
} }
} }
if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0); ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);
if (ret) { if (ret) {
dev_err(smu->adev->dev, "[%s] Set hard min uclk failed!", __func__); dev_err(smu->adev->dev, "[%s] Set hard min uclk failed!", __func__);
@ -2300,6 +2300,7 @@ static const struct pptable_funcs navi10_ppt_funcs = {
.init_display_count = smu_v11_0_init_display_count, .init_display_count = smu_v11_0_init_display_count,
.set_allowed_mask = smu_v11_0_set_allowed_mask, .set_allowed_mask = smu_v11_0_set_allowed_mask,
.get_enabled_mask = smu_v11_0_get_enabled_mask, .get_enabled_mask = smu_v11_0_get_enabled_mask,
.feature_is_enabled = smu_cmn_feature_is_enabled,
.notify_display_change = smu_v11_0_notify_display_change, .notify_display_change = smu_v11_0_notify_display_change,
.set_power_limit = smu_v11_0_set_power_limit, .set_power_limit = smu_v11_0_set_power_limit,
.init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks, .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,

11
drivers/gpu/drm/amd/powerplay/renoir_ppt.c
View File

@ -463,14 +463,14 @@ static int renoir_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
if (enable) { if (enable) {
/* vcn dpm on is a prerequisite for vcn power gate messages */ /* vcn dpm on is a prerequisite for vcn power gate messages */
if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) { if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL); ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL);
if (ret) if (ret)
return ret; return ret;
} }
power_gate->vcn_gated = false; power_gate->vcn_gated = false;
} else { } else {
if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) { if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownVcn, NULL); ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownVcn, NULL);
if (ret) if (ret)
return ret; return ret;
@ -488,14 +488,14 @@ static int renoir_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
int ret = 0; int ret = 0;
if (enable) { if (enable) {
if (smu_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) { if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL); ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL);
if (ret) if (ret)
return ret; return ret;
} }
power_gate->jpeg_gated = false; power_gate->jpeg_gated = false;
} else { } else {
if (smu_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) { if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL); ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL);
if (ret) if (ret)
return ret; return ret;
@ -571,7 +571,7 @@ static int renoir_unforce_dpm_levels(struct smu_context *smu) {
}; };
for (i = 0; i < ARRAY_SIZE(clk_feature_map); i++) { for (i = 0; i < ARRAY_SIZE(clk_feature_map); i++) {
if (!smu_feature_is_enabled(smu, clk_feature_map[i].feature)) if (!smu_cmn_feature_is_enabled(smu, clk_feature_map[i].feature))
continue; continue;
clk_type = clk_feature_map[i].clk_type; clk_type = clk_feature_map[i].clk_type;
@ -1019,6 +1019,7 @@ static const struct pptable_funcs renoir_ppt_funcs = {
.fini_smc_tables = smu_v12_0_fini_smc_tables, .fini_smc_tables = smu_v12_0_fini_smc_tables,
.set_default_dpm_table = smu_v12_0_set_default_dpm_tables, .set_default_dpm_table = smu_v12_0_set_default_dpm_tables,
.get_enabled_mask = smu_v12_0_get_enabled_mask, .get_enabled_mask = smu_v12_0_get_enabled_mask,
.feature_is_enabled = smu_cmn_feature_is_enabled,
.get_dpm_ultimate_freq = renoir_get_dpm_ultimate_freq, .get_dpm_ultimate_freq = renoir_get_dpm_ultimate_freq,
.mode2_reset = smu_v12_0_mode2_reset, .mode2_reset = smu_v12_0_mode2_reset,
.set_soft_freq_limited_range = smu_v12_0_set_soft_freq_limited_range, .set_soft_freq_limited_range = smu_v12_0_set_soft_freq_limited_range,

37
drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
View File

@ -515,7 +515,7 @@ static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
/* socclk dpm table setup */ /* socclk dpm table setup */
dpm_table = &dpm_context->dpm_tables.soc_table; dpm_table = &dpm_context->dpm_tables.soc_table;
if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
ret = smu_v11_0_set_single_dpm_table(smu, ret = smu_v11_0_set_single_dpm_table(smu,
SMU_SOCCLK, SMU_SOCCLK,
dpm_table); dpm_table);
@ -533,7 +533,7 @@ static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
/* gfxclk dpm table setup */ /* gfxclk dpm table setup */
dpm_table = &dpm_context->dpm_tables.gfx_table; dpm_table = &dpm_context->dpm_tables.gfx_table;
if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) { if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
ret = smu_v11_0_set_single_dpm_table(smu, ret = smu_v11_0_set_single_dpm_table(smu,
SMU_GFXCLK, SMU_GFXCLK,
dpm_table); dpm_table);
@ -551,7 +551,7 @@ static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
/* uclk dpm table setup */ /* uclk dpm table setup */
dpm_table = &dpm_context->dpm_tables.uclk_table; dpm_table = &dpm_context->dpm_tables.uclk_table;
if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
ret = smu_v11_0_set_single_dpm_table(smu, ret = smu_v11_0_set_single_dpm_table(smu,
SMU_UCLK, SMU_UCLK,
dpm_table); dpm_table);
@ -569,7 +569,7 @@ static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
/* fclk dpm table setup */ /* fclk dpm table setup */
dpm_table = &dpm_context->dpm_tables.fclk_table; dpm_table = &dpm_context->dpm_tables.fclk_table;
if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) { if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
ret = smu_v11_0_set_single_dpm_table(smu, ret = smu_v11_0_set_single_dpm_table(smu,
SMU_FCLK, SMU_FCLK,
dpm_table); dpm_table);
@ -587,7 +587,7 @@ static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
/* vclk0 dpm table setup */ /* vclk0 dpm table setup */
dpm_table = &dpm_context->dpm_tables.vclk_table; dpm_table = &dpm_context->dpm_tables.vclk_table;
if (smu_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) { if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
ret = smu_v11_0_set_single_dpm_table(smu, ret = smu_v11_0_set_single_dpm_table(smu,
SMU_VCLK, SMU_VCLK,
dpm_table); dpm_table);
@ -605,7 +605,7 @@ static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
/* vclk1 dpm table setup */ /* vclk1 dpm table setup */
dpm_table = &dpm_context->dpm_tables.vclk1_table; dpm_table = &dpm_context->dpm_tables.vclk1_table;
if (smu_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) { if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
ret = smu_v11_0_set_single_dpm_table(smu, ret = smu_v11_0_set_single_dpm_table(smu,
SMU_VCLK1, SMU_VCLK1,
dpm_table); dpm_table);
@ -623,7 +623,7 @@ static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
/* dclk0 dpm table setup */ /* dclk0 dpm table setup */
dpm_table = &dpm_context->dpm_tables.dclk_table; dpm_table = &dpm_context->dpm_tables.dclk_table;
if (smu_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) { if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
ret = smu_v11_0_set_single_dpm_table(smu, ret = smu_v11_0_set_single_dpm_table(smu,
SMU_DCLK, SMU_DCLK,
dpm_table); dpm_table);
@ -641,7 +641,7 @@ static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
/* dclk1 dpm table setup */ /* dclk1 dpm table setup */
dpm_table = &dpm_context->dpm_tables.dclk1_table; dpm_table = &dpm_context->dpm_tables.dclk1_table;
if (smu_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) { if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
ret = smu_v11_0_set_single_dpm_table(smu, ret = smu_v11_0_set_single_dpm_table(smu,
SMU_DCLK1, SMU_DCLK1,
dpm_table); dpm_table);
@ -659,7 +659,7 @@ static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
/* dcefclk dpm table setup */ /* dcefclk dpm table setup */
dpm_table = &dpm_context->dpm_tables.dcef_table; dpm_table = &dpm_context->dpm_tables.dcef_table;
if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
ret = smu_v11_0_set_single_dpm_table(smu, ret = smu_v11_0_set_single_dpm_table(smu,
SMU_DCEFCLK, SMU_DCEFCLK,
dpm_table); dpm_table);
@ -677,7 +677,7 @@ static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
/* pixelclk dpm table setup */ /* pixelclk dpm table setup */
dpm_table = &dpm_context->dpm_tables.pixel_table; dpm_table = &dpm_context->dpm_tables.pixel_table;
if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
ret = smu_v11_0_set_single_dpm_table(smu, ret = smu_v11_0_set_single_dpm_table(smu,
SMU_PIXCLK, SMU_PIXCLK,
dpm_table); dpm_table);
@ -695,7 +695,7 @@ static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
/* displayclk dpm table setup */ /* displayclk dpm table setup */
dpm_table = &dpm_context->dpm_tables.display_table; dpm_table = &dpm_context->dpm_tables.display_table;
if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
ret = smu_v11_0_set_single_dpm_table(smu, ret = smu_v11_0_set_single_dpm_table(smu,
SMU_DISPCLK, SMU_DISPCLK,
dpm_table); dpm_table);
@ -713,7 +713,7 @@ static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
/* phyclk dpm table setup */ /* phyclk dpm table setup */
dpm_table = &dpm_context->dpm_tables.phy_table; dpm_table = &dpm_context->dpm_tables.phy_table;
if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
ret = smu_v11_0_set_single_dpm_table(smu, ret = smu_v11_0_set_single_dpm_table(smu,
SMU_PHYCLK, SMU_PHYCLK,
dpm_table); dpm_table);
@ -742,7 +742,7 @@ static int sienna_cichlid_dpm_set_vcn_enable(struct smu_context *smu, bool enabl
if (enable) { if (enable) {
/* vcn dpm on is a prerequisite for vcn power gate messages */ /* vcn dpm on is a prerequisite for vcn power gate messages */
if (smu_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) { if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL); ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL);
if (ret) if (ret)
return ret; return ret;
@ -755,7 +755,7 @@ static int sienna_cichlid_dpm_set_vcn_enable(struct smu_context *smu, bool enabl
} }
power_gate->vcn_gated = false; power_gate->vcn_gated = false;
} else { } else {
if (smu_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) { if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn, 0, NULL); ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn, 0, NULL);
if (ret) if (ret)
return ret; return ret;
@ -779,14 +779,14 @@ static int sienna_cichlid_dpm_set_jpeg_enable(struct smu_context *smu, bool enab
int ret = 0; int ret = 0;
if (enable) { if (enable) {
if (smu_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) { if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL); ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL);
if (ret) if (ret)
return ret; return ret;
} }
power_gate->jpeg_gated = false; power_gate->jpeg_gated = false;
} else { } else {
if (smu_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) { if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL); ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL);
if (ret) if (ret)
return ret; return ret;
@ -1050,7 +1050,7 @@ static int sienna_cichlid_pre_display_config_changed(struct smu_context *smu)
return ret; return ret;
#endif #endif
if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &max_freq); ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &max_freq);
if (ret) if (ret)
return ret; return ret;
@ -1368,7 +1368,7 @@ static int sienna_cichlid_notify_smc_display_config(struct smu_context *smu)
} }
} }
if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0); ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);
if (ret) { if (ret) {
dev_err(smu->adev->dev, "[%s] Set hard min uclk failed!", __func__); dev_err(smu->adev->dev, "[%s] Set hard min uclk failed!", __func__);
@ -2451,6 +2451,7 @@ static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
.init_display_count = NULL, .init_display_count = NULL,
.set_allowed_mask = smu_v11_0_set_allowed_mask, .set_allowed_mask = smu_v11_0_set_allowed_mask,
.get_enabled_mask = smu_v11_0_get_enabled_mask, .get_enabled_mask = smu_v11_0_get_enabled_mask,
.feature_is_enabled = smu_cmn_feature_is_enabled,
.notify_display_change = NULL, .notify_display_change = NULL,
.set_power_limit = smu_v11_0_set_power_limit, .set_power_limit = smu_v11_0_set_power_limit,
.init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks, .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,

24
drivers/gpu/drm/amd/powerplay/smu_cmn.c
View File

@ -138,3 +138,27 @@ int smu_cmn_feature_is_supported(struct smu_context *smu,
return ret; return ret;
} }
int smu_cmn_feature_is_enabled(struct smu_context *smu,
enum smu_feature_mask mask)
{
struct smu_feature *feature = &smu->smu_feature;
int feature_id;
int ret = 0;
if (smu->is_apu)
return 1;
feature_id = smu_cmn_to_asic_specific_index(smu,
CMN2ASIC_MAPPING_FEATURE,
mask);
if (feature_id < 0)
return 0;
WARN_ON(feature_id > feature->feature_num);
mutex_lock(&feature->mutex);
ret = test_bit(feature_id, feature->enabled);
mutex_unlock(&feature->mutex);
return ret;
}

3
drivers/gpu/drm/amd/powerplay/smu_cmn.h
View File

@ -32,4 +32,7 @@ int smu_cmn_to_asic_specific_index(struct smu_context *smu,
int smu_cmn_feature_is_supported(struct smu_context *smu, int smu_cmn_feature_is_supported(struct smu_context *smu,
enum smu_feature_mask mask); enum smu_feature_mask mask);
int smu_cmn_feature_is_enabled(struct smu_context *smu,
enum smu_feature_mask mask);
#endif #endif

1
drivers/gpu/drm/amd/powerplay/smu_internal.h
View File

@ -55,6 +55,7 @@
#define smu_init_display_count(smu, count) smu_ppt_funcs(init_display_count, 0, smu, count) #define smu_init_display_count(smu, count) smu_ppt_funcs(init_display_count, 0, smu, count)
#define smu_feature_set_allowed_mask(smu) smu_ppt_funcs(set_allowed_mask, 0, smu) #define smu_feature_set_allowed_mask(smu) smu_ppt_funcs(set_allowed_mask, 0, smu)
#define smu_feature_get_enabled_mask(smu, mask, num) smu_ppt_funcs(get_enabled_mask, 0, smu, mask, num) #define smu_feature_get_enabled_mask(smu, mask, num) smu_ppt_funcs(get_enabled_mask, 0, smu, mask, num)
#define smu_feature_is_enabled(smu, mask) smu_ppt_funcs(feature_is_enabled, 0, smu, mask)
#define smu_is_dpm_running(smu) smu_ppt_funcs(is_dpm_running, 0 , smu) #define smu_is_dpm_running(smu) smu_ppt_funcs(is_dpm_running, 0 , smu)
#define smu_notify_display_change(smu) smu_ppt_funcs(notify_display_change, 0, smu) #define smu_notify_display_change(smu) smu_ppt_funcs(notify_display_change, 0, smu)
#define smu_set_default_dpm_table(smu) smu_ppt_funcs(set_default_dpm_table, 0, smu) #define smu_set_default_dpm_table(smu) smu_ppt_funcs(set_default_dpm_table, 0, smu)

20
drivers/gpu/drm/amd/powerplay/smu_v11_0.c
View File

@ -936,7 +936,7 @@ int smu_v11_0_notify_display_change(struct smu_context *smu)
if (!smu->pm_enabled) if (!smu->pm_enabled)
return ret; return ret;
if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) && if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
smu->adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM) smu->adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM)
ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1, NULL); ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1, NULL);
@ -994,7 +994,7 @@ int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu)
max_sustainable_clocks->phy_clock = 0xFFFFFFFF; max_sustainable_clocks->phy_clock = 0xFFFFFFFF;
max_sustainable_clocks->pixel_clock = 0xFFFFFFFF; max_sustainable_clocks->pixel_clock = 0xFFFFFFFF;
if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
ret = smu_v11_0_get_max_sustainable_clock(smu, ret = smu_v11_0_get_max_sustainable_clock(smu,
&(max_sustainable_clocks->uclock), &(max_sustainable_clocks->uclock),
SMU_UCLK); SMU_UCLK);
@ -1005,7 +1005,7 @@ int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu)
} }
} }
if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
ret = smu_v11_0_get_max_sustainable_clock(smu, ret = smu_v11_0_get_max_sustainable_clock(smu,
&(max_sustainable_clocks->soc_clock), &(max_sustainable_clocks->soc_clock),
SMU_SOCCLK); SMU_SOCCLK);
@ -1016,7 +1016,7 @@ int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu)
} }
} }
if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
ret = smu_v11_0_get_max_sustainable_clock(smu, ret = smu_v11_0_get_max_sustainable_clock(smu,
&(max_sustainable_clocks->dcef_clock), &(max_sustainable_clocks->dcef_clock),
SMU_DCEFCLK); SMU_DCEFCLK);
@ -1064,7 +1064,7 @@ int smu_v11_0_get_current_power_limit(struct smu_context *smu,
int power_src; int power_src;
int ret = 0; int ret = 0;
if (!smu_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT))
return -EINVAL; return -EINVAL;
power_src = smu_cmn_to_asic_specific_index(smu, power_src = smu_cmn_to_asic_specific_index(smu,
@ -1089,7 +1089,7 @@ int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n)
{ {
int ret = 0; int ret = 0;
if (!smu_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) { if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
dev_err(smu->adev->dev, "Setting new power limit is not supported!\n"); dev_err(smu->adev->dev, "Setting new power limit is not supported!\n");
return -EOPNOTSUPP; return -EOPNOTSUPP;
} }
@ -1152,8 +1152,8 @@ smu_v11_0_display_clock_voltage_request(struct smu_context *smu,
enum smu_clk_type clk_select = 0; enum smu_clk_type clk_select = 0;
uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000; uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) || if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) ||
smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
switch (clk_type) { switch (clk_type) {
case amd_pp_dcef_clock: case amd_pp_dcef_clock:
clk_select = SMU_DCEFCLK; clk_select = SMU_DCEFCLK;
@ -1219,7 +1219,7 @@ int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable)
uint32_t uint32_t
smu_v11_0_get_fan_control_mode(struct smu_context *smu) smu_v11_0_get_fan_control_mode(struct smu_context *smu)
{ {
if (!smu_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT)) if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT))
return AMD_FAN_CTRL_MANUAL; return AMD_FAN_CTRL_MANUAL;
else else
return AMD_FAN_CTRL_AUTO; return AMD_FAN_CTRL_AUTO;
@ -1599,7 +1599,7 @@ bool smu_v11_0_baco_is_support(struct smu_context *smu)
/* Arcturus does not support this bit mask */ /* Arcturus does not support this bit mask */
if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_BACO_BIT) && if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_BACO_BIT) &&
!smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) !smu_cmn_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT))
return false; return false;
return true; return true;