staging: brcm80211: absorb bcmsdpcm.h in fullmac
Absorb bcmsdpcm.h into dhd_sdio.c Signed-off-by: Franky Lin <frankyl@broadcom.com> Reviewed-by: Roland Vossen <rvossen@broadcom.com> Reviewed-by: Arend van Spriel <arend@broadcom.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Franky Lin
Greg Kroah-Hartman
parent
7c6100ee08
commit
b49b14d2e3
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@ -1,208 +0,0 @@
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/*
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* Copyright (c) 2010 Broadcom Corporation
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
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* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
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* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
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* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef _bcmsdpcm_h_
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#define _bcmsdpcm_h_
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/*
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* Software allocation of To SB Mailbox resources
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*/
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/* intstatus bits */
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#define I_SMB_NAK I_SMB_SW0 /* To SB Mailbox Frame NAK */
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#define I_SMB_INT_ACK I_SMB_SW1 /* To SB Mailbox Host Interrupt ACK */
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#define I_SMB_USE_OOB I_SMB_SW2 /* To SB Mailbox Use OOB Wakeup */
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#define I_SMB_DEV_INT I_SMB_SW3 /* To SB Mailbox Miscellaneous Interrupt */
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#define I_TOSBMAIL (I_SMB_NAK | I_SMB_INT_ACK | I_SMB_USE_OOB | I_SMB_DEV_INT)
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/* tosbmailbox bits corresponding to intstatus bits */
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#define SMB_NAK (1 << 0) /* To SB Mailbox Frame NAK */
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#define SMB_INT_ACK (1 << 1) /* To SB Mailbox Host Interrupt ACK */
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#define SMB_USE_OOB (1 << 2) /* To SB Mailbox Use OOB Wakeup */
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#define SMB_DEV_INT (1 << 3) /* To SB Mailbox Miscellaneous Interrupt */
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#define SMB_MASK 0x0000000f /* To SB Mailbox Mask */
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/* tosbmailboxdata */
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#define SMB_DATA_VERSION_MASK 0x00ff0000 /* host protocol version (sent with F2 enable) */
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#define SMB_DATA_VERSION_SHIFT 16 /* host protocol version (sent with F2 enable) */
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/*
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* Software allocation of To Host Mailbox resources
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*/
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/* intstatus bits */
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#define I_HMB_FC_STATE I_HMB_SW0 /* To Host Mailbox Flow Control State */
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#define I_HMB_FC_CHANGE I_HMB_SW1 /* To Host Mailbox Flow Control State Changed */
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#define I_HMB_FRAME_IND I_HMB_SW2 /* To Host Mailbox Frame Indication */
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#define I_HMB_HOST_INT I_HMB_SW3 /* To Host Mailbox Miscellaneous Interrupt */
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#define I_TOHOSTMAIL (I_HMB_FC_CHANGE | I_HMB_FRAME_IND | I_HMB_HOST_INT)
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/* tohostmailbox bits corresponding to intstatus bits */
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#define HMB_FC_ON (1 << 0) /* To Host Mailbox Flow Control State */
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#define HMB_FC_CHANGE (1 << 1) /* To Host Mailbox Flow Control State Changed */
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#define HMB_FRAME_IND (1 << 2) /* To Host Mailbox Frame Indication */
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#define HMB_HOST_INT (1 << 3) /* To Host Mailbox Miscellaneous Interrupt */
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#define HMB_MASK 0x0000000f /* To Host Mailbox Mask */
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/* tohostmailboxdata */
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#define HMB_DATA_NAKHANDLED 1 /* we're ready to retransmit NAK'd frame to host */
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#define HMB_DATA_DEVREADY 2 /* we're ready to to talk to host after enable */
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#define HMB_DATA_FC 4 /* per prio flowcontrol update flag to host */
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#define HMB_DATA_FWREADY 8 /* firmware is ready for protocol activity */
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#define HMB_DATA_FCDATA_MASK 0xff000000 /* per prio flowcontrol data */
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#define HMB_DATA_FCDATA_SHIFT 24 /* per prio flowcontrol data */
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#define HMB_DATA_VERSION_MASK 0x00ff0000 /* device protocol version (with devready) */
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#define HMB_DATA_VERSION_SHIFT 16 /* device protocol version (with devready) */
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/*
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* Software-defined protocol header
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*/
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/* Current protocol version */
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#define SDPCM_PROT_VERSION 4
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/* SW frame header */
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#define SDPCM_SEQUENCE_MASK 0x000000ff /* Sequence Number Mask */
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#define SDPCM_PACKET_SEQUENCE(p) (((u8 *)p)[0] & 0xff) /* p starts w/SW Header */
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#define SDPCM_CHANNEL_MASK 0x00000f00 /* Channel Number Mask */
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#define SDPCM_CHANNEL_SHIFT 8 /* Channel Number Shift */
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#define SDPCM_PACKET_CHANNEL(p) (((u8 *)p)[1] & 0x0f) /* p starts w/SW Header */
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#define SDPCM_FLAGS_MASK 0x0000f000 /* Mask of flag bits */
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#define SDPCM_FLAGS_SHIFT 12 /* Flag bits shift */
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#define SDPCM_PACKET_FLAGS(p) ((((u8 *)p)[1] & 0xf0) >> 4) /* p starts w/SW Header */
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/* Next Read Len: lookahead length of next frame, in 16-byte units (rounded up) */
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#define SDPCM_NEXTLEN_MASK 0x00ff0000 /* Next Read Len Mask */
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#define SDPCM_NEXTLEN_SHIFT 16 /* Next Read Len Shift */
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#define SDPCM_NEXTLEN_VALUE(p) ((((u8 *)p)[2] & 0xff) << 4) /* p starts w/SW Header */
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#define SDPCM_NEXTLEN_OFFSET 2
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/* Data Offset from SOF (HW Tag, SW Tag, Pad) */
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#define SDPCM_DOFFSET_OFFSET 3 /* Data Offset */
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#define SDPCM_DOFFSET_VALUE(p) (((u8 *)p)[SDPCM_DOFFSET_OFFSET] & 0xff)
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#define SDPCM_DOFFSET_MASK 0xff000000
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#define SDPCM_DOFFSET_SHIFT 24
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#define SDPCM_FCMASK_OFFSET 4 /* Flow control */
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#define SDPCM_FCMASK_VALUE(p) (((u8 *)p)[SDPCM_FCMASK_OFFSET] & 0xff)
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#define SDPCM_WINDOW_OFFSET 5 /* Credit based fc */
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#define SDPCM_WINDOW_VALUE(p) (((u8 *)p)[SDPCM_WINDOW_OFFSET] & 0xff)
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#define SDPCM_VERSION_OFFSET 6 /* Version # */
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#define SDPCM_VERSION_VALUE(p) (((u8 *)p)[SDPCM_VERSION_OFFSET] & 0xff)
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#define SDPCM_UNUSED_OFFSET 7 /* Spare */
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#define SDPCM_UNUSED_VALUE(p) (((u8 *)p)[SDPCM_UNUSED_OFFSET] & 0xff)
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#define SDPCM_SWHEADER_LEN 8 /* SW header is 64 bits */
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/* logical channel numbers */
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#define SDPCM_CONTROL_CHANNEL 0 /* Control Request/Response Channel Id */
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#define SDPCM_EVENT_CHANNEL 1 /* Asyc Event Indication Channel Id */
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#define SDPCM_DATA_CHANNEL 2 /* Data Xmit/Recv Channel Id */
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#define SDPCM_GLOM_CHANNEL 3 /* For coalesced packets (superframes) */
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#define SDPCM_TEST_CHANNEL 15 /* Reserved for test/debug packets */
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#define SDPCM_MAX_CHANNEL 15
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#define SDPCM_SEQUENCE_WRAP 256 /* wrap-around val for eight-bit frame seq number */
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#define SDPCM_FLAG_RESVD0 0x01
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#define SDPCM_FLAG_RESVD1 0x02
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#define SDPCM_FLAG_GSPI_TXENAB 0x04
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#define SDPCM_FLAG_GLOMDESC 0x08 /* Superframe descriptor mask */
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/* For GLOM_CHANNEL frames, use a flag to indicate descriptor frame */
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#define SDPCM_GLOMDESC_FLAG (SDPCM_FLAG_GLOMDESC << SDPCM_FLAGS_SHIFT)
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#define SDPCM_GLOMDESC(p) (((u8 *)p)[1] & 0x80)
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/* For TEST_CHANNEL packets, define another 4-byte header */
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#define SDPCM_TEST_HDRLEN 4 /* Generally: Cmd(1), Ext(1), Len(2);
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* Semantics of Ext byte depend on command.
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* Len is current or requested frame length, not
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* including test header; sent little-endian.
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*/
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#define SDPCM_TEST_DISCARD 0x01 /* Receiver discards. Ext is a pattern id. */
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#define SDPCM_TEST_ECHOREQ 0x02 /* Echo request. Ext is a pattern id. */
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#define SDPCM_TEST_ECHORSP 0x03 /* Echo response. Ext is a pattern id. */
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#define SDPCM_TEST_BURST 0x04 /* Receiver to send a burst. Ext is a frame count */
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#define SDPCM_TEST_SEND 0x05 /* Receiver sets send mode. Ext is boolean on/off */
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/* Handy macro for filling in datagen packets with a pattern */
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#define SDPCM_TEST_FILL(byteno, id) ((u8)(id + byteno))
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/*
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* Software counters (first part matches hardware counters)
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*/
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typedef volatile struct {
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u32 cmd52rd; /* Cmd52RdCount, SDIO: cmd52 reads */
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u32 cmd52wr; /* Cmd52WrCount, SDIO: cmd52 writes */
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u32 cmd53rd; /* Cmd53RdCount, SDIO: cmd53 reads */
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u32 cmd53wr; /* Cmd53WrCount, SDIO: cmd53 writes */
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u32 abort; /* AbortCount, SDIO: aborts */
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u32 datacrcerror; /* DataCrcErrorCount, SDIO: frames w/CRC error */
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u32 rdoutofsync; /* RdOutOfSyncCount, SDIO/PCMCIA: Rd Frm out of sync */
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u32 wroutofsync; /* RdOutOfSyncCount, SDIO/PCMCIA: Wr Frm out of sync */
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u32 writebusy; /* WriteBusyCount, SDIO: device asserted "busy" */
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u32 readwait; /* ReadWaitCount, SDIO: no data ready for a read cmd */
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u32 readterm; /* ReadTermCount, SDIO: read frame termination cmds */
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u32 writeterm; /* WriteTermCount, SDIO: write frames termination cmds */
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u32 rxdescuflo; /* receive descriptor underflows */
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u32 rxfifooflo; /* receive fifo overflows */
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u32 txfifouflo; /* transmit fifo underflows */
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u32 runt; /* runt (too short) frames recv'd from bus */
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u32 badlen; /* frame's rxh len does not match its hw tag len */
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u32 badcksum; /* frame's hw tag chksum doesn't agree with len value */
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u32 seqbreak; /* break in sequence # space from one rx frame to the next */
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u32 rxfcrc; /* frame rx header indicates crc error */
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u32 rxfwoos; /* frame rx header indicates write out of sync */
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u32 rxfwft; /* frame rx header indicates write frame termination */
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u32 rxfabort; /* frame rx header indicates frame aborted */
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u32 woosint; /* write out of sync interrupt */
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u32 roosint; /* read out of sync interrupt */
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u32 rftermint; /* read frame terminate interrupt */
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u32 wftermint; /* write frame terminate interrupt */
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} sdpcmd_cnt_t;
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/*
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* Shared structure between dongle and the host.
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* The structure contains pointers to trap or assert information.
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*/
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#define SDPCM_SHARED_VERSION 0x0002
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#define SDPCM_SHARED_VERSION_MASK 0x00FF
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#define SDPCM_SHARED_ASSERT_BUILT 0x0100
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#define SDPCM_SHARED_ASSERT 0x0200
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#define SDPCM_SHARED_TRAP 0x0400
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typedef struct {
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u32 flags;
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u32 trap_addr;
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u32 assert_exp_addr;
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u32 assert_file_addr;
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u32 assert_line;
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u32 console_addr; /* Address of rte_cons_t */
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u32 msgtrace_addr;
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u8 tag[32];
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} sdpcm_shared_t;
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extern sdpcm_shared_t sdpcm_shared;
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#endif /* _bcmsdpcm_h_ */
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@ -131,7 +131,6 @@ typedef struct {
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#include <sdio.h>
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#include <sbsdio.h>
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#include <sbsdpcmdev.h>
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#include <bcmsdpcm.h>
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#include <dngl_stats.h>
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#include <dhd.h>
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@ -193,6 +192,114 @@ typedef struct {
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#define SDPCM_RESERVE (SDPCM_HDRLEN + DHD_SDALIGN)
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#endif
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/*
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* Software allocation of To SB Mailbox resources
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*/
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/* tosbmailbox bits corresponding to intstatus bits */
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#define SMB_NAK (1 << 0) /* Frame NAK */
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#define SMB_INT_ACK (1 << 1) /* Host Interrupt ACK */
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#define SMB_USE_OOB (1 << 2) /* Use OOB Wakeup */
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#define SMB_DEV_INT (1 << 3) /* Miscellaneous Interrupt */
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/* tosbmailboxdata */
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#define SMB_DATA_VERSION_SHIFT 16 /* host protocol version */
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/*
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* Software allocation of To Host Mailbox resources
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*/
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/* intstatus bits */
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#define I_HMB_FC_STATE I_HMB_SW0 /* Flow Control State */
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#define I_HMB_FC_CHANGE I_HMB_SW1 /* Flow Control State Changed */
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#define I_HMB_FRAME_IND I_HMB_SW2 /* Frame Indication */
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#define I_HMB_HOST_INT I_HMB_SW3 /* Miscellaneous Interrupt */
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/* tohostmailboxdata */
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#define HMB_DATA_NAKHANDLED 1 /* retransmit NAK'd frame */
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#define HMB_DATA_DEVREADY 2 /* talk to host after enable */
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#define HMB_DATA_FC 4 /* per prio flowcontrol update flag */
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#define HMB_DATA_FWREADY 8 /* fw ready for protocol activity */
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#define HMB_DATA_FCDATA_MASK 0xff000000
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#define HMB_DATA_FCDATA_SHIFT 24
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#define HMB_DATA_VERSION_MASK 0x00ff0000
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#define HMB_DATA_VERSION_SHIFT 16
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/*
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* Software-defined protocol header
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*/
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/* Current protocol version */
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#define SDPCM_PROT_VERSION 4
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/* SW frame header */
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#define SDPCM_PACKET_SEQUENCE(p) (((u8 *)p)[0] & 0xff)
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#define SDPCM_CHANNEL_MASK 0x00000f00
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#define SDPCM_CHANNEL_SHIFT 8
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#define SDPCM_PACKET_CHANNEL(p) (((u8 *)p)[1] & 0x0f)
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#define SDPCM_NEXTLEN_OFFSET 2
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/* Data Offset from SOF (HW Tag, SW Tag, Pad) */
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#define SDPCM_DOFFSET_OFFSET 3 /* Data Offset */
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#define SDPCM_DOFFSET_VALUE(p) (((u8 *)p)[SDPCM_DOFFSET_OFFSET] & 0xff)
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#define SDPCM_DOFFSET_MASK 0xff000000
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#define SDPCM_DOFFSET_SHIFT 24
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#define SDPCM_FCMASK_OFFSET 4 /* Flow control */
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#define SDPCM_FCMASK_VALUE(p) (((u8 *)p)[SDPCM_FCMASK_OFFSET] & 0xff)
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#define SDPCM_WINDOW_OFFSET 5 /* Credit based fc */
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#define SDPCM_WINDOW_VALUE(p) (((u8 *)p)[SDPCM_WINDOW_OFFSET] & 0xff)
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#define SDPCM_SWHEADER_LEN 8 /* SW header is 64 bits */
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/* logical channel numbers */
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#define SDPCM_CONTROL_CHANNEL 0 /* Control channel Id */
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#define SDPCM_EVENT_CHANNEL 1 /* Asyc Event Indication Channel Id */
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#define SDPCM_DATA_CHANNEL 2 /* Data Xmit/Recv Channel Id */
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#define SDPCM_GLOM_CHANNEL 3 /* For coalesced packets */
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#define SDPCM_TEST_CHANNEL 15 /* Reserved for test/debug packets */
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#define SDPCM_SEQUENCE_WRAP 256 /* wrap-around val for 8bit frame seq */
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#define SDPCM_GLOMDESC(p) (((u8 *)p)[1] & 0x80)
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/* For TEST_CHANNEL packets, define another 4-byte header */
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#define SDPCM_TEST_HDRLEN 4 /*
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* Generally: Cmd(1), Ext(1), Len(2);
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* Semantics of Ext byte depend on
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* command. Len is current or requested
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* frame length, not including test
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* header; sent little-endian.
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*/
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#define SDPCM_TEST_DISCARD 0x01 /* Receiver discards. Ext:pattern id. */
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#define SDPCM_TEST_ECHOREQ 0x02 /* Echo request. Ext:pattern id. */
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#define SDPCM_TEST_ECHORSP 0x03 /* Echo response. Ext:pattern id. */
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#define SDPCM_TEST_BURST 0x04 /*
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* Receiver to send a burst.
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* Ext is a frame count
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*/
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#define SDPCM_TEST_SEND 0x05 /*
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* Receiver sets send mode.
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* Ext is boolean on/off
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*/
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/* Handy macro for filling in datagen packets with a pattern */
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#define SDPCM_TEST_FILL(byteno, id) ((u8)(id + byteno))
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/*
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* Shared structure between dongle and the host.
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* The structure contains pointers to trap or assert information.
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*/
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#define SDPCM_SHARED_VERSION 0x0002
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#define SDPCM_SHARED_VERSION_MASK 0x00FF
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#define SDPCM_SHARED_ASSERT_BUILT 0x0100
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#define SDPCM_SHARED_ASSERT 0x0200
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#define SDPCM_SHARED_TRAP 0x0400
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/* Space for header read, limit for data packets */
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#ifndef MAX_HDR_READ
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#define MAX_HDR_READ 32
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@ -289,6 +396,18 @@ typedef struct dhd_console {
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} dhd_console_t;
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#endif /* DHD_DEBUG */
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struct sdpcm_shared {
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u32 flags;
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u32 trap_addr;
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u32 assert_exp_addr;
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u32 assert_file_addr;
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u32 assert_line;
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u32 console_addr; /* Address of rte_cons_t */
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u32 msgtrace_addr;
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u8 tag[32];
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};
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/* misc chip info needed by some of the routines */
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struct chip_info {
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u32 chip;
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@ -1876,7 +1995,7 @@ xfer_done:
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}
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#ifdef DHD_DEBUG
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static int dhdsdio_readshared(dhd_bus_t *bus, sdpcm_shared_t *sh)
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static int dhdsdio_readshared(dhd_bus_t *bus, struct sdpcm_shared *sh)
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{
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u32 addr;
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int rv;
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@ -1903,7 +2022,7 @@ static int dhdsdio_readshared(dhd_bus_t *bus, sdpcm_shared_t *sh)
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/* Read rte_shared structure */
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rv = dhdsdio_membytes(bus, false, addr, (u8 *) sh,
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sizeof(sdpcm_shared_t));
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sizeof(struct sdpcm_shared));
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if (rv < 0)
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return rv;
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@ -1935,7 +2054,7 @@ static int dhdsdio_checkdied(dhd_bus_t *bus, u8 *data, uint size)
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uint maxstrlen = 256;
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char *str = NULL;
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trap_t tr;
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sdpcm_shared_t sdpcm_shared;
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struct sdpcm_shared sdpcm_shared;
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struct bcmstrbuf strbuf;
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DHD_TRACE(("%s: Enter\n", __func__));
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