Merge remote-tracking branch 'jwb/next' into next
Josh writes: << A few patches from Suzie for 47x kexec/kdump support, and some MSI patches from Mai La. >>
This commit is contained in:
Benjamin Herrenschmidt
commit
b48d441a8a
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@ -353,7 +353,7 @@ config ARCH_ENABLE_MEMORY_HOTREMOVE
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config KEXEC
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bool "kexec system call (EXPERIMENTAL)"
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depends on (PPC_BOOK3S || FSL_BOOKE || (44x && !SMP && !PPC_47x)) && EXPERIMENTAL
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depends on (PPC_BOOK3S || FSL_BOOKE || (44x && !SMP)) && EXPERIMENTAL
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help
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kexec is a system call that implements the ability to shutdown your
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current kernel, and to start another kernel. It is like a reboot
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@ -370,7 +370,7 @@ config KEXEC
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config CRASH_DUMP
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bool "Build a kdump crash kernel"
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depends on PPC64 || 6xx || FSL_BOOKE || (44x && !SMP && !PPC_47x)
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depends on PPC64 || 6xx || FSL_BOOKE || (44x && !SMP)
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select RELOCATABLE if PPC64 || 44x
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select DYNAMIC_MEMSTART if FSL_BOOKE
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help
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@ -373,5 +373,30 @@
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0x0 0x0 0x0 0x3 &UIC3 0xe 0x4 /* swizzled int C */
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0x0 0x0 0x0 0x4 &UIC3 0xf 0x4 /* swizzled int D */>;
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};
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MSI: ppc4xx-msi@C10000000 {
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compatible = "amcc,ppc4xx-msi", "ppc4xx-msi";
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reg = < 0xC 0x10000000 0x100
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0xC 0x10000000 0x100>;
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sdr-base = <0x36C>;
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msi-data = <0x00004440>;
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msi-mask = <0x0000ffe0>;
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interrupts =<0 1 2 3 4 5 6 7>;
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interrupt-parent = <&MSI>;
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#interrupt-cells = <1>;
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#address-cells = <0>;
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#size-cells = <0>;
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msi-available-ranges = <0x0 0x100>;
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interrupt-map = <
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0 &UIC3 0x18 1
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1 &UIC3 0x19 1
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2 &UIC3 0x1A 1
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3 &UIC3 0x1B 1
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4 &UIC3 0x1C 1
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5 &UIC3 0x1D 1
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6 &UIC3 0x1E 1
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7 &UIC3 0x1F 1
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>;
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};
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};
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};
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@ -738,8 +738,23 @@ relocate_new_kernel:
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mr r5, r31
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li r0, 0
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#elif defined(CONFIG_44x) && !defined(CONFIG_PPC_47x)
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#elif defined(CONFIG_44x)
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/* Save our parameters */
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mr r29, r3
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mr r30, r4
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mr r31, r5
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#ifdef CONFIG_PPC_47x
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/* Check for 47x cores */
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mfspr r3,SPRN_PVR
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srwi r3,r3,16
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cmplwi cr0,r3,PVR_476@h
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beq setup_map_47x
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cmplwi cr0,r3,PVR_476_ISS@h
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beq setup_map_47x
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#endif /* CONFIG_PPC_47x */
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/*
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* Code for setting up 1:1 mapping for PPC440x for KEXEC
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*
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@ -753,16 +768,15 @@ relocate_new_kernel:
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* 5) Invalidate the tmp mapping.
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*
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* - Based on the kexec support code for FSL BookE
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* - Doesn't support 47x yet.
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*
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*/
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/* Save our parameters */
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mr r29, r3
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mr r30, r4
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mr r31, r5
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/* Load our MSR_IS and TID to MMUCR for TLB search */
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mfspr r3,SPRN_PID
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/*
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* Load the PID with kernel PID (0).
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* Also load our MSR_IS and TID to MMUCR for TLB search.
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*/
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li r3, 0
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mtspr SPRN_PID, r3
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mfmsr r4
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andi. r4,r4,MSR_IS@l
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beq wmmucr
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@ -900,6 +914,179 @@ next_tlb:
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li r3, 0
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tlbwe r3, r24, PPC44x_TLB_PAGEID
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sync
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b ppc44x_map_done
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#ifdef CONFIG_PPC_47x
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/* 1:1 mapping for 47x */
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setup_map_47x:
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/*
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* Load the kernel pid (0) to PID and also to MMUCR[TID].
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* Also set the MSR IS->MMUCR STS
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*/
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li r3, 0
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mtspr SPRN_PID, r3 /* Set PID */
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mfmsr r4 /* Get MSR */
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andi. r4, r4, MSR_IS@l /* TS=1? */
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beq 1f /* If not, leave STS=0 */
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oris r3, r3, PPC47x_MMUCR_STS@h /* Set STS=1 */
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1: mtspr SPRN_MMUCR, r3 /* Put MMUCR */
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sync
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/* Find the entry we are running from */
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bl 2f
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2: mflr r23
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tlbsx r23, 0, r23
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tlbre r24, r23, 0 /* TLB Word 0 */
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tlbre r25, r23, 1 /* TLB Word 1 */
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tlbre r26, r23, 2 /* TLB Word 2 */
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/*
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* Invalidates all the tlb entries by writing to 256 RPNs(r4)
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* of 4k page size in all 4 ways (0-3 in r3).
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* This would invalidate the entire UTLB including the one we are
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* running from. However the shadow TLB entries would help us
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* to continue the execution, until we flush them (rfi/isync).
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*/
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addis r3, 0, 0x8000 /* specify the way */
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addi r4, 0, 0 /* TLB Word0 = (EPN=0, VALID = 0) */
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addi r5, 0, 0
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b clear_utlb_entry
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/* Align the loop to speed things up. from head_44x.S */
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.align 6
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clear_utlb_entry:
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tlbwe r4, r3, 0
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tlbwe r5, r3, 1
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tlbwe r5, r3, 2
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addis r3, r3, 0x2000 /* Increment the way */
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cmpwi r3, 0
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bne clear_utlb_entry
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addis r3, 0, 0x8000
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addis r4, r4, 0x100 /* Increment the EPN */
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cmpwi r4, 0
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bne clear_utlb_entry
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/* Create the entries in the other address space */
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mfmsr r5
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rlwinm r7, r5, 27, 31, 31 /* Get the TS (Bit 26) from MSR */
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xori r7, r7, 1 /* r7 = !TS */
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insrwi r24, r7, 1, 21 /* Change the TS in the saved TLB word 0 */
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/*
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* write out the TLB entries for the tmp mapping
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* Use way '0' so that we could easily invalidate it later.
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*/
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lis r3, 0x8000 /* Way '0' */
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tlbwe r24, r3, 0
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tlbwe r25, r3, 1
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tlbwe r26, r3, 2
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/* Update the msr to the new TS */
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insrwi r5, r7, 1, 26
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bl 1f
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1: mflr r6
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addi r6, r6, (2f-1b)
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mtspr SPRN_SRR0, r6
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mtspr SPRN_SRR1, r5
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rfi
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/*
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* Now we are in the tmp address space.
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* Create a 1:1 mapping for 0-2GiB in the original TS.
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*/
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2:
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li r3, 0
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li r4, 0 /* TLB Word 0 */
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li r5, 0 /* TLB Word 1 */
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li r6, 0
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ori r6, r6, PPC47x_TLB2_S_RWX /* TLB word 2 */
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li r8, 0 /* PageIndex */
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xori r7, r7, 1 /* revert back to original TS */
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write_utlb:
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rotlwi r5, r8, 28 /* RPN = PageIndex * 256M */
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/* ERPN = 0 as we don't use memory above 2G */
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mr r4, r5 /* EPN = RPN */
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ori r4, r4, (PPC47x_TLB0_VALID | PPC47x_TLB0_256M)
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insrwi r4, r7, 1, 21 /* Insert the TS to Word 0 */
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tlbwe r4, r3, 0 /* Write out the entries */
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tlbwe r5, r3, 1
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tlbwe r6, r3, 2
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addi r8, r8, 1
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cmpwi r8, 8 /* Have we completed ? */
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bne write_utlb
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/* make sure we complete the TLB write up */
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isync
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/*
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* Prepare to jump to the 1:1 mapping.
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* 1) Extract page size of the tmp mapping
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* DSIZ = TLB_Word0[22:27]
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* 2) Calculate the physical address of the address
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* to jump to.
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*/
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rlwinm r10, r24, 0, 22, 27
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cmpwi r10, PPC47x_TLB0_4K
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bne 0f
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li r10, 0x1000 /* r10 = 4k */
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bl 1f
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0:
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/* Defaults to 256M */
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lis r10, 0x1000
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bl 1f
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1: mflr r4
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addi r4, r4, (2f-1b) /* virtual address of 2f */
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subi r11, r10, 1 /* offsetmask = Pagesize - 1 */
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not r10, r11 /* Pagemask = ~(offsetmask) */
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and r5, r25, r10 /* Physical page */
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and r6, r4, r11 /* offset within the current page */
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or r5, r5, r6 /* Physical address for 2f */
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/* Switch the TS in MSR to the original one */
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mfmsr r8
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insrwi r8, r7, 1, 26
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mtspr SPRN_SRR1, r8
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mtspr SPRN_SRR0, r5
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rfi
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2:
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/* Invalidate the tmp mapping */
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lis r3, 0x8000 /* Way '0' */
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clrrwi r24, r24, 12 /* Clear the valid bit */
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tlbwe r24, r3, 0
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tlbwe r25, r3, 1
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tlbwe r26, r3, 2
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/* Make sure we complete the TLB write and flush the shadow TLB */
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isync
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#endif
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ppc44x_map_done:
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/* Restore the parameters */
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mr r3, r29
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@ -23,6 +23,8 @@ config BLUESTONE
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default n
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select PPC44x_SIMPLE
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select APM821xx
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select PCI_MSI
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select PPC4xx_MSI
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select PPC4xx_PCI_EXPRESS
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select IBM_EMAC_RGMII
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help
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@ -28,10 +28,11 @@
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#include <linux/of_platform.h>
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#include <linux/interrupt.h>
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#include <linux/export.h>
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#include <linux/kernel.h>
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#include <asm/prom.h>
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#include <asm/hw_irq.h>
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#include <asm/ppc-pci.h>
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#include <boot/dcr.h>
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#include <asm/dcr.h>
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#include <asm/dcr-regs.h>
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#include <asm/msi_bitmap.h>
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@ -43,13 +44,14 @@
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#define PEIH_FLUSH0 0x30
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#define PEIH_FLUSH1 0x38
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#define PEIH_CNTRST 0x48
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#define NR_MSI_IRQS 4
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static int msi_irqs;
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struct ppc4xx_msi {
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u32 msi_addr_lo;
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u32 msi_addr_hi;
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void __iomem *msi_regs;
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int msi_virqs[NR_MSI_IRQS];
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int *msi_virqs;
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struct msi_bitmap bitmap;
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struct device_node *msi_dev;
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};
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@ -61,7 +63,7 @@ static int ppc4xx_msi_init_allocator(struct platform_device *dev,
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{
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int err;
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err = msi_bitmap_alloc(&msi_data->bitmap, NR_MSI_IRQS,
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err = msi_bitmap_alloc(&msi_data->bitmap, msi_irqs,
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dev->dev.of_node);
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if (err)
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return err;
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@ -83,6 +85,11 @@ static int ppc4xx_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
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struct msi_desc *entry;
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struct ppc4xx_msi *msi_data = &ppc4xx_msi;
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msi_data->msi_virqs = kmalloc((msi_irqs) * sizeof(int),
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GFP_KERNEL);
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if (!msi_data->msi_virqs)
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return -ENOMEM;
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list_for_each_entry(entry, &dev->msi_list, list) {
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int_no = msi_bitmap_alloc_hwirqs(&msi_data->bitmap, 1);
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if (int_no >= 0)
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@ -150,12 +157,11 @@ static int ppc4xx_setup_pcieh_hw(struct platform_device *dev,
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if (!sdr_addr)
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return -1;
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SDR0_WRITE(sdr_addr, (u64)res.start >> 32); /*HIGH addr */
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SDR0_WRITE(sdr_addr + 1, res.start & 0xFFFFFFFF); /* Low addr */
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mtdcri(SDR0, *sdr_addr, upper_32_bits(res.start)); /*HIGH addr */
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mtdcri(SDR0, *sdr_addr + 1, lower_32_bits(res.start)); /* Low addr */
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msi->msi_dev = of_find_node_by_name(NULL, "ppc4xx-msi");
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if (msi->msi_dev)
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if (!msi->msi_dev)
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return -ENODEV;
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msi->msi_regs = of_iomap(msi->msi_dev, 0);
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@ -167,9 +173,12 @@ static int ppc4xx_setup_pcieh_hw(struct platform_device *dev,
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(u32) (msi->msi_regs + PEIH_TERMADH), (u32) (msi->msi_regs));
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msi_virt = dma_alloc_coherent(&dev->dev, 64, &msi_phys, GFP_KERNEL);
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msi->msi_addr_hi = 0x0;
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msi->msi_addr_lo = (u32) msi_phys;
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dev_dbg(&dev->dev, "PCIE-MSI: msi address 0x%x\n", msi->msi_addr_lo);
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if (!msi_virt)
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return -ENOMEM;
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msi->msi_addr_hi = upper_32_bits(msi_phys);
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msi->msi_addr_lo = lower_32_bits(msi_phys & 0xffffffff);
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dev_dbg(&dev->dev, "PCIE-MSI: msi address high 0x%x, low 0x%x\n",
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msi->msi_addr_hi, msi->msi_addr_lo);
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/* Progam the Interrupt handler Termination addr registers */
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out_be32(msi->msi_regs + PEIH_TERMADH, msi->msi_addr_hi);
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@ -185,6 +194,8 @@ static int ppc4xx_setup_pcieh_hw(struct platform_device *dev,
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out_be32(msi->msi_regs + PEIH_MSIED, *msi_data);
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out_be32(msi->msi_regs + PEIH_MSIMK, *msi_mask);
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dma_free_coherent(&dev->dev, 64, msi_virt, msi_phys);
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return 0;
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}
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@ -194,7 +205,7 @@ static int ppc4xx_of_msi_remove(struct platform_device *dev)
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int i;
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int virq;
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for (i = 0; i < NR_MSI_IRQS; i++) {
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for (i = 0; i < msi_irqs; i++) {
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virq = msi->msi_virqs[i];
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if (virq != NO_IRQ)
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irq_dispose_mapping(virq);
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@ -215,8 +226,6 @@ static int __devinit ppc4xx_msi_probe(struct platform_device *dev)
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struct resource res;
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int err = 0;
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msi = &ppc4xx_msi;/*keep the msi data for further use*/
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dev_dbg(&dev->dev, "PCIE-MSI: Setting up MSI support...\n");
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msi = kzalloc(sizeof(struct ppc4xx_msi), GFP_KERNEL);
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@ -234,6 +243,10 @@ static int __devinit ppc4xx_msi_probe(struct platform_device *dev)
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goto error_out;
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}
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msi_irqs = of_irq_count(dev->dev.of_node);
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if (!msi_irqs)
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return -ENODEV;
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if (ppc4xx_setup_pcieh_hw(dev, res, msi))
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goto error_out;
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@ -242,6 +255,7 @@ static int __devinit ppc4xx_msi_probe(struct platform_device *dev)
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dev_err(&dev->dev, "Error allocating MSI bitmap\n");
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goto error_out;
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}
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ppc4xx_msi = *msi;
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ppc_md.setup_msi_irqs = ppc4xx_setup_msi_irqs;
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ppc_md.teardown_msi_irqs = ppc4xx_teardown_msi_irqs;
|
||||
|
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|
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