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Merge branch 'qed-qedr-infrastructure' 

Yuval Mintz says:

====================
qed*: Add qedr infrastructure support

In the last couple of weeks we've been sending RFCs for the qedr
driver - the RoCE driver for QLogic FastLinQ 4xxxx line of adapters.
Latest RFC can be found at [1].

At Doug's advice [2], we've decided to split the series into two:
 - first part contains the qed backbone that's necessary for all the
configurations relating to the qedr driver, as well as the qede
infrastructure that is used for communication between the qedr and qede.
 - Second part consists of the actual qedr driver and introduces almost
no changes to qed/qede.

This is the first of said two parts. The second half would be sent
later this week.

The only 'oddity' in the devision are the Kconfig options -
As this series introduces both LL2 and QEDR-based logic in qed/qede,
I wanted to add the CONFIG_INFINIBAND_QEDR option here [with default n].
Otherwise, a lot of the code introduced would be dead-code [won't even
be compiled] until qedr is accepted.
As a result I've placed the config option in an odd place - under
qlogic's Kconfig. The second series would then remove that option
and add it in its correct place under the infiniband Kconfig.
[I'm fine with pushing it there to begin with, but I didn't want to
'contaminate' non-qlogic configuration files with half-baked options].

Dave - I don't think you were E-mailed with Doug's suggestion.
I think the notion was to have the two halves accepted side-by-side,
but actually the first has no dependency issues, so it's also
possible to simply take this first to net-next, and push the qedr
into rdma once it's merged. But it's basically up to you and Doug;
We'd align with whatever suits you best.
====================

Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller 2016-10-03 23:22:52 -04:00
parent b9118b7221 abd49676c7
commit b462d22bf3
28 changed files with 6944 additions and 22 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
drivers/net/ethernet/qlogic/Kconfig
View File

@ -88,6 +88,9 @@ config QED
---help---
This enables the support for ...
config QED_LL2
bool
config QED_SRIOV
bool "QLogic QED 25/40/100Gb SR-IOV support"
depends on QED && PCI_IOV
@ -104,4 +107,15 @@ config QEDE
---help---
This enables the support for ...
config INFINIBAND_QEDR
tristate "QLogic qede RoCE sources [debug]"
depends on QEDE && 64BIT
select QED_LL2
default n
---help---
This provides a temporary node that allows the compilation
and logical testing of the InfiniBand over Ethernet support
for QLogic QED. This would be replaced by the 'real' option
once the QEDR driver is added [+relocated].
endif # NET_VENDOR_QLOGIC

2
drivers/net/ethernet/qlogic/qed/Makefile
View File

@ -4,3 +4,5 @@ qed-y := qed_cxt.o qed_dev.o qed_hw.o qed_init_fw_funcs.o qed_init_ops.o \
qed_int.o qed_main.o qed_mcp.o qed_sp_commands.o qed_spq.o qed_l2.o \
qed_selftest.o qed_dcbx.o qed_debug.o
qed-$(CONFIG_QED_SRIOV) += qed_sriov.o qed_vf.o
qed-$(CONFIG_QED_LL2) += qed_ll2.o
qed-$(CONFIG_INFINIBAND_QEDR) += qed_roce.o

43
drivers/net/ethernet/qlogic/qed/qed.h
View File

@ -35,6 +35,9 @@ extern const struct qed_common_ops qed_common_ops_pass;
#define QED_WFQ_UNIT 100
#define QED_WID_SIZE (1024)
#define QED_PF_DEMS_SIZE (4)
/* cau states */
enum qed_coalescing_mode {
QED_COAL_MODE_DISABLE,
@ -48,6 +51,14 @@ enum qed_mcp_protocol_type;
/* helpers */
static inline u32 qed_db_addr(u32 cid, u32 DEMS)
{
u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
(cid * QED_PF_DEMS_SIZE);
return db_addr;
}
static inline u32 qed_db_addr_vf(u32 cid, u32 DEMS)
{
u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
FIELD_VALUE(DB_LEGACY_ADDR_ICID, cid);
@ -72,6 +83,7 @@ struct qed_sb_info;
struct qed_sb_attn_info;
struct qed_cxt_mngr;
struct qed_sb_sp_info;
struct qed_ll2_info;
struct qed_mcp_info;
struct qed_rt_data {
@ -151,13 +163,17 @@ enum QED_RESOURCES {
QED_RL,
QED_MAC,
QED_VLAN,
QED_RDMA_CNQ_RAM,
QED_ILT,
QED_LL2_QUEUE,
QED_RDMA_STATS_QUEUE,
QED_MAX_RESC,
};
enum QED_FEATURE {
QED_PF_L2_QUE,
QED_VF,
QED_RDMA_CNQ,
QED_MAX_FEATURES,
};
@ -360,6 +376,9 @@ struct qed_hwfn {
struct qed_sb_attn_info *p_sb_attn;
/* Protocol related */
bool using_ll2;
struct qed_ll2_info *p_ll2_info;
struct qed_rdma_info *p_rdma_info;
struct qed_pf_params pf_params;
bool b_rdma_enabled_in_prs;
@ -398,6 +417,17 @@ struct qed_hwfn {
struct dbg_tools_data dbg_info;
/* PWM region specific data */
u32 dpi_size;
u32 dpi_count;
/* This is used to calculate the doorbell address */
u32 dpi_start_offset;
/* If one of the following is set then EDPM shouldn't be used */
u8 dcbx_no_edpm;
u8 db_bar_no_edpm;
struct qed_simd_fp_handler simd_proto_handler[64];
#ifdef CONFIG_QED_SRIOV
@ -407,6 +437,7 @@ struct qed_hwfn {
#endif
struct z_stream_s *stream;
struct qed_roce_ll2_info *ll2;
};
struct pci_params {
@ -431,6 +462,8 @@ struct qed_int_params {
bool fp_initialized;
u8 fp_msix_base;
u8 fp_msix_cnt;
u8 rdma_msix_base;
u8 rdma_msix_cnt;
};
struct qed_dbg_feature {
@ -537,7 +570,6 @@ struct qed_dev {
bool b_is_vf;
u32 drv_type;
struct qed_eth_stats *reset_stats;
struct qed_fw_data *fw_data;
@ -564,7 +596,16 @@ struct qed_dev {
struct qed_dbg_params dbg_params;
#ifdef CONFIG_QED_LL2
struct qed_cb_ll2_info *ll2;
u8 ll2_mac_address[ETH_ALEN];
#endif
const struct firmware *firmware;
u32 rdma_max_sge;
u32 rdma_max_inline;
u32 rdma_max_srq_sge;
};
#define NUM_OF_VFS(dev) MAX_NUM_VFS_BB

8
drivers/net/ethernet/qlogic/qed/qed_cxt.c
View File

@ -48,7 +48,13 @@
#define TM_ELEM_SIZE 4
/* ILT constants */
#if IS_ENABLED(CONFIG_INFINIBAND_QEDR)
/* For RoCE we configure to 64K to cover for RoCE max tasks 256K purpose. */
#define ILT_DEFAULT_HW_P_SIZE 4
#else
#define ILT_DEFAULT_HW_P_SIZE 3
#endif
#define ILT_PAGE_IN_BYTES(hw_p_size) (1U << ((hw_p_size) + 12))
#define ILT_CFG_REG(cli, reg) PSWRQ2_REG_ ## cli ## _ ## reg ## _RT_OFFSET
@ -1839,6 +1845,8 @@ int qed_cxt_set_pf_params(struct qed_hwfn *p_hwfn)
/* Set the number of required CORE connections */
u32 core_cids = 1; /* SPQ */
if (p_hwfn->using_ll2)
core_cids += 4;
qed_cxt_set_proto_cid_count(p_hwfn, PROTOCOLID_CORE, core_cids, 0);
switch (p_hwfn->hw_info.personality) {

7
drivers/net/ethernet/qlogic/qed/qed_cxt.h
View File

@ -170,6 +170,13 @@ int qed_qm_reconf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt);
*/
void qed_cxt_release_cid(struct qed_hwfn *p_hwfn,
u32 cid);
int qed_cxt_dynamic_ilt_alloc(struct qed_hwfn *p_hwfn,
enum qed_cxt_elem_type elem_type, u32 iid);
u32 qed_cxt_get_proto_tid_count(struct qed_hwfn *p_hwfn,
enum protocol_type type);
u32 qed_cxt_get_proto_cid_start(struct qed_hwfn *p_hwfn,
enum protocol_type type);
int qed_cxt_free_proto_ilt(struct qed_hwfn *p_hwfn, enum protocol_type proto);
#define QED_CTX_WORKING_MEM 0
#define QED_CTX_FL_MEM 1

274
drivers/net/ethernet/qlogic/qed/qed_dev.c
View File

@ -29,14 +29,19 @@
#include "qed_hw.h"
#include "qed_init_ops.h"
#include "qed_int.h"
#include "qed_ll2.h"
#include "qed_mcp.h"
#include "qed_reg_addr.h"
#include "qed_sp.h"
#include "qed_sriov.h"
#include "qed_vf.h"
#include "qed_roce.h"
static DEFINE_SPINLOCK(qm_lock);
#define QED_MIN_DPIS (4)
#define QED_MIN_PWM_REGION (QED_WID_SIZE * QED_MIN_DPIS)
/* API common to all protocols */
enum BAR_ID {
BAR_ID_0, /* used for GRC */
@ -147,6 +152,9 @@ void qed_resc_free(struct qed_dev *cdev)
qed_eq_free(p_hwfn, p_hwfn->p_eq);
qed_consq_free(p_hwfn, p_hwfn->p_consq);
qed_int_free(p_hwfn);
#ifdef CONFIG_QED_LL2
qed_ll2_free(p_hwfn, p_hwfn->p_ll2_info);
#endif
qed_iov_free(p_hwfn);
qed_dmae_info_free(p_hwfn);
qed_dcbx_info_free(p_hwfn, p_hwfn->p_dcbx_info);
@ -403,6 +411,9 @@ int qed_qm_reconf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
int qed_resc_alloc(struct qed_dev *cdev)
{
#ifdef CONFIG_QED_LL2
struct qed_ll2_info *p_ll2_info;
#endif
struct qed_consq *p_consq;
struct qed_eq *p_eq;
int i, rc = 0;
@ -513,6 +524,15 @@ int qed_resc_alloc(struct qed_dev *cdev)
goto alloc_no_mem;
p_hwfn->p_consq = p_consq;
#ifdef CONFIG_QED_LL2
if (p_hwfn->using_ll2) {
p_ll2_info = qed_ll2_alloc(p_hwfn);
if (!p_ll2_info)
goto alloc_no_mem;
p_hwfn->p_ll2_info = p_ll2_info;
}
#endif
/* DMA info initialization */
rc = qed_dmae_info_alloc(p_hwfn);
if (rc)
@ -561,6 +581,10 @@ void qed_resc_setup(struct qed_dev *cdev)
qed_int_setup(p_hwfn, p_hwfn->p_main_ptt);
qed_iov_setup(p_hwfn, p_hwfn->p_main_ptt);
#ifdef CONFIG_QED_LL2
if (p_hwfn->using_ll2)
qed_ll2_setup(p_hwfn, p_hwfn->p_ll2_info);
#endif
}
}
@ -767,6 +791,136 @@ static int qed_hw_init_common(struct qed_hwfn *p_hwfn,
return rc;
}
static int
qed_hw_init_dpi_size(struct qed_hwfn *p_hwfn,
struct qed_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus)
{
u32 dpi_page_size_1, dpi_page_size_2, dpi_page_size;
u32 dpi_bit_shift, dpi_count;
u32 min_dpis;
/* Calculate DPI size */
dpi_page_size_1 = QED_WID_SIZE * n_cpus;
dpi_page_size_2 = max_t(u32, QED_WID_SIZE, PAGE_SIZE);
dpi_page_size = max_t(u32, dpi_page_size_1, dpi_page_size_2);
dpi_page_size = roundup_pow_of_two(dpi_page_size);
dpi_bit_shift = ilog2(dpi_page_size / 4096);
dpi_count = pwm_region_size / dpi_page_size;
min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis;
min_dpis = max_t(u32, QED_MIN_DPIS, min_dpis);
p_hwfn->dpi_size = dpi_page_size;
p_hwfn->dpi_count = dpi_count;
qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift);
if (dpi_count < min_dpis)
return -EINVAL;
return 0;
}
enum QED_ROCE_EDPM_MODE {
QED_ROCE_EDPM_MODE_ENABLE = 0,
QED_ROCE_EDPM_MODE_FORCE_ON = 1,
QED_ROCE_EDPM_MODE_DISABLE = 2,
};
static int
qed_hw_init_pf_doorbell_bar(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
{
u32 pwm_regsize, norm_regsize;
u32 non_pwm_conn, min_addr_reg1;
u32 db_bar_size, n_cpus;
u32 roce_edpm_mode;
u32 pf_dems_shift;
int rc = 0;
u8 cond;
db_bar_size = qed_hw_bar_size(p_hwfn, BAR_ID_1);
if (p_hwfn->cdev->num_hwfns > 1)
db_bar_size /= 2;
/* Calculate doorbell regions */
non_pwm_conn = qed_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
NULL) +
qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH,
NULL);
norm_regsize = roundup(QED_PF_DEMS_SIZE * non_pwm_conn, 4096);
min_addr_reg1 = norm_regsize / 4096;
pwm_regsize = db_bar_size - norm_regsize;
/* Check that the normal and PWM sizes are valid */
if (db_bar_size < norm_regsize) {
DP_ERR(p_hwfn->cdev,
"Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n",
db_bar_size, norm_regsize);
return -EINVAL;
}
if (pwm_regsize < QED_MIN_PWM_REGION) {
DP_ERR(p_hwfn->cdev,
"PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n",
pwm_regsize,
QED_MIN_PWM_REGION, db_bar_size, norm_regsize);
return -EINVAL;
}
/* Calculate number of DPIs */
roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode;
if ((roce_edpm_mode == QED_ROCE_EDPM_MODE_ENABLE) ||
((roce_edpm_mode == QED_ROCE_EDPM_MODE_FORCE_ON))) {
/* Either EDPM is mandatory, or we are attempting to allocate a
* WID per CPU.
*/
n_cpus = num_active_cpus();
rc = qed_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
}
cond = (rc && (roce_edpm_mode == QED_ROCE_EDPM_MODE_ENABLE)) ||
(roce_edpm_mode == QED_ROCE_EDPM_MODE_DISABLE);
if (cond || p_hwfn->dcbx_no_edpm) {
/* Either EDPM is disabled from user configuration, or it is
* disabled via DCBx, or it is not mandatory and we failed to
* allocated a WID per CPU.
*/
n_cpus = 1;
rc = qed_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
if (cond)
qed_rdma_dpm_bar(p_hwfn, p_ptt);
}
DP_INFO(p_hwfn,
"doorbell bar: normal_region_size=%d, pwm_region_size=%d, dpi_size=%d, dpi_count=%d, roce_edpm=%s\n",
norm_regsize,
pwm_regsize,
p_hwfn->dpi_size,
p_hwfn->dpi_count,
((p_hwfn->dcbx_no_edpm) || (p_hwfn->db_bar_no_edpm)) ?
"disabled" : "enabled");
if (rc) {
DP_ERR(p_hwfn,
"Failed to allocate enough DPIs. Allocated %d but the current minimum is %d.\n",
p_hwfn->dpi_count,
p_hwfn->pf_params.rdma_pf_params.min_dpis);
return -EINVAL;
}
p_hwfn->dpi_start_offset = norm_regsize;
/* DEMS size is configured log2 of DWORDs, hence the division by 4 */
pf_dems_shift = ilog2(QED_PF_DEMS_SIZE / 4);
qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift);
qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1);
return 0;
}
static int qed_hw_init_port(struct qed_hwfn *p_hwfn,
struct qed_ptt *p_ptt, int hw_mode)
{
@ -840,6 +994,10 @@ static int qed_hw_init_pf(struct qed_hwfn *p_hwfn,
/* Pure runtime initializations - directly to the HW */
qed_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
rc = qed_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
if (rc)
return rc;
if (b_hw_start) {
/* enable interrupts */
qed_int_igu_enable(p_hwfn, p_ptt, int_mode);
@ -1264,6 +1422,19 @@ static void qed_hw_set_feat(struct qed_hwfn *p_hwfn)
u32 *feat_num = p_hwfn->hw_info.feat_num;
int num_features = 1;
#if IS_ENABLED(CONFIG_INFINIBAND_QEDR)
/* Roce CNQ each requires: 1 status block + 1 CNQ. We divide the
* status blocks equally between L2 / RoCE but with consideration as
* to how many l2 queues / cnqs we have
*/
if (p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE) {
num_features++;
feat_num[QED_RDMA_CNQ] =
min_t(u32, RESC_NUM(p_hwfn, QED_SB) / num_features,
RESC_NUM(p_hwfn, QED_RDMA_CNQ_RAM));
}
#endif
feat_num[QED_PF_L2_QUE] = min_t(u32, RESC_NUM(p_hwfn, QED_SB) /
num_features,
RESC_NUM(p_hwfn, QED_L2_QUEUE));
@ -1304,6 +1475,10 @@ static int qed_hw_get_resc(struct qed_hwfn *p_hwfn)
resc_num[QED_VLAN] = (ETH_NUM_VLAN_FILTERS - 1 /*For vlan0*/) /
num_funcs;
resc_num[QED_ILT] = PXP_NUM_ILT_RECORDS_BB / num_funcs;
resc_num[QED_LL2_QUEUE] = MAX_NUM_LL2_RX_QUEUES / num_funcs;
resc_num[QED_RDMA_CNQ_RAM] = NUM_OF_CMDQS_CQS / num_funcs;
resc_num[QED_RDMA_STATS_QUEUE] = RDMA_NUM_STATISTIC_COUNTERS_BB /
num_funcs;
for (i = 0; i < QED_MAX_RESC; i++)
resc_start[i] = resc_num[i] * enabled_func_idx;
@ -1327,7 +1502,8 @@ static int qed_hw_get_resc(struct qed_hwfn *p_hwfn)
"RL = %d start = %d\n"
"MAC = %d start = %d\n"
"VLAN = %d start = %d\n"
"ILT = %d start = %d\n",
"ILT = %d start = %d\n"
"LL2_QUEUE = %d start = %d\n",
p_hwfn->hw_info.resc_num[QED_SB],
p_hwfn->hw_info.resc_start[QED_SB],
p_hwfn->hw_info.resc_num[QED_L2_QUEUE],
@ -1343,7 +1519,9 @@ static int qed_hw_get_resc(struct qed_hwfn *p_hwfn)
p_hwfn->hw_info.resc_num[QED_VLAN],
p_hwfn->hw_info.resc_start[QED_VLAN],
p_hwfn->hw_info.resc_num[QED_ILT],
p_hwfn->hw_info.resc_start[QED_ILT]);
p_hwfn->hw_info.resc_start[QED_ILT],
RESC_NUM(p_hwfn, QED_LL2_QUEUE),
RESC_START(p_hwfn, QED_LL2_QUEUE));
return 0;
}
@ -2133,6 +2311,98 @@ int qed_fw_rss_eng(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id)
return 0;
}
static void qed_llh_mac_to_filter(u32 *p_high, u32 *p_low,
u8 *p_filter)
{
*p_high = p_filter[1] | (p_filter[0] << 8);
*p_low = p_filter[5] | (p_filter[4] << 8) |
(p_filter[3] << 16) | (p_filter[2] << 24);
}
int qed_llh_add_mac_filter(struct qed_hwfn *p_hwfn,
struct qed_ptt *p_ptt, u8 *p_filter)
{
u32 high = 0, low = 0, en;
int i;
if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
return 0;
qed_llh_mac_to_filter(&high, &low, p_filter);
/* Find a free entry and utilize it */
for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
en = qed_rd(p_hwfn, p_ptt,
NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
if (en)
continue;
qed_wr(p_hwfn, p_ptt,
NIG_REG_LLH_FUNC_FILTER_VALUE +
2 * i * sizeof(u32), low);
qed_wr(p_hwfn, p_ptt,
NIG_REG_LLH_FUNC_FILTER_VALUE +
(2 * i + 1) * sizeof(u32), high);
qed_wr(p_hwfn, p_ptt,
NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
qed_wr(p_hwfn, p_ptt,
NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
i * sizeof(u32), 0);
qed_wr(p_hwfn, p_ptt,
NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
break;
}
if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
DP_NOTICE(p_hwfn,
"Failed to find an empty LLH filter to utilize\n");
return -EINVAL;
}
DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
"mac: %pM is added at %d\n",
p_filter, i);
return 0;
}
void qed_llh_remove_mac_filter(struct qed_hwfn *p_hwfn,
struct qed_ptt *p_ptt, u8 *p_filter)
{
u32 high = 0, low = 0;
int i;
if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
return;
qed_llh_mac_to_filter(&high, &low, p_filter);
/* Find the entry and clean it */
for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
if (qed_rd(p_hwfn, p_ptt,
NIG_REG_LLH_FUNC_FILTER_VALUE +
2 * i * sizeof(u32)) != low)
continue;
if (qed_rd(p_hwfn, p_ptt,
NIG_REG_LLH_FUNC_FILTER_VALUE +
(2 * i + 1) * sizeof(u32)) != high)
continue;
qed_wr(p_hwfn, p_ptt,
NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
qed_wr(p_hwfn, p_ptt,
NIG_REG_LLH_FUNC_FILTER_VALUE + 2 * i * sizeof(u32), 0);
qed_wr(p_hwfn, p_ptt,
NIG_REG_LLH_FUNC_FILTER_VALUE +
(2 * i + 1) * sizeof(u32), 0);
DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
"mac: %pM is removed from %d\n",
p_filter, i);
break;
}
if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
DP_NOTICE(p_hwfn, "Tried to remove a non-configured filter\n");
}
static int qed_set_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
u32 hw_addr, void *p_eth_qzone,
size_t eth_qzone_size, u8 timeset)

20
drivers/net/ethernet/qlogic/qed/qed_dev_api.h
View File

@ -309,6 +309,26 @@ int qed_fw_rss_eng(struct qed_hwfn *p_hwfn,
u8 src_id,
u8 *dst_id);
/**
* @brief qed_llh_add_mac_filter - configures a MAC filter in llh
*
* @param p_hwfn
* @param p_ptt
* @param p_filter - MAC to add
*/
int qed_llh_add_mac_filter(struct qed_hwfn *p_hwfn,
struct qed_ptt *p_ptt, u8 *p_filter);
/**
* @brief qed_llh_remove_mac_filter - removes a MAC filter from llh
*
* @param p_hwfn
* @param p_ptt
* @param p_filter - MAC to remove
*/
void qed_llh_remove_mac_filter(struct qed_hwfn *p_hwfn,
struct qed_ptt *p_ptt, u8 *p_filter);
/**
* *@brief Cleanup of previous driver remains prior to load
*

3
drivers/net/ethernet/qlogic/qed/qed_hsi.h
View File

@ -727,6 +727,9 @@ struct core_tx_bd_flags {
#define CORE_TX_BD_FLAGS_L4_PROTOCOL_SHIFT 6
#define CORE_TX_BD_FLAGS_L4_PSEUDO_CSUM_MODE_MASK 0x1
#define CORE_TX_BD_FLAGS_L4_PSEUDO_CSUM_MODE_SHIFT 7
#define CORE_TX_BD_FLAGS_ROCE_FLAV_MASK 0x1
#define CORE_TX_BD_FLAGS_ROCE_FLAV_SHIFT 12
};
struct core_tx_bd {

1792
drivers/net/ethernet/qlogic/qed/qed_ll2.c Normal file
View File

File diff suppressed because it is too large Load Diff

316
drivers/net/ethernet/qlogic/qed/qed_ll2.h Normal file
View File

@ -0,0 +1,316 @@
/* QLogic qed NIC Driver
*
* Copyright (c) 2015 QLogic Corporation
*
* This software is available under the terms of the GNU General Public License
* (GPL) Version 2, available from the file COPYING in the main directory of
* this source tree.
*/
#ifndef _QED_LL2_H
#define _QED_LL2_H
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/mutex.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/qed/qed_chain.h>
#include <linux/qed/qed_ll2_if.h>
#include "qed.h"
#include "qed_hsi.h"
#include "qed_sp.h"
#define QED_MAX_NUM_OF_LL2_CONNECTIONS (4)
enum qed_ll2_roce_flavor_type {
QED_LL2_ROCE,
QED_LL2_RROCE,
MAX_QED_LL2_ROCE_FLAVOR_TYPE
};
enum qed_ll2_conn_type {
QED_LL2_TYPE_RESERVED,
QED_LL2_TYPE_ISCSI,
QED_LL2_TYPE_TEST,
QED_LL2_TYPE_ISCSI_OOO,
QED_LL2_TYPE_RESERVED2,
QED_LL2_TYPE_ROCE,
QED_LL2_TYPE_RESERVED3,
MAX_QED_LL2_RX_CONN_TYPE
};
struct qed_ll2_rx_packet {
struct list_head list_entry;
struct core_rx_bd_with_buff_len *rxq_bd;
dma_addr_t rx_buf_addr;
u16 buf_length;
void *cookie;
u8 placement_offset;
u16 parse_flags;
u16 packet_length;
u16 vlan;
u32 opaque_data[2];
};
struct qed_ll2_tx_packet {
struct list_head list_entry;
u16 bd_used;
u16 vlan;
u16 l4_hdr_offset_w;
u8 bd_flags;
bool notify_fw;
void *cookie;
struct {
struct core_tx_bd *txq_bd;
dma_addr_t tx_frag;
u16 frag_len;
} bds_set[ETH_TX_MAX_BDS_PER_NON_LSO_PACKET];
};
struct qed_ll2_rx_queue {
/* Lock protecting the Rx queue manipulation */
spinlock_t lock;
struct qed_chain rxq_chain;
struct qed_chain rcq_chain;
u8 rx_sb_index;
bool b_cb_registred;
__le16 *p_fw_cons;
struct list_head active_descq;
struct list_head free_descq;
struct list_head posting_descq;
struct qed_ll2_rx_packet *descq_array;
void __iomem *set_prod_addr;
};
struct qed_ll2_tx_queue {
/* Lock protecting the Tx queue manipulation */
spinlock_t lock;
struct qed_chain txq_chain;
u8 tx_sb_index;
bool b_cb_registred;
__le16 *p_fw_cons;
struct list_head active_descq;
struct list_head free_descq;
struct list_head sending_descq;
struct qed_ll2_tx_packet *descq_array;
struct qed_ll2_tx_packet *cur_send_packet;
struct qed_ll2_tx_packet cur_completing_packet;
u16 cur_completing_bd_idx;
void __iomem *doorbell_addr;
u16 bds_idx;
u16 cur_send_frag_num;
u16 cur_completing_frag_num;
bool b_completing_packet;
};
struct qed_ll2_info {
/* Lock protecting the state of LL2 */
struct mutex mutex;
enum qed_ll2_conn_type conn_type;
u32 cid;
u8 my_id;
u8 queue_id;
u8 tx_stats_id;
bool b_active;
u16 mtu;
u8 rx_drop_ttl0_flg;
u8 rx_vlan_removal_en;
u8 tx_tc;
enum core_tx_dest tx_dest;
enum core_error_handle ai_err_packet_too_big;
enum core_error_handle ai_err_no_buf;
u8 tx_stats_en;
struct qed_ll2_rx_queue rx_queue;
struct qed_ll2_tx_queue tx_queue;
u8 gsi_enable;
};
/**
* @brief qed_ll2_acquire_connection - allocate resources,
* starts rx & tx (if relevant) queues pair. Provides
* connecion handler as output parameter.
*
* @param p_hwfn
* @param p_params Contain various configuration properties
* @param rx_num_desc
* @param tx_num_desc
*
* @param p_connection_handle Output container for LL2 connection's handle
*
* @return 0 on success, failure otherwise
*/
int qed_ll2_acquire_connection(struct qed_hwfn *p_hwfn,
struct qed_ll2_info *p_params,
u16 rx_num_desc,
u16 tx_num_desc,
u8 *p_connection_handle);
/**
* @brief qed_ll2_establish_connection - start previously
* allocated LL2 queues pair
*
* @param p_hwfn
* @param p_ptt
* @param connection_handle LL2 connection's handle obtained from
* qed_ll2_require_connection
*
* @return 0 on success, failure otherwise
*/
int qed_ll2_establish_connection(struct qed_hwfn *p_hwfn, u8 connection_handle);
/**
* @brief qed_ll2_post_rx_buffers - submit buffers to LL2 Rx queue.
*
* @param p_hwfn
* @param connection_handle LL2 connection's handle obtained from
* qed_ll2_require_connection
* @param addr rx (physical address) buffers to submit
* @param cookie
* @param notify_fw produce corresponding Rx BD immediately
*
* @return 0 on success, failure otherwise
*/
int qed_ll2_post_rx_buffer(struct qed_hwfn *p_hwfn,
u8 connection_handle,
dma_addr_t addr,
u16 buf_len, void *cookie, u8 notify_fw);
/**
* @brief qed_ll2_prepare_tx_packet - request for start Tx BD
* to prepare Tx packet submission to FW.
*
* @param p_hwfn
* @param connection_handle LL2 connection's handle obtained from
* qed_ll2_require_connection
* @param num_of_bds a number of requested BD equals a number of
* fragments in Tx packet
* @param vlan VLAN to insert to packet (if insertion set)
* @param bd_flags
* @param l4_hdr_offset_w L4 Header Offset from start of packet
* (in words). This is needed if both l4_csum
* and ipv6_ext are set
* @param first_frag
* @param first_frag_len
* @param cookie
*
* @param notify_fw
*
* @return 0 on success, failure otherwise
*/
int qed_ll2_prepare_tx_packet(struct qed_hwfn *p_hwfn,
u8 connection_handle,
u8 num_of_bds,
u16 vlan,
u8 bd_flags,
u16 l4_hdr_offset_w,
enum qed_ll2_roce_flavor_type qed_roce_flavor,
dma_addr_t first_frag,
u16 first_frag_len, void *cookie, u8 notify_fw);
/**
* @brief qed_ll2_release_connection - releases resources
* allocated for LL2 connection
*
* @param p_hwfn
* @param connection_handle LL2 connection's handle obtained from
* qed_ll2_require_connection
*/
void qed_ll2_release_connection(struct qed_hwfn *p_hwfn, u8 connection_handle);
/**
* @brief qed_ll2_set_fragment_of_tx_packet - provides fragments to fill
* Tx BD of BDs requested by
* qed_ll2_prepare_tx_packet
*
* @param p_hwfn
* @param connection_handle LL2 connection's handle
* obtained from
* qed_ll2_require_connection
* @param addr
* @param nbytes
*
* @return 0 on success, failure otherwise
*/
int qed_ll2_set_fragment_of_tx_packet(struct qed_hwfn *p_hwfn,
u8 connection_handle,
dma_addr_t addr, u16 nbytes);
/**
* @brief qed_ll2_terminate_connection - stops Tx/Rx queues
*
*
* @param p_hwfn
* @param connection_handle LL2 connection's handle
* obtained from
* qed_ll2_require_connection
*
* @return 0 on success, failure otherwise
*/
int qed_ll2_terminate_connection(struct qed_hwfn *p_hwfn, u8 connection_handle);
/**
* @brief qed_ll2_get_stats - get LL2 queue's statistics
*
*
* @param p_hwfn
* @param connection_handle LL2 connection's handle obtained from
* qed_ll2_require_connection
* @param p_stats
*
* @return 0 on success, failure otherwise
*/
int qed_ll2_get_stats(struct qed_hwfn *p_hwfn,
u8 connection_handle, struct qed_ll2_stats *p_stats);
/**
* @brief qed_ll2_alloc - Allocates LL2 connections set
*
* @param p_hwfn
*
* @return pointer to alocated qed_ll2_info or NULL
*/
struct qed_ll2_info *qed_ll2_alloc(struct qed_hwfn *p_hwfn);
/**
* @brief qed_ll2_setup - Inits LL2 connections set
*
* @param p_hwfn
* @param p_ll2_connections
*
*/
void qed_ll2_setup(struct qed_hwfn *p_hwfn,
struct qed_ll2_info *p_ll2_connections);
/**
* @brief qed_ll2_free - Releases LL2 connections set
*
* @param p_hwfn
* @param p_ll2_connections
*
*/
void qed_ll2_free(struct qed_hwfn *p_hwfn,
struct qed_ll2_info *p_ll2_connections);
void qed_ll2b_complete_rx_gsi_packet(struct qed_hwfn *p_hwfn,
u8 connection_handle,
void *cookie,
dma_addr_t rx_buf_addr,
u16 data_length,
u8 data_length_error,
u16 parse_flags,
u16 vlan,
u32 src_mac_addr_hi,
u16 src_mac_addr_lo, bool b_last_packet);
void qed_ll2b_complete_tx_gsi_packet(struct qed_hwfn *p_hwfn,
u8 connection_handle,
void *cookie,
dma_addr_t first_frag_addr,
bool b_last_fragment, bool b_last_packet);
void qed_ll2b_release_tx_gsi_packet(struct qed_hwfn *p_hwfn,
u8 connection_handle,
void *cookie,
dma_addr_t first_frag_addr,
bool b_last_fragment, bool b_last_packet);
#endif

67
drivers/net/ethernet/qlogic/qed/qed_main.c
View File

@ -22,15 +22,22 @@
#include <linux/etherdevice.h>
#include <linux/vmalloc.h>
#include <linux/qed/qed_if.h>
#include <linux/qed/qed_ll2_if.h>
#include "qed.h"
#include "qed_sriov.h"
#include "qed_sp.h"
#include "qed_dev_api.h"
#include "qed_ll2.h"
#include "qed_mcp.h"
#include "qed_hw.h"
#include "qed_selftest.h"
#if IS_ENABLED(CONFIG_INFINIBAND_QEDR)
#define QED_ROCE_QPS (8192)
#define QED_ROCE_DPIS (8)
#endif
static char version[] =
"QLogic FastLinQ 4xxxx Core Module qed " DRV_MODULE_VERSION "\n";
@ -204,8 +211,8 @@ int qed_fill_dev_info(struct qed_dev *cdev,
dev_info->pci_mem_start = cdev->pci_params.mem_start;
dev_info->pci_mem_end = cdev->pci_params.mem_end;
dev_info->pci_irq = cdev->pci_params.irq;
dev_info->rdma_supported =
(cdev->hwfns[0].hw_info.personality == QED_PCI_ETH_ROCE);
dev_info->rdma_supported = (cdev->hwfns[0].hw_info.personality ==
QED_PCI_ETH_ROCE);
dev_info->is_mf_default = IS_MF_DEFAULT(&cdev->hwfns[0]);
ether_addr_copy(dev_info->hw_mac, cdev->hwfns[0].hw_info.hw_mac_addr);
@ -608,7 +615,16 @@ static int qed_nic_reset(struct qed_dev *cdev)
static int qed_nic_setup(struct qed_dev *cdev)
{
int rc;
int rc, i;
/* Determine if interface is going to require LL2 */
if (QED_LEADING_HWFN(cdev)->hw_info.personality != QED_PCI_ETH) {
for (i = 0; i < cdev->num_hwfns; i++) {
struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
p_hwfn->using_ll2 = true;
}
}
rc = qed_resc_alloc(cdev);
if (rc)
@ -666,6 +682,9 @@ static int qed_slowpath_setup_int(struct qed_dev *cdev,
enum qed_int_mode int_mode)
{
struct qed_sb_cnt_info sb_cnt_info;
#if IS_ENABLED(CONFIG_INFINIBAND_QEDR)
int num_l2_queues;
#endif
int rc;
int i;
@ -696,6 +715,31 @@ static int qed_slowpath_setup_int(struct qed_dev *cdev,
cdev->int_params.fp_msix_cnt = cdev->int_params.out.num_vectors -
cdev->num_hwfns;
#if IS_ENABLED(CONFIG_INFINIBAND_QEDR)
num_l2_queues = 0;
for_each_hwfn(cdev, i)
num_l2_queues += FEAT_NUM(&cdev->hwfns[i], QED_PF_L2_QUE);
DP_VERBOSE(cdev, QED_MSG_RDMA,
"cdev->int_params.fp_msix_cnt=%d num_l2_queues=%d\n",
cdev->int_params.fp_msix_cnt, num_l2_queues);
if (cdev->int_params.fp_msix_cnt > num_l2_queues) {
cdev->int_params.rdma_msix_cnt =
(cdev->int_params.fp_msix_cnt - num_l2_queues)
/ cdev->num_hwfns;
cdev->int_params.rdma_msix_base =
cdev->int_params.fp_msix_base + num_l2_queues;
cdev->int_params.fp_msix_cnt = num_l2_queues;
} else {
cdev->int_params.rdma_msix_cnt = 0;
}
DP_VERBOSE(cdev, QED_MSG_RDMA, "roce_msix_cnt=%d roce_msix_base=%d\n",
cdev->int_params.rdma_msix_cnt,
cdev->int_params.rdma_msix_base);
#endif
return 0;
}
@ -799,6 +843,13 @@ static void qed_update_pf_params(struct qed_dev *cdev,
{
int i;
#if IS_ENABLED(CONFIG_INFINIBAND_QEDR)
params->rdma_pf_params.num_qps = QED_ROCE_QPS;
params->rdma_pf_params.min_dpis = QED_ROCE_DPIS;
/* divide by 3 the MRs to avoid MF ILT overflow */
params->rdma_pf_params.num_mrs = RDMA_MAX_TIDS;
params->rdma_pf_params.gl_pi = QED_ROCE_PROTOCOL_INDEX;
#endif
for (i = 0; i < cdev->num_hwfns; i++) {
struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
@ -873,6 +924,12 @@ static int qed_slowpath_start(struct qed_dev *cdev,
DP_INFO(cdev,
"HW initialization and function start completed successfully\n");
/* Allocate LL2 interface if needed */
if (QED_LEADING_HWFN(cdev)->using_ll2) {
rc = qed_ll2_alloc_if(cdev);
if (rc)
goto err3;
}
if (IS_PF(cdev)) {
hwfn = QED_LEADING_HWFN(cdev);
drv_version.version = (params->drv_major << 24) |
@ -893,6 +950,8 @@ static int qed_slowpath_start(struct qed_dev *cdev,
return 0;
err3:
qed_hw_stop(cdev);
err2:
qed_hw_timers_stop_all(cdev);
if (IS_PF(cdev))
@ -915,6 +974,8 @@ static int qed_slowpath_stop(struct qed_dev *cdev)
if (!cdev)
return -ENODEV;
qed_ll2_dealloc_if(cdev);
if (IS_PF(cdev)) {
qed_free_stream_mem(cdev);
if (IS_QED_ETH_IF(cdev))

30
drivers/net/ethernet/qlogic/qed/qed_reg_addr.h
View File

@ -208,6 +208,26 @@
0x50196cUL
#define NIG_REG_LLH_CLS_TYPE_DUALMODE \
0x501964UL
#define NIG_REG_LLH_FUNC_FILTER_VALUE \
0x501a00UL
#define NIG_REG_LLH_FUNC_FILTER_VALUE_SIZE \
32
#define NIG_REG_LLH_FUNC_FILTER_EN \
0x501a80UL
#define NIG_REG_LLH_FUNC_FILTER_EN_SIZE \
16
#define NIG_REG_LLH_FUNC_FILTER_MODE \
0x501ac0UL
#define NIG_REG_LLH_FUNC_FILTER_MODE_SIZE \
16
#define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE \
0x501b00UL
#define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_SIZE \
16
#define NIG_REG_LLH_FUNC_FILTER_HDR_SEL \
0x501b40UL
#define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_SIZE \
16
#define NCSI_REG_CONFIG \
0x040200UL
#define PBF_REG_INIT \
@ -264,6 +284,8 @@
0x1f0a1cUL
#define PRS_REG_ROCE_DEST_QP_MAX_PF \
0x1f0430UL
#define PRS_REG_USE_LIGHT_L2 \
0x1f096cUL
#define PSDM_REG_ENABLE_IN1 \
0xfa0004UL
#define PSEM_REG_ENABLE_IN \
@ -1426,5 +1448,11 @@
0x620000UL
#define PHY_PCIE_REG_PHY1 \
0x624000UL
#define NIG_REG_ROCE_DUPLICATE_TO_HOST 0x5088f0UL
#define PRS_REG_LIGHT_L2_ETHERTYPE_EN 0x1f0968UL
#define NIG_REG_LLH_ENG_CLS_ENG_ID_TBL 0x501b90UL
#define DORQ_REG_PF_DPM_ENABLE 0x100510UL
#define DORQ_REG_PF_ICID_BIT_SHIFT_NORM 0x100448UL
#define DORQ_REG_PF_MIN_ADDR_REG1 0x100400UL
#define DORQ_REG_PF_DPI_BIT_SHIFT 0x100450UL
#endif

2954
drivers/net/ethernet/qlogic/qed/qed_roce.c Normal file
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File diff suppressed because it is too large Load Diff

216
drivers/net/ethernet/qlogic/qed/qed_roce.h Normal file
View File

@ -0,0 +1,216 @@
/* QLogic qed NIC Driver
* Copyright (c) 2015-2016 QLogic Corporation
*
* This software is available to you under a choice of one of two
* licenses. You may choose to be licensed under the terms of the GNU
* General Public License (GPL) Version 2, available from the file
* COPYING in the main directory of this source tree, or the
* OpenIB.org BSD license below:
*
* Redistribution and use in source and binary forms, with or
* without modification, are permitted provided that the following
* conditions are met:
*
* - Redistributions of source code must retain the above
* copyright notice, this list of conditions and the following
* disclaimer.
*
* - Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and /or other materials
* provided with the distribution.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#ifndef _QED_ROCE_H
#define _QED_ROCE_H
#include <linux/types.h>
#include <linux/bitops.h>
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/qed/qed_if.h>
#include <linux/qed/qed_roce_if.h>
#include "qed.h"
#include "qed_dev_api.h"
#include "qed_hsi.h"
#include "qed_ll2.h"
#define QED_RDMA_MAX_FMR (RDMA_MAX_TIDS)
#define QED_RDMA_MAX_P_KEY (1)
#define QED_RDMA_MAX_WQE (0x7FFF)
#define QED_RDMA_MAX_SRQ_WQE_ELEM (0x7FFF)
#define QED_RDMA_PAGE_SIZE_CAPS (0xFFFFF000)
#define QED_RDMA_ACK_DELAY (15)
#define QED_RDMA_MAX_MR_SIZE (0x10000000000ULL)
#define QED_RDMA_MAX_CQS (RDMA_MAX_CQS)
#define QED_RDMA_MAX_MRS (RDMA_MAX_TIDS)
/* Add 1 for header element */
#define QED_RDMA_MAX_SRQ_ELEM_PER_WQE (RDMA_MAX_SGE_PER_RQ_WQE + 1)
#define QED_RDMA_MAX_SGE_PER_SRQ_WQE (RDMA_MAX_SGE_PER_RQ_WQE)
#define QED_RDMA_SRQ_WQE_ELEM_SIZE (16)
#define QED_RDMA_MAX_SRQS (32 * 1024)
#define QED_RDMA_MAX_CQE_32_BIT (0x7FFFFFFF - 1)
#define QED_RDMA_MAX_CQE_16_BIT (0x7FFF - 1)
enum qed_rdma_toggle_bit {
QED_RDMA_TOGGLE_BIT_CLEAR = 0,
QED_RDMA_TOGGLE_BIT_SET = 1
};
struct qed_bmap {
unsigned long *bitmap;
u32 max_count;
};
struct qed_rdma_info {
/* spin lock to protect bitmaps */
spinlock_t lock;
struct qed_bmap cq_map;
struct qed_bmap pd_map;
struct qed_bmap tid_map;
struct qed_bmap qp_map;
struct qed_bmap srq_map;
struct qed_bmap cid_map;
struct qed_bmap dpi_map;
struct qed_bmap toggle_bits;
struct qed_rdma_events events;
struct qed_rdma_device *dev;
struct qed_rdma_port *port;
u32 last_tid;
u8 num_cnqs;
u32 num_qps;
u32 num_mrs;
u16 queue_zone_base;
enum protocol_type proto;
};
struct qed_rdma_resize_cq_in_params {
u16 icid;
u32 cq_size;
bool pbl_two_level;
u64 pbl_ptr;
u16 pbl_num_pages;
u8 pbl_page_size_log;
};
struct qed_rdma_resize_cq_out_params {
u32 prod;
u32 cons;
};
struct qed_rdma_resize_cnq_in_params {
u32 cnq_id;
u32 pbl_page_size_log;
u64 pbl_ptr;
};
struct qed_rdma_qp {
struct regpair qp_handle;
struct regpair qp_handle_async;
u32 qpid;
u16 icid;
enum qed_roce_qp_state cur_state;
bool use_srq;
bool signal_all;
bool fmr_and_reserved_lkey;
bool incoming_rdma_read_en;
bool incoming_rdma_write_en;
bool incoming_atomic_en;
bool e2e_flow_control_en;
u16 pd;
u16 pkey;
u32 dest_qp;
u16 mtu;
u16 srq_id;
u8 traffic_class_tos;
u8 hop_limit_ttl;
u16 dpi;
u32 flow_label;
bool lb_indication;
u16 vlan_id;
u32 ack_timeout;
u8 retry_cnt;
u8 rnr_retry_cnt;
u8 min_rnr_nak_timer;
bool sqd_async;
union qed_gid sgid;
union qed_gid dgid;
enum roce_mode roce_mode;
u16 udp_src_port;
u8 stats_queue;
/* requeseter */
u8 max_rd_atomic_req;
u32 sq_psn;
u16 sq_cq_id;
u16 sq_num_pages;
dma_addr_t sq_pbl_ptr;
void *orq;
dma_addr_t orq_phys_addr;
u8 orq_num_pages;
bool req_offloaded;
/* responder */
u8 max_rd_atomic_resp;
u32 rq_psn;
u16 rq_cq_id;
u16 rq_num_pages;
dma_addr_t rq_pbl_ptr;
void *irq;
dma_addr_t irq_phys_addr;
u8 irq_num_pages;
bool resp_offloaded;
u8 remote_mac_addr[6];
u8 local_mac_addr[6];
void *shared_queue;
dma_addr_t shared_queue_phys_addr;
};
int
qed_rdma_add_user(void *rdma_cxt,
struct qed_rdma_add_user_out_params *out_params);
int qed_rdma_alloc_pd(void *rdma_cxt, u16 *pd);
int qed_rdma_alloc_tid(void *rdma_cxt, u32 *tid);
int qed_rdma_deregister_tid(void *rdma_cxt, u32 tid);
void qed_rdma_free_tid(void *rdma_cxt, u32 tid);
struct qed_rdma_device *qed_rdma_query_device(void *rdma_cxt);
struct qed_rdma_port *qed_rdma_query_port(void *rdma_cxt);
int
qed_rdma_register_tid(void *rdma_cxt,
struct qed_rdma_register_tid_in_params *params);
void qed_rdma_remove_user(void *rdma_cxt, u16 dpi);
int qed_rdma_start(void *p_hwfn, struct qed_rdma_start_in_params *params);
int qed_rdma_stop(void *rdma_cxt);
u32 qed_rdma_get_sb_id(void *p_hwfn, u32 rel_sb_id);
u32 qed_rdma_query_cau_timer_res(void *p_hwfn);
void qed_rdma_cnq_prod_update(void *rdma_cxt, u8 cnq_index, u16 prod);
void qed_rdma_resc_free(struct qed_hwfn *p_hwfn);
void qed_async_roce_event(struct qed_hwfn *p_hwfn,
struct event_ring_entry *p_eqe);
int qed_rdma_destroy_qp(void *rdma_cxt, struct qed_rdma_qp *qp);
int qed_rdma_modify_qp(void *rdma_cxt, struct qed_rdma_qp *qp,
struct qed_rdma_modify_qp_in_params *params);
int qed_rdma_query_qp(void *rdma_cxt, struct qed_rdma_qp *qp,
struct qed_rdma_query_qp_out_params *out_params);
#if IS_ENABLED(CONFIG_INFINIBAND_QEDR)
void qed_rdma_dpm_bar(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt);
#else
void qed_rdma_dpm_bar(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) {}
#endif
#endif

5
drivers/net/ethernet/qlogic/qed/qed_sp.h
View File

@ -61,6 +61,10 @@ union ramrod_data {
struct vport_start_ramrod_data vport_start;
struct vport_stop_ramrod_data vport_stop;
struct vport_update_ramrod_data vport_update;
struct core_rx_start_ramrod_data core_rx_queue_start;
struct core_rx_stop_ramrod_data core_rx_queue_stop;
struct core_tx_start_ramrod_data core_tx_queue_start;
struct core_tx_stop_ramrod_data core_tx_queue_stop;
struct vport_filter_update_ramrod_data vport_filter_update;
struct rdma_init_func_ramrod_data rdma_init_func;
@ -81,6 +85,7 @@ union ramrod_data {
struct rdma_srq_create_ramrod_data rdma_create_srq;
struct rdma_srq_destroy_ramrod_data rdma_destroy_srq;
struct rdma_srq_modify_ramrod_data rdma_modify_srq;
struct roce_init_func_ramrod_data roce_init_func;
struct iscsi_slow_path_hdr iscsi_empty;
struct iscsi_init_ramrod_params iscsi_init;

8
drivers/net/ethernet/qlogic/qed/qed_spq.c
View File

@ -28,6 +28,9 @@
#include "qed_reg_addr.h"
#include "qed_sp.h"
#include "qed_sriov.h"
#if IS_ENABLED(CONFIG_INFINIBAND_QEDR)
#include "qed_roce.h"
#endif
/***************************************************************************
* Structures & Definitions
@ -237,6 +240,11 @@ qed_async_event_completion(struct qed_hwfn *p_hwfn,
struct event_ring_entry *p_eqe)
{
switch (p_eqe->protocol_id) {
#if IS_ENABLED(CONFIG_INFINIBAND_QEDR)
case PROTOCOLID_ROCE:
qed_async_roce_event(p_hwfn, p_eqe);
return 0;
#endif
case PROTOCOLID_COMMON:
return qed_sriov_eqe_event(p_hwfn,
p_eqe->opcode,

4
drivers/net/ethernet/qlogic/qed/qed_sriov.c
View File

@ -1851,8 +1851,8 @@ static void qed_iov_vf_mbx_start_txq_resp(struct qed_hwfn *p_hwfn,
if ((status == PFVF_STATUS_SUCCESS) && !b_legacy) {
u16 qid = mbx->req_virt->start_txq.tx_qid;
p_tlv->offset = qed_db_addr(p_vf->vf_queues[qid].fw_cid,
DQ_DEMS_LEGACY);
p_tlv->offset = qed_db_addr_vf(p_vf->vf_queues[qid].fw_cid,
DQ_DEMS_LEGACY);
}
qed_iov_send_response(p_hwfn, p_ptt, p_vf, length, status);

2
drivers/net/ethernet/qlogic/qed/qed_vf.c
View File

@ -544,7 +544,7 @@ int qed_vf_pf_txq_start(struct qed_hwfn *p_hwfn,
u8 cid = p_iov->acquire_resp.resc.cid[tx_queue_id];
u32 db_addr;
db_addr = qed_db_addr(cid, DQ_DEMS_LEGACY);
db_addr = qed_db_addr_vf(cid, DQ_DEMS_LEGACY);
*pp_doorbell = (u8 __iomem *)p_hwfn->doorbells +
db_addr;
}

1
drivers/net/ethernet/qlogic/qede/Makefile
View File

@ -2,3 +2,4 @@ obj-$(CONFIG_QEDE) := qede.o
qede-y := qede_main.o qede_ethtool.o
qede-$(CONFIG_DCB) += qede_dcbnl.o
qede-$(CONFIG_INFINIBAND_QEDR) += qede_roce.o

9
drivers/net/ethernet/qlogic/qede/qede.h
View File

@ -106,6 +106,13 @@ struct qede_vlan {
bool configured;
};
struct qede_rdma_dev {
struct qedr_dev *qedr_dev;
struct list_head entry;
struct list_head roce_event_list;
struct workqueue_struct *roce_wq;
};
struct qede_dev {
struct qed_dev *cdev;
struct net_device *ndev;
@ -185,6 +192,8 @@ struct qede_dev {
unsigned long sp_flags;
u16 vxlan_dst_port;
u16 geneve_dst_port;
struct qede_rdma_dev rdma_info;
};
enum QEDE_STATE {

35
drivers/net/ethernet/qlogic/qede/qede_main.c
View File

@ -36,7 +36,7 @@
#include <linux/random.h>
#include <net/ip6_checksum.h>
#include <linux/bitops.h>
#include <linux/qed/qede_roce.h>
#include "qede.h"
static char version[] =
@ -193,8 +193,7 @@ static int qede_netdev_event(struct notifier_block *this, unsigned long event,
struct ethtool_drvinfo drvinfo;
struct qede_dev *edev;
/* Currently only support name change */
if (event != NETDEV_CHANGENAME)
if (event != NETDEV_CHANGENAME && event != NETDEV_CHANGEADDR)
goto done;
/* Check whether this is a qede device */
@ -207,11 +206,18 @@ static int qede_netdev_event(struct notifier_block *this, unsigned long event,
goto done;
edev = netdev_priv(ndev);
/* Notify qed of the name change */
if (!edev->ops || !edev->ops->common)
goto done;
edev->ops->common->set_id(edev->cdev, edev->ndev->name,
"qede");
switch (event) {
case NETDEV_CHANGENAME:
/* Notify qed of the name change */
if (!edev->ops || !edev->ops->common)
goto done;
edev->ops->common->set_id(edev->cdev, edev->ndev->name, "qede");
break;
case NETDEV_CHANGEADDR:
edev = netdev_priv(ndev);
qede_roce_event_changeaddr(edev);
break;
}
done:
return NOTIFY_DONE;
@ -2545,10 +2551,14 @@ static int __qede_probe(struct pci_dev *pdev, u32 dp_module, u8 dp_level,
qede_init_ndev(edev);
rc = qede_roce_dev_add(edev);
if (rc)
goto err3;
rc = register_netdev(edev->ndev);
if (rc) {
DP_NOTICE(edev, "Cannot register net-device\n");
goto err3;
goto err4;
}
edev->ops->common->set_id(cdev, edev->ndev->name, DRV_MODULE_VERSION);
@ -2568,6 +2578,8 @@ static int __qede_probe(struct pci_dev *pdev, u32 dp_module, u8 dp_level,
return 0;
err4:
qede_roce_dev_remove(edev);
err3:
free_netdev(edev->ndev);
err2:
@ -2614,8 +2626,11 @@ static void __qede_remove(struct pci_dev *pdev, enum qede_remove_mode mode)
DP_INFO(edev, "Starting qede_remove\n");
cancel_delayed_work_sync(&edev->sp_task);
unregister_netdev(ndev);
qede_roce_dev_remove(edev);
edev->ops->common->set_power_state(cdev, PCI_D0);
pci_set_drvdata(pdev, NULL);
@ -3512,6 +3527,7 @@ static void qede_unload(struct qede_dev *edev, enum qede_unload_mode mode)
DP_INFO(edev, "Starting qede unload\n");
qede_roce_dev_event_close(edev);
mutex_lock(&edev->qede_lock);
edev->state = QEDE_STATE_CLOSED;
@ -3612,6 +3628,7 @@ static int qede_load(struct qede_dev *edev, enum qede_load_mode mode)
/* Query whether link is already-up */
memset(&link_output, 0, sizeof(link_output));
edev->ops->common->get_link(edev->cdev, &link_output);
qede_roce_dev_event_open(edev);
qede_link_update(edev, &link_output);
DP_INFO(edev, "Ending successfully qede load\n");

314
drivers/net/ethernet/qlogic/qede/qede_roce.c Normal file
View File

@ -0,0 +1,314 @@
/* QLogic qedr NIC Driver
* Copyright (c) 2015-2016 QLogic Corporation
*
* This software is available to you under a choice of one of two
* licenses. You may choose to be licensed under the terms of the GNU
* General Public License (GPL) Version 2, available from the file
* COPYING in the main directory of this source tree, or the
* OpenIB.org BSD license below:
*
* Redistribution and use in source and binary forms, with or
* without modification, are permitted provided that the following
* conditions are met:
*
* - Redistributions of source code must retain the above
* copyright notice, this list of conditions and the following
* disclaimer.
*
* - Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and /or other materials
* provided with the distribution.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#include <linux/pci.h>
#include <linux/netdevice.h>
#include <linux/list.h>
#include <linux/mutex.h>
#include <linux/qed/qede_roce.h>
#include "qede.h"
static struct qedr_driver *qedr_drv;
static LIST_HEAD(qedr_dev_list);
static DEFINE_MUTEX(qedr_dev_list_lock);
bool qede_roce_supported(struct qede_dev *dev)
{
return dev->dev_info.common.rdma_supported;
}
static void _qede_roce_dev_add(struct qede_dev *edev)
{
if (!qedr_drv)
return;
edev->rdma_info.qedr_dev = qedr_drv->add(edev->cdev, edev->pdev,
edev->ndev);
}
static int qede_roce_create_wq(struct qede_dev *edev)
{
INIT_LIST_HEAD(&edev->rdma_info.roce_event_list);
edev->rdma_info.roce_wq = create_singlethread_workqueue("roce_wq");
if (!edev->rdma_info.roce_wq) {
DP_NOTICE(edev, "qedr: Could not create workqueue\n");
return -ENOMEM;
}
return 0;
}
static void qede_roce_cleanup_event(struct qede_dev *edev)
{
struct list_head *head = &edev->rdma_info.roce_event_list;
struct qede_roce_event_work *event_node;
flush_workqueue(edev->rdma_info.roce_wq);
while (!list_empty(head)) {
event_node = list_entry(head->next, struct qede_roce_event_work,
list);
cancel_work_sync(&event_node->work);
list_del(&event_node->list);
kfree(event_node);
}
}
static void qede_roce_destroy_wq(struct qede_dev *edev)
{
qede_roce_cleanup_event(edev);
destroy_workqueue(edev->rdma_info.roce_wq);
}
int qede_roce_dev_add(struct qede_dev *edev)
{
int rc = 0;
if (qede_roce_supported(edev)) {
rc = qede_roce_create_wq(edev);
if (rc)
return rc;
INIT_LIST_HEAD(&edev->rdma_info.entry);
mutex_lock(&qedr_dev_list_lock);
list_add_tail(&edev->rdma_info.entry, &qedr_dev_list);
_qede_roce_dev_add(edev);
mutex_unlock(&qedr_dev_list_lock);
}
return rc;
}
static void _qede_roce_dev_remove(struct qede_dev *edev)
{
if (qedr_drv && qedr_drv->remove && edev->rdma_info.qedr_dev)
qedr_drv->remove(edev->rdma_info.qedr_dev);
edev->rdma_info.qedr_dev = NULL;
}
void qede_roce_dev_remove(struct qede_dev *edev)
{
if (!qede_roce_supported(edev))
return;
qede_roce_destroy_wq(edev);
mutex_lock(&qedr_dev_list_lock);
_qede_roce_dev_remove(edev);
list_del(&edev->rdma_info.entry);
mutex_unlock(&qedr_dev_list_lock);
}
static void _qede_roce_dev_open(struct qede_dev *edev)
{
if (qedr_drv && edev->rdma_info.qedr_dev && qedr_drv->notify)
qedr_drv->notify(edev->rdma_info.qedr_dev, QEDE_UP);
}
static void qede_roce_dev_open(struct qede_dev *edev)
{
if (!qede_roce_supported(edev))
return;
mutex_lock(&qedr_dev_list_lock);
_qede_roce_dev_open(edev);
mutex_unlock(&qedr_dev_list_lock);
}
static void _qede_roce_dev_close(struct qede_dev *edev)
{
if (qedr_drv && edev->rdma_info.qedr_dev && qedr_drv->notify)
qedr_drv->notify(edev->rdma_info.qedr_dev, QEDE_DOWN);
}
static void qede_roce_dev_close(struct qede_dev *edev)
{
if (!qede_roce_supported(edev))
return;
mutex_lock(&qedr_dev_list_lock);
_qede_roce_dev_close(edev);
mutex_unlock(&qedr_dev_list_lock);
}
static void qede_roce_dev_shutdown(struct qede_dev *edev)
{
if (!qede_roce_supported(edev))
return;
mutex_lock(&qedr_dev_list_lock);
if (qedr_drv && edev->rdma_info.qedr_dev && qedr_drv->notify)
qedr_drv->notify(edev->rdma_info.qedr_dev, QEDE_CLOSE);
mutex_unlock(&qedr_dev_list_lock);
}
int qede_roce_register_driver(struct qedr_driver *drv)
{
struct qede_dev *edev;
u8 qedr_counter = 0;
mutex_lock(&qedr_dev_list_lock);
if (qedr_drv) {
mutex_unlock(&qedr_dev_list_lock);
return -EINVAL;
}
qedr_drv = drv;
list_for_each_entry(edev, &qedr_dev_list, rdma_info.entry) {
struct net_device *ndev;
qedr_counter++;
_qede_roce_dev_add(edev);
ndev = edev->ndev;
if (netif_running(ndev) && netif_oper_up(ndev))
_qede_roce_dev_open(edev);
}
mutex_unlock(&qedr_dev_list_lock);
DP_INFO(edev, "qedr: discovered and registered %d RoCE funcs\n",
qedr_counter);
return 0;
}
EXPORT_SYMBOL(qede_roce_register_driver);
void qede_roce_unregister_driver(struct qedr_driver *drv)
{
struct qede_dev *edev;
mutex_lock(&qedr_dev_list_lock);
list_for_each_entry(edev, &qedr_dev_list, rdma_info.entry) {
if (edev->rdma_info.qedr_dev)
_qede_roce_dev_remove(edev);
}
qedr_drv = NULL;
mutex_unlock(&qedr_dev_list_lock);
}
EXPORT_SYMBOL(qede_roce_unregister_driver);
static void qede_roce_changeaddr(struct qede_dev *edev)
{
if (!qede_roce_supported(edev))
return;
if (qedr_drv && edev->rdma_info.qedr_dev && qedr_drv->notify)
qedr_drv->notify(edev->rdma_info.qedr_dev, QEDE_CHANGE_ADDR);
}
struct qede_roce_event_work *qede_roce_get_free_event_node(struct qede_dev
*edev)
{
struct qede_roce_event_work *event_node = NULL;
struct list_head *list_node = NULL;
bool found = false;
list_for_each(list_node, &edev->rdma_info.roce_event_list) {
event_node = list_entry(list_node, struct qede_roce_event_work,
list);
if (!work_pending(&event_node->work)) {
found = true;
break;
}
}
if (!found) {
event_node = kzalloc(sizeof(*event_node), GFP_KERNEL);
if (!event_node) {
DP_NOTICE(edev,
"qedr: Could not allocate memory for roce work\n");
return NULL;
}
list_add_tail(&event_node->list,
&edev->rdma_info.roce_event_list);
}
return event_node;
}
static void qede_roce_handle_event(struct work_struct *work)
{
struct qede_roce_event_work *event_node;
enum qede_roce_event event;
struct qede_dev *edev;
event_node = container_of(work, struct qede_roce_event_work, work);
event = event_node->event;
edev = event_node->ptr;
switch (event) {
case QEDE_UP:
qede_roce_dev_open(edev);
break;
case QEDE_DOWN:
qede_roce_dev_close(edev);
break;
case QEDE_CLOSE:
qede_roce_dev_shutdown(edev);
break;
case QEDE_CHANGE_ADDR:
qede_roce_changeaddr(edev);
break;
default:
DP_NOTICE(edev, "Invalid roce event %d", event);
}
}
static void qede_roce_add_event(struct qede_dev *edev,
enum qede_roce_event event)
{
struct qede_roce_event_work *event_node;
if (!edev->rdma_info.qedr_dev)
return;
event_node = qede_roce_get_free_event_node(edev);
if (!event_node)
return;
event_node->event = event;
event_node->ptr = edev;
INIT_WORK(&event_node->work, qede_roce_handle_event);
queue_work(edev->rdma_info.roce_wq, &event_node->work);
}
void qede_roce_dev_event_open(struct qede_dev *edev)
{
qede_roce_add_event(edev, QEDE_UP);
}
void qede_roce_dev_event_close(struct qede_dev *edev)
{
qede_roce_add_event(edev, QEDE_DOWN);
}
void qede_roce_event_changeaddr(struct qede_dev *edev)
{
qede_roce_add_event(edev, QEDE_CHANGE_ADDR);
}

1
include/linux/qed/common_hsi.h
View File

@ -674,6 +674,7 @@ union event_ring_data {
struct iscsi_eqe_data iscsi_info;
struct malicious_vf_eqe_data malicious_vf;
struct initial_cleanup_eqe_data vf_init_cleanup;
struct regpair roce_handle;
};
/* Event Ring Entry */

9
include/linux/qed/qed_if.h
View File

@ -34,6 +34,8 @@ enum dcbx_protocol_type {
DCBX_MAX_PROTOCOL_TYPE
};
#define QED_ROCE_PROTOCOL_INDEX (3)
#ifdef CONFIG_DCB
#define QED_LLDP_CHASSIS_ID_STAT_LEN 4
#define QED_LLDP_PORT_ID_STAT_LEN 4
@ -260,15 +262,15 @@ struct qed_dev_info {
/* MFW version */
u32 mfw_rev;
bool rdma_supported;
u32 flash_size;
u8 mf_mode;
bool tx_switching;
bool rdma_supported;
};
enum qed_sb_type {
QED_SB_TYPE_L2_QUEUE,
QED_SB_TYPE_CNQ,
};
enum qed_protocol {
@ -627,8 +629,9 @@ enum DP_MODULE {
QED_MSG_SP = 0x100000,
QED_MSG_STORAGE = 0x200000,
QED_MSG_CXT = 0x800000,
QED_MSG_LL2 = 0x1000000,
QED_MSG_ILT = 0x2000000,
QED_MSG_ROCE = 0x4000000,
QED_MSG_RDMA = 0x4000000,
QED_MSG_DEBUG = 0x8000000,
/* to be added...up to 0x8000000 */
};

139
include/linux/qed/qed_ll2_if.h Normal file
View File

@ -0,0 +1,139 @@
/* QLogic qed NIC Driver
*
* Copyright (c) 2015 QLogic Corporation
*
* This software is available under the terms of the GNU General Public License
* (GPL) Version 2, available from the file COPYING in the main directory of
* this source tree.
*/
#ifndef _QED_LL2_IF_H
#define _QED_LL2_IF_H
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/netdevice.h>
#include <linux/pci.h>
#include <linux/skbuff.h>
#include <linux/version.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/qed/qed_if.h>
struct qed_ll2_stats {
u64 gsi_invalid_hdr;
u64 gsi_invalid_pkt_length;
u64 gsi_unsupported_pkt_typ;
u64 gsi_crcchksm_error;
u64 packet_too_big_discard;
u64 no_buff_discard;
u64 rcv_ucast_bytes;
u64 rcv_mcast_bytes;
u64 rcv_bcast_bytes;
u64 rcv_ucast_pkts;
u64 rcv_mcast_pkts;
u64 rcv_bcast_pkts;
u64 sent_ucast_bytes;
u64 sent_mcast_bytes;
u64 sent_bcast_bytes;
u64 sent_ucast_pkts;
u64 sent_mcast_pkts;
u64 sent_bcast_pkts;
};
#define QED_LL2_UNUSED_HANDLE (0xff)
struct qed_ll2_cb_ops {
int (*rx_cb)(void *, struct sk_buff *, u32, u32);
int (*tx_cb)(void *, struct sk_buff *, bool);
};
struct qed_ll2_params {
u16 mtu;
bool drop_ttl0_packets;
bool rx_vlan_stripping;
u8 tx_tc;
bool frags_mapped;
u8 ll2_mac_address[ETH_ALEN];
};
struct qed_ll2_ops {
/**
* @brief start - initializes ll2
*
* @param cdev
* @param params - protocol driver configuration for the ll2.
*
* @return 0 on success, otherwise error value.
*/
int (*start)(struct qed_dev *cdev, struct qed_ll2_params *params);
/**
* @brief stop - stops the ll2
*
* @param cdev
*
* @return 0 on success, otherwise error value.
*/
int (*stop)(struct qed_dev *cdev);
/**
* @brief start_xmit - transmits an skb over the ll2 interface
*
* @param cdev
* @param skb
*
* @return 0 on success, otherwise error value.
*/
int (*start_xmit)(struct qed_dev *cdev, struct sk_buff *skb);
/**
* @brief register_cb_ops - protocol driver register the callback for Rx/Tx
* packets. Should be called before `start'.
*
* @param cdev
* @param cookie - to be passed to the callback functions.
* @param ops - the callback functions to register for Rx / Tx.
*
* @return 0 on success, otherwise error value.
*/
void (*register_cb_ops)(struct qed_dev *cdev,
const struct qed_ll2_cb_ops *ops,
void *cookie);
/**
* @brief get LL2 related statistics
*
* @param cdev
* @param stats - pointer to struct that would be filled with stats
*
* @return 0 on success, error otherwise.
*/
int (*get_stats)(struct qed_dev *cdev, struct qed_ll2_stats *stats);
};
#ifdef CONFIG_QED_LL2
int qed_ll2_alloc_if(struct qed_dev *);
void qed_ll2_dealloc_if(struct qed_dev *);
#else
static const struct qed_ll2_ops qed_ll2_ops_pass = {
.start = NULL,
.stop = NULL,
.start_xmit = NULL,
.register_cb_ops = NULL,
.get_stats = NULL,
};
static inline int qed_ll2_alloc_if(struct qed_dev *cdev)
{
return 0;
}
static inline void qed_ll2_dealloc_if(struct qed_dev *cdev)
{
}
#endif
#endif

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/* QLogic qed NIC Driver
* Copyright (c) 2015-2016 QLogic Corporation
*
* This software is available to you under a choice of one of two
* licenses. You may choose to be licensed under the terms of the GNU
* General Public License (GPL) Version 2, available from the file
* COPYING in the main directory of this source tree, or the
* OpenIB.org BSD license below:
*
* Redistribution and use in source and binary forms, with or
* without modification, are permitted provided that the following
* conditions are met:
*
* - Redistributions of source code must retain the above
* copyright notice, this list of conditions and the following
* disclaimer.
*
* - Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and /or other materials
* provided with the distribution.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#ifndef _QED_ROCE_IF_H
#define _QED_ROCE_IF_H
#include <linux/types.h>
#include <linux/delay.h>
#include <linux/list.h>
#include <linux/mutex.h>
#include <linux/pci.h>
#include <linux/slab.h>
#include <linux/qed/qed_if.h>
#include <linux/qed/qed_ll2_if.h>
#include <linux/qed/rdma_common.h>
enum qed_roce_ll2_tx_dest {
/* Light L2 TX Destination to the Network */
QED_ROCE_LL2_TX_DEST_NW,
/* Light L2 TX Destination to the Loopback */
QED_ROCE_LL2_TX_DEST_LB,
QED_ROCE_LL2_TX_DEST_MAX
};
#define QED_RDMA_MAX_CNQ_SIZE (0xFFFF)
/* rdma interface */
enum qed_roce_qp_state {
QED_ROCE_QP_STATE_RESET,
QED_ROCE_QP_STATE_INIT,
QED_ROCE_QP_STATE_RTR,
QED_ROCE_QP_STATE_RTS,
QED_ROCE_QP_STATE_SQD,
QED_ROCE_QP_STATE_ERR,
QED_ROCE_QP_STATE_SQE
};
enum qed_rdma_tid_type {
QED_RDMA_TID_REGISTERED_MR,
QED_RDMA_TID_FMR,
QED_RDMA_TID_MW_TYPE1,
QED_RDMA_TID_MW_TYPE2A
};
struct qed_rdma_events {
void *context;
void (*affiliated_event)(void *context, u8 fw_event_code,
void *fw_handle);
void (*unaffiliated_event)(void *context, u8 event_code);
};
struct qed_rdma_device {
u32 vendor_id;
u32 vendor_part_id;
u32 hw_ver;
u64 fw_ver;
u64 node_guid;
u64 sys_image_guid;
u8 max_cnq;
u8 max_sge;
u8 max_srq_sge;
u16 max_inline;
u32 max_wqe;
u32 max_srq_wqe;
u8 max_qp_resp_rd_atomic_resc;
u8 max_qp_req_rd_atomic_resc;
u64 max_dev_resp_rd_atomic_resc;
u32 max_cq;
u32 max_qp;
u32 max_srq;
u32 max_mr;
u64 max_mr_size;
u32 max_cqe;
u32 max_mw;
u32 max_fmr;
u32 max_mr_mw_fmr_pbl;
u64 max_mr_mw_fmr_size;
u32 max_pd;
u32 max_ah;
u8 max_pkey;
u16 max_srq_wr;
u8 max_stats_queues;
u32 dev_caps;
/* Abilty to support RNR-NAK generation */
#define QED_RDMA_DEV_CAP_RNR_NAK_MASK 0x1
#define QED_RDMA_DEV_CAP_RNR_NAK_SHIFT 0
/* Abilty to support shutdown port */
#define QED_RDMA_DEV_CAP_SHUTDOWN_PORT_MASK 0x1
#define QED_RDMA_DEV_CAP_SHUTDOWN_PORT_SHIFT 1
/* Abilty to support port active event */
#define QED_RDMA_DEV_CAP_PORT_ACTIVE_EVENT_MASK 0x1
#define QED_RDMA_DEV_CAP_PORT_ACTIVE_EVENT_SHIFT 2
/* Abilty to support port change event */
#define QED_RDMA_DEV_CAP_PORT_CHANGE_EVENT_MASK 0x1
#define QED_RDMA_DEV_CAP_PORT_CHANGE_EVENT_SHIFT 3
/* Abilty to support system image GUID */
#define QED_RDMA_DEV_CAP_SYS_IMAGE_MASK 0x1
#define QED_RDMA_DEV_CAP_SYS_IMAGE_SHIFT 4
/* Abilty to support bad P_Key counter support */
#define QED_RDMA_DEV_CAP_BAD_PKEY_CNT_MASK 0x1
#define QED_RDMA_DEV_CAP_BAD_PKEY_CNT_SHIFT 5
/* Abilty to support atomic operations */
#define QED_RDMA_DEV_CAP_ATOMIC_OP_MASK 0x1
#define QED_RDMA_DEV_CAP_ATOMIC_OP_SHIFT 6
#define QED_RDMA_DEV_CAP_RESIZE_CQ_MASK 0x1
#define QED_RDMA_DEV_CAP_RESIZE_CQ_SHIFT 7
/* Abilty to support modifying the maximum number of
* outstanding work requests per QP
*/
#define QED_RDMA_DEV_CAP_RESIZE_MAX_WR_MASK 0x1
#define QED_RDMA_DEV_CAP_RESIZE_MAX_WR_SHIFT 8
/* Abilty to support automatic path migration */
#define QED_RDMA_DEV_CAP_AUTO_PATH_MIG_MASK 0x1
#define QED_RDMA_DEV_CAP_AUTO_PATH_MIG_SHIFT 9
/* Abilty to support the base memory management extensions */
#define QED_RDMA_DEV_CAP_BASE_MEMORY_EXT_MASK 0x1
#define QED_RDMA_DEV_CAP_BASE_MEMORY_EXT_SHIFT 10
#define QED_RDMA_DEV_CAP_BASE_QUEUE_EXT_MASK 0x1
#define QED_RDMA_DEV_CAP_BASE_QUEUE_EXT_SHIFT 11
/* Abilty to support multipile page sizes per memory region */
#define QED_RDMA_DEV_CAP_MULTI_PAGE_PER_MR_EXT_MASK 0x1
#define QED_RDMA_DEV_CAP_MULTI_PAGE_PER_MR_EXT_SHIFT 12
/* Abilty to support block list physical buffer list */
#define QED_RDMA_DEV_CAP_BLOCK_MODE_MASK 0x1
#define QED_RDMA_DEV_CAP_BLOCK_MODE_SHIFT 13
/* Abilty to support zero based virtual addresses */
#define QED_RDMA_DEV_CAP_ZBVA_MASK 0x1
#define QED_RDMA_DEV_CAP_ZBVA_SHIFT 14
/* Abilty to support local invalidate fencing */
#define QED_RDMA_DEV_CAP_LOCAL_INV_FENCE_MASK 0x1
#define QED_RDMA_DEV_CAP_LOCAL_INV_FENCE_SHIFT 15
/* Abilty to support Loopback on QP */
#define QED_RDMA_DEV_CAP_LB_INDICATOR_MASK 0x1
#define QED_RDMA_DEV_CAP_LB_INDICATOR_SHIFT 16
u64 page_size_caps;
u8 dev_ack_delay;
u32 reserved_lkey;
u32 bad_pkey_counter;
struct qed_rdma_events events;
};
enum qed_port_state {
QED_RDMA_PORT_UP,
QED_RDMA_PORT_DOWN,
};
enum qed_roce_capability {
QED_ROCE_V1 = 1 << 0,
QED_ROCE_V2 = 1 << 1,
};
struct qed_rdma_port {
enum qed_port_state port_state;
int link_speed;
u64 max_msg_size;
u8 source_gid_table_len;
void *source_gid_table_ptr;
u8 pkey_table_len;
void *pkey_table_ptr;
u32 pkey_bad_counter;
enum qed_roce_capability capability;
};
struct qed_rdma_cnq_params {
u8 num_pbl_pages;
u64 pbl_ptr;
};
/* The CQ Mode affects the CQ doorbell transaction size.
* 64/32 bit machines should configure to 32/16 bits respectively.
*/
enum qed_rdma_cq_mode {
QED_RDMA_CQ_MODE_16_BITS,
QED_RDMA_CQ_MODE_32_BITS,
};
struct qed_roce_dcqcn_params {
u8 notification_point;
u8 reaction_point;
/* fields for notification point */
u32 cnp_send_timeout;
/* fields for reaction point */
u32 rl_bc_rate;
u16 rl_max_rate;
u16 rl_r_ai;
u16 rl_r_hai;
u16 dcqcn_g;
u32 dcqcn_k_us;
u32 dcqcn_timeout_us;
};
struct qed_rdma_start_in_params {
struct qed_rdma_events *events;
struct qed_rdma_cnq_params cnq_pbl_list[128];
u8 desired_cnq;
enum qed_rdma_cq_mode cq_mode;
struct qed_roce_dcqcn_params dcqcn_params;
u16 max_mtu;
u8 mac_addr[ETH_ALEN];
u8 iwarp_flags;
};
struct qed_rdma_add_user_out_params {
u16 dpi;
u64 dpi_addr;
u64 dpi_phys_addr;
u32 dpi_size;
};
enum roce_mode {
ROCE_V1,
ROCE_V2_IPV4,
ROCE_V2_IPV6,
MAX_ROCE_MODE
};
union qed_gid {
u8 bytes[16];
u16 words[8];
u32 dwords[4];
u64 qwords[2];
u32 ipv4_addr;
};
struct qed_rdma_register_tid_in_params {
u32 itid;
enum qed_rdma_tid_type tid_type;
u8 key;
u16 pd;
bool local_read;
bool local_write;
bool remote_read;
bool remote_write;
bool remote_atomic;
bool mw_bind;
u64 pbl_ptr;
bool pbl_two_level;
u8 pbl_page_size_log;
u8 page_size_log;
u32 fbo;
u64 length;
u64 vaddr;
bool zbva;
bool phy_mr;
bool dma_mr;
bool dif_enabled;
u64 dif_error_addr;
u64 dif_runt_addr;
};
struct qed_rdma_create_cq_in_params {
u32 cq_handle_lo;
u32 cq_handle_hi;
u32 cq_size;
u16 dpi;
bool pbl_two_level;
u64 pbl_ptr;
u16 pbl_num_pages;
u8 pbl_page_size_log;
u8 cnq_id;
u16 int_timeout;
};
struct qed_rdma_create_srq_in_params {
u64 pbl_base_addr;
u64 prod_pair_addr;
u16 num_pages;
u16 pd_id;
u16 page_size;
};
struct qed_rdma_destroy_cq_in_params {
u16 icid;
};
struct qed_rdma_destroy_cq_out_params {
u16 num_cq_notif;
};
struct qed_rdma_create_qp_in_params {
u32 qp_handle_lo;
u32 qp_handle_hi;
u32 qp_handle_async_lo;
u32 qp_handle_async_hi;
bool use_srq;
bool signal_all;
bool fmr_and_reserved_lkey;
u16 pd;
u16 dpi;
u16 sq_cq_id;
u16 sq_num_pages;
u64 sq_pbl_ptr;
u8 max_sq_sges;
u16 rq_cq_id;
u16 rq_num_pages;
u64 rq_pbl_ptr;
u16 srq_id;
u8 stats_queue;
};
struct qed_rdma_create_qp_out_params {
u32 qp_id;
u16 icid;
void *rq_pbl_virt;
dma_addr_t rq_pbl_phys;
void *sq_pbl_virt;
dma_addr_t sq_pbl_phys;
};
struct qed_rdma_modify_qp_in_params {
u32 modify_flags;
#define QED_RDMA_MODIFY_QP_VALID_NEW_STATE_MASK 0x1
#define QED_RDMA_MODIFY_QP_VALID_NEW_STATE_SHIFT 0
#define QED_ROCE_MODIFY_QP_VALID_PKEY_MASK 0x1
#define QED_ROCE_MODIFY_QP_VALID_PKEY_SHIFT 1
#define QED_RDMA_MODIFY_QP_VALID_RDMA_OPS_EN_MASK 0x1
#define QED_RDMA_MODIFY_QP_VALID_RDMA_OPS_EN_SHIFT 2
#define QED_ROCE_MODIFY_QP_VALID_DEST_QP_MASK 0x1
#define QED_ROCE_MODIFY_QP_VALID_DEST_QP_SHIFT 3
#define QED_ROCE_MODIFY_QP_VALID_ADDRESS_VECTOR_MASK 0x1
#define QED_ROCE_MODIFY_QP_VALID_ADDRESS_VECTOR_SHIFT 4
#define QED_ROCE_MODIFY_QP_VALID_RQ_PSN_MASK 0x1
#define QED_ROCE_MODIFY_QP_VALID_RQ_PSN_SHIFT 5
#define QED_ROCE_MODIFY_QP_VALID_SQ_PSN_MASK 0x1
#define QED_ROCE_MODIFY_QP_VALID_SQ_PSN_SHIFT 6
#define QED_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_REQ_MASK 0x1
#define QED_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_REQ_SHIFT 7
#define QED_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_RESP_MASK 0x1
#define QED_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_RESP_SHIFT 8
#define QED_ROCE_MODIFY_QP_VALID_ACK_TIMEOUT_MASK 0x1
#define QED_ROCE_MODIFY_QP_VALID_ACK_TIMEOUT_SHIFT 9
#define QED_ROCE_MODIFY_QP_VALID_RETRY_CNT_MASK 0x1
#define QED_ROCE_MODIFY_QP_VALID_RETRY_CNT_SHIFT 10
#define QED_ROCE_MODIFY_QP_VALID_RNR_RETRY_CNT_MASK 0x1
#define QED_ROCE_MODIFY_QP_VALID_RNR_RETRY_CNT_SHIFT 11
#define QED_ROCE_MODIFY_QP_VALID_MIN_RNR_NAK_TIMER_MASK 0x1
#define QED_ROCE_MODIFY_QP_VALID_MIN_RNR_NAK_TIMER_SHIFT 12
#define QED_ROCE_MODIFY_QP_VALID_E2E_FLOW_CONTROL_EN_MASK 0x1
#define QED_ROCE_MODIFY_QP_VALID_E2E_FLOW_CONTROL_EN_SHIFT 13
#define QED_ROCE_MODIFY_QP_VALID_ROCE_MODE_MASK 0x1
#define QED_ROCE_MODIFY_QP_VALID_ROCE_MODE_SHIFT 14
enum qed_roce_qp_state new_state;
u16 pkey;
bool incoming_rdma_read_en;
bool incoming_rdma_write_en;
bool incoming_atomic_en;
bool e2e_flow_control_en;
u32 dest_qp;
bool lb_indication;
u16 mtu;
u8 traffic_class_tos;
u8 hop_limit_ttl;
u32 flow_label;
union qed_gid sgid;
union qed_gid dgid;
u16 udp_src_port;
u16 vlan_id;
u32 rq_psn;
u32 sq_psn;
u8 max_rd_atomic_resp;
u8 max_rd_atomic_req;
u32 ack_timeout;
u8 retry_cnt;
u8 rnr_retry_cnt;
u8 min_rnr_nak_timer;
bool sqd_async;
u8 remote_mac_addr[6];
u8 local_mac_addr[6];
bool use_local_mac;
enum roce_mode roce_mode;
};
struct qed_rdma_query_qp_out_params {
enum qed_roce_qp_state state;
u32 rq_psn;
u32 sq_psn;
bool draining;
u16 mtu;
u32 dest_qp;
bool incoming_rdma_read_en;
bool incoming_rdma_write_en;
bool incoming_atomic_en;
bool e2e_flow_control_en;
union qed_gid sgid;
union qed_gid dgid;
u32 flow_label;
u8 hop_limit_ttl;
u8 traffic_class_tos;
u32 timeout;
u8 rnr_retry;
u8 retry_cnt;
u8 min_rnr_nak_timer;
u16 pkey_index;
u8 max_rd_atomic;
u8 max_dest_rd_atomic;
bool sqd_async;
};
struct qed_rdma_create_srq_out_params {
u16 srq_id;
};
struct qed_rdma_destroy_srq_in_params {
u16 srq_id;
};
struct qed_rdma_modify_srq_in_params {
u32 wqe_limit;
u16 srq_id;
};
struct qed_rdma_stats_out_params {
u64 sent_bytes;
u64 sent_pkts;
u64 rcv_bytes;
u64 rcv_pkts;
};
struct qed_rdma_counters_out_params {
u64 pd_count;
u64 max_pd;
u64 dpi_count;
u64 max_dpi;
u64 cq_count;
u64 max_cq;
u64 qp_count;
u64 max_qp;
u64 tid_count;
u64 max_tid;
};
#define QED_ROCE_TX_HEAD_FAILURE (1)
#define QED_ROCE_TX_FRAG_FAILURE (2)
struct qed_roce_ll2_header {
void *vaddr;
dma_addr_t baddr;
size_t len;
};
struct qed_roce_ll2_buffer {
dma_addr_t baddr;
size_t len;
};
struct qed_roce_ll2_packet {
struct qed_roce_ll2_header header;
int n_seg;
struct qed_roce_ll2_buffer payload[RDMA_MAX_SGE_PER_SQ_WQE];
int roce_mode;
enum qed_roce_ll2_tx_dest tx_dest;
};
struct qed_roce_ll2_tx_params {
int reserved;
};
struct qed_roce_ll2_rx_params {
u16 vlan_id;
u8 smac[ETH_ALEN];
int rc;
};
struct qed_roce_ll2_cbs {
void (*tx_cb)(void *pdev, struct qed_roce_ll2_packet *pkt);
void (*rx_cb)(void *pdev, struct qed_roce_ll2_packet *pkt,
struct qed_roce_ll2_rx_params *params);
};
struct qed_roce_ll2_params {
u16 max_rx_buffers;
u16 max_tx_buffers;
u16 mtu;
u8 mac_address[ETH_ALEN];
struct qed_roce_ll2_cbs cbs;
void *cb_cookie;
};
struct qed_roce_ll2_info {
u8 handle;
struct qed_roce_ll2_cbs cbs;
u8 mac_address[ETH_ALEN];
void *cb_cookie;
/* Lock to protect ll2 */
struct mutex lock;
};
enum qed_rdma_type {
QED_RDMA_TYPE_ROCE,
};
struct qed_dev_rdma_info {
struct qed_dev_info common;
enum qed_rdma_type rdma_type;
};
struct qed_rdma_ops {
const struct qed_common_ops *common;
int (*fill_dev_info)(struct qed_dev *cdev,
struct qed_dev_rdma_info *info);
void *(*rdma_get_rdma_ctx)(struct qed_dev *cdev);
int (*rdma_init)(struct qed_dev *dev,
struct qed_rdma_start_in_params *iparams);
int (*rdma_add_user)(void *rdma_cxt,
struct qed_rdma_add_user_out_params *oparams);
void (*rdma_remove_user)(void *rdma_cxt, u16 dpi);
int (*rdma_stop)(void *rdma_cxt);
struct qed_rdma_device* (*rdma_query_device)(void *rdma_cxt);
struct qed_rdma_port* (*rdma_query_port)(void *rdma_cxt);
int (*rdma_get_start_sb)(struct qed_dev *cdev);
int (*rdma_get_min_cnq_msix)(struct qed_dev *cdev);
void (*rdma_cnq_prod_update)(void *rdma_cxt, u8 cnq_index, u16 prod);
int (*rdma_get_rdma_int)(struct qed_dev *cdev,
struct qed_int_info *info);
int (*rdma_set_rdma_int)(struct qed_dev *cdev, u16 cnt);
int (*rdma_alloc_pd)(void *rdma_cxt, u16 *pd);
void (*rdma_dealloc_pd)(void *rdma_cxt, u16 pd);
int (*rdma_create_cq)(void *rdma_cxt,
struct qed_rdma_create_cq_in_params *params,
u16 *icid);
int (*rdma_destroy_cq)(void *rdma_cxt,
struct qed_rdma_destroy_cq_in_params *iparams,
struct qed_rdma_destroy_cq_out_params *oparams);
struct qed_rdma_qp *
(*rdma_create_qp)(void *rdma_cxt,
struct qed_rdma_create_qp_in_params *iparams,
struct qed_rdma_create_qp_out_params *oparams);
int (*rdma_modify_qp)(void *roce_cxt, struct qed_rdma_qp *qp,
struct qed_rdma_modify_qp_in_params *iparams);
int (*rdma_query_qp)(void *rdma_cxt, struct qed_rdma_qp *qp,
struct qed_rdma_query_qp_out_params *oparams);
int (*rdma_destroy_qp)(void *rdma_cxt, struct qed_rdma_qp *qp);
int
(*rdma_register_tid)(void *rdma_cxt,
struct qed_rdma_register_tid_in_params *iparams);
int (*rdma_deregister_tid)(void *rdma_cxt, u32 itid);
int (*rdma_alloc_tid)(void *rdma_cxt, u32 *itid);
void (*rdma_free_tid)(void *rdma_cxt, u32 itid);
int (*roce_ll2_start)(struct qed_dev *cdev,
struct qed_roce_ll2_params *params);
int (*roce_ll2_stop)(struct qed_dev *cdev);
int (*roce_ll2_tx)(struct qed_dev *cdev,
struct qed_roce_ll2_packet *packet,
struct qed_roce_ll2_tx_params *params);
int (*roce_ll2_post_rx_buffer)(struct qed_dev *cdev,
struct qed_roce_ll2_buffer *buf,
u64 cookie, u8 notify_fw);
int (*roce_ll2_set_mac_filter)(struct qed_dev *cdev,
u8 *old_mac_address,
u8 *new_mac_address);
int (*roce_ll2_stats)(struct qed_dev *cdev,
struct qed_ll2_stats *stats);
};
const struct qed_rdma_ops *qed_get_rdma_ops(void);
#endif

88
include/linux/qed/qede_roce.h Normal file
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@ -0,0 +1,88 @@
/* QLogic qedr NIC Driver
* Copyright (c) 2015-2016 QLogic Corporation
*
* This software is available to you under a choice of one of two
* licenses. You may choose to be licensed under the terms of the GNU
* General Public License (GPL) Version 2, available from the file
* COPYING in the main directory of this source tree, or the
* OpenIB.org BSD license below:
*
* Redistribution and use in source and binary forms, with or
* without modification, are permitted provided that the following
* conditions are met:
*
* - Redistributions of source code must retain the above
* copyright notice, this list of conditions and the following
* disclaimer.
*
* - Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and /or other materials
* provided with the distribution.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#ifndef QEDE_ROCE_H
#define QEDE_ROCE_H
struct qedr_dev;
struct qed_dev;
struct qede_dev;
enum qede_roce_event {
QEDE_UP,
QEDE_DOWN,
QEDE_CHANGE_ADDR,
QEDE_CLOSE
};
struct qede_roce_event_work {
struct list_head list;
struct work_struct work;
void *ptr;
enum qede_roce_event event;
};
struct qedr_driver {
unsigned char name[32];
struct qedr_dev* (*add)(struct qed_dev *, struct pci_dev *,
struct net_device *);
void (*remove)(struct qedr_dev *);
void (*notify)(struct qedr_dev *, enum qede_roce_event);
};
/* APIs for RoCE driver to register callback handlers,
* which will be invoked when device is added, removed, ifup, ifdown
*/
int qede_roce_register_driver(struct qedr_driver *drv);
void qede_roce_unregister_driver(struct qedr_driver *drv);
bool qede_roce_supported(struct qede_dev *dev);
#if IS_ENABLED(CONFIG_INFINIBAND_QEDR)
int qede_roce_dev_add(struct qede_dev *dev);
void qede_roce_dev_event_open(struct qede_dev *dev);
void qede_roce_dev_event_close(struct qede_dev *dev);
void qede_roce_dev_remove(struct qede_dev *dev);
void qede_roce_event_changeaddr(struct qede_dev *qedr);
#else
static inline int qede_roce_dev_add(struct qede_dev *dev)
{
return 0;
}
static inline void qede_roce_dev_event_open(struct qede_dev *dev) {}
static inline void qede_roce_dev_event_close(struct qede_dev *dev) {}
static inline void qede_roce_dev_remove(struct qede_dev *dev) {}
static inline void qede_roce_event_changeaddr(struct qede_dev *qedr) {}
#endif
#endif

1
include/linux/qed/rdma_common.h
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@ -28,6 +28,7 @@
#define RDMA_MAX_PDS (64 * 1024)
#define RDMA_NUM_STATISTIC_COUNTERS MAX_NUM_VPORTS
#define RDMA_NUM_STATISTIC_COUNTERS_BB MAX_NUM_VPORTS_BB
#define RDMA_TASK_TYPE (PROTOCOLID_ROCE)