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i.MX DT bindings update for 5.2: 

- Add vendor prefix for TQ Systems GmbH, Rakuten Kobo and Menlo Systems
    GmbH.
  - Add DT schema for SoC i.MX8MM and i.MX50, and board ZII VF610, VF610
    SPB4, i.MX7 RPU2, i.MX7S TQ MBa7, M53 Menlo and Eckelmann ci4x10.
  - Update imx-scu bindings on resource table and general interrupt
    support.
  - Add bindings for i.MX MMDC memory controller.
  - Update i.MX7D ADC bindings to add missing '#io-channel-cells'
    property.
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Merge tag 'imx-bindings-5.2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt

i.MX DT bindings update for 5.2:
 - Add vendor prefix for TQ Systems GmbH, Rakuten Kobo and Menlo Systems
   GmbH.
 - Add DT schema for SoC i.MX8MM and i.MX50, and board ZII VF610, VF610
   SPB4, i.MX7 RPU2, i.MX7S TQ MBa7, M53 Menlo and Eckelmann ci4x10.
 - Update imx-scu bindings on resource table and general interrupt
   support.
 - Add bindings for i.MX MMDC memory controller.
 - Update i.MX7D ADC bindings to add missing '#io-channel-cells'
   property.

* tag 'imx-bindings-5.2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  dt-bindings: iio: imx7d-adc: Add #io-channel-cells to required
  dt-bindings: arm: fsl: Add support for ZII i.MX7 RPU2 board
  dt-bindings: arm: fsl: Add devicetree binding for M53 Menlo board.
  dt-bindings: fsl: scu: add general interrupt support
  dt-bindings: arm: fsl: Add i.MX50 based boards
  dt-bindings: Add vendor prefix for Rakuten Kobo, Inc.
  dt-bindings: arm: add TQ boards
  dt-bindings: add vendor prefix for TQ Systems GmbH
  dt-bindings: arm: fsl: Add support for ZII VF610 SPB4
  dt-bindings: arm: fsl: Add supported ZII VF610 boards to DT schema
  dt-bindings: arm: imx: Add the soc binding for imx8mm
  dt-bindings: arm: fsl: Add devicetree binding for Eckelmann ci4x10
  dt-bindings: memory-controllers: freescale: add MMDC binding doc
  of: Add vendor prefix for Menlo Systems GmbH
  bindings: fsl-imx-sdma: Document fsl,imx8mq-sdma compatbile string
  dt-bindings: firmware: imx-scu: add new resources to scu resource table
  dt-bindings: firmware: imx-scu: remove unused resources from scu resource table

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2019-04-28 12:50:38 -07:00
parent 1e67323721 e2c7f52bcd
commit b45da609a0
7 changed files with 108 additions and 23 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

29
Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt
View File

@ -22,9 +22,11 @@ Required properties:
------------------- -------------------
- compatible: should be "fsl,imx-scu". - compatible: should be "fsl,imx-scu".
- mbox-names: should include "tx0", "tx1", "tx2", "tx3", - mbox-names: should include "tx0", "tx1", "tx2", "tx3",
"rx0", "rx1", "rx2", "rx3". "rx0", "rx1", "rx2", "rx3";
- mboxes: List of phandle of 4 MU channels for tx and 4 MU channels include "gip3" if want to support general MU interrupt.
for rx. All 8 MU channels must be in the same MU instance. - mboxes: List of phandle of 4 MU channels for tx, 4 MU channels for
rx, and 1 optional MU channel for general interrupt.
All MU channels must be in the same MU instance.
Cross instances are not allowed. The MU instance can only Cross instances are not allowed. The MU instance can only
be one of LSIO MU0~M4 for imx8qxp and imx8qm. Users need be one of LSIO MU0~M4 for imx8qxp and imx8qm. Users need
to make sure use the one which is not conflict with other to make sure use the one which is not conflict with other
@ -34,6 +36,7 @@ Required properties:
Channel 1 must be "tx1" or "rx1". Channel 1 must be "tx1" or "rx1".
Channel 2 must be "tx2" or "rx2". Channel 2 must be "tx2" or "rx2".
Channel 3 must be "tx3" or "rx3". Channel 3 must be "tx3" or "rx3".
General interrupt rx channel must be "gip3".
e.g. e.g.
mboxes = <&lsio_mu1 0 0 mboxes = <&lsio_mu1 0 0
&lsio_mu1 0 1 &lsio_mu1 0 1
@ -42,10 +45,18 @@ Required properties:
&lsio_mu1 1 0 &lsio_mu1 1 0
&lsio_mu1 1 1 &lsio_mu1 1 1
&lsio_mu1 1 2 &lsio_mu1 1 2
&lsio_mu1 1 3>; &lsio_mu1 1 3
&lsio_mu1 3 3>;
See Documentation/devicetree/bindings/mailbox/fsl,mu.txt See Documentation/devicetree/bindings/mailbox/fsl,mu.txt
for detailed mailbox binding. for detailed mailbox binding.
Note: Each mu which supports general interrupt should have an alias correctly
numbered in "aliases" node.
e.g.
aliases {
mu1 = &lsio_mu1;
};
i.MX SCU Client Device Node: i.MX SCU Client Device Node:
============================================================ ============================================================
@ -124,6 +135,10 @@ Required properties:
Example (imx8qxp): Example (imx8qxp):
------------- -------------
aliases {
mu1 = &lsio_mu1;
};
lsio_mu1: mailbox@5d1c0000 { lsio_mu1: mailbox@5d1c0000 {
... ...
#mbox-cells = <2>; #mbox-cells = <2>;
@ -133,7 +148,8 @@ firmware {
scu { scu {
compatible = "fsl,imx-scu"; compatible = "fsl,imx-scu";
mbox-names = "tx0", "tx1", "tx2", "tx3", mbox-names = "tx0", "tx1", "tx2", "tx3",
"rx0", "rx1", "rx2", "rx3"; "rx0", "rx1", "rx2", "rx3",
"gip3";
mboxes = <&lsio_mu1 0 0 mboxes = <&lsio_mu1 0 0
&lsio_mu1 0 1 &lsio_mu1 0 1
&lsio_mu1 0 2 &lsio_mu1 0 2
@ -141,7 +157,8 @@ firmware {
&lsio_mu1 1 0 &lsio_mu1 1 0
&lsio_mu1 1 1 &lsio_mu1 1 1
&lsio_mu1 1 2 &lsio_mu1 1 2
&lsio_mu1 1 3>; &lsio_mu1 1 3
&lsio_mu1 3 3>;
clk: clk { clk: clk {
compatible = "fsl,imx8qxp-clk", "fsl,scu-clk"; compatible = "fsl,imx8qxp-clk", "fsl,scu-clk";

36
Documentation/devicetree/bindings/arm/fsl.yaml
View File

@ -51,6 +51,13 @@ properties:
- const: i2se,duckbill-2 - const: i2se,duckbill-2
- const: fsl,imx28 - const: fsl,imx28
- description: i.MX50 based Boards
items:
- enum:
- fsl,imx50-evk
- kobo,aura
- const: fsl,imx50
- description: i.MX51 Babbage Board - description: i.MX51 Babbage Board
items: items:
- enum: - enum:
@ -67,6 +74,7 @@ properties:
- fsl,imx53-evk - fsl,imx53-evk
- fsl,imx53-qsb - fsl,imx53-qsb
- fsl,imx53-smd - fsl,imx53-smd
- menlo,m53menlo
- const: fsl,imx53 - const: fsl,imx53
- description: i.MX6Q based Boards - description: i.MX6Q based Boards
@ -90,6 +98,7 @@ properties:
- description: i.MX6DL based Boards - description: i.MX6DL based Boards
items: items:
- enum: - enum:
- eckelmann,imx6dl-ci4x10
- fsl,imx6dl-sabreauto # i.MX6 DualLite/Solo SABRE Automotive Board - fsl,imx6dl-sabreauto # i.MX6 DualLite/Solo SABRE Automotive Board
- fsl,imx6dl-sabresd # i.MX6 DualLite SABRE Smart Device Board - fsl,imx6dl-sabresd # i.MX6 DualLite SABRE Smart Device Board
- technologic,imx6dl-ts4900 - technologic,imx6dl-ts4900
@ -137,10 +146,18 @@ properties:
- const: fsl,imx6ull # This seems odd. Should be last? - const: fsl,imx6ull # This seems odd. Should be last?
- const: fsl,imx6ulz - const: fsl,imx6ulz
- description: i.MX7S based Boards
items:
- enum:
- tq,imx7s-mba7 # i.MX7S TQ MBa7 with TQMa7S SoM
- const: fsl,imx7s
- description: i.MX7D based Boards - description: i.MX7D based Boards
items: items:
- enum: - enum:
- fsl,imx7d-sdb # i.MX7 SabreSD Board - fsl,imx7d-sdb # i.MX7 SabreSD Board
- tq,imx7d-mba7 # i.MX7D TQ MBa7 with TQMa7D SoM
- zii,imx7d-rpu2 # ZII RPU2 Board
- const: fsl,imx7d - const: fsl,imx7d
- description: - description:
@ -154,6 +171,12 @@ properties:
- const: compulab,cl-som-imx7 - const: compulab,cl-som-imx7
- const: fsl,imx7d - const: fsl,imx7d
- description: i.MX8MM based Boards
items:
- enum:
- fsl,imx8mm-evk # i.MX8MM EVK Board
- const: fsl,imx8mm
- description: i.MX8QXP based Boards - description: i.MX8QXP based Boards
items: items:
- enum: - enum:
@ -176,6 +199,19 @@ properties:
- fsl,vf610 - fsl,vf610
- fsl,vf610m4 - fsl,vf610m4
- description: ZII's VF610 based Boards
items:
- enum:
- zii,vf610cfu1 # ZII VF610 CFU1 Board
- zii,vf610dev-c # ZII VF610 Development Board, Rev C
- zii,vf610dev-b # ZII VF610 Development Board, Rev B
- zii,vf610scu4-aib # ZII VF610 SCU4 AIB
- zii,vf610dtu # ZII VF610 SSMB DTU Board
- zii,vf610spu3 # ZII VF610 SSMB SPU3 Board
- zii,vf610spb4 # ZII VF610 SPB4 Board
- const: zii,vf610dev
- const: fsl,vf610
- description: LS1012A based Boards - description: LS1012A based Boards
items: items:
- enum: - enum:

1
Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt
View File

@ -9,6 +9,7 @@ Required properties:
"fsl,imx53-sdma" "fsl,imx53-sdma"
"fsl,imx6q-sdma" "fsl,imx6q-sdma"
"fsl,imx7d-sdma" "fsl,imx7d-sdma"
"fsl,imx8mq-sdma"
The -to variants should be preferred since they allow to determine the The -to variants should be preferred since they allow to determine the
correct ROM script addresses needed for the driver to work without additional correct ROM script addresses needed for the driver to work without additional
firmware. firmware.

2
Documentation/devicetree/bindings/iio/adc/imx7d-adc.txt
View File

@ -10,6 +10,7 @@ Required properties:
- clocks: The root clock of the ADC controller - clocks: The root clock of the ADC controller
- clock-names: Must contain "adc", matching entry in the clocks property - clock-names: Must contain "adc", matching entry in the clocks property
- vref-supply: The regulator supply ADC reference voltage - vref-supply: The regulator supply ADC reference voltage
- #io-channel-cells: Must be 1 as per ../iio-bindings.txt
Example: Example:
adc1: adc@30610000 { adc1: adc@30610000 {
@ -19,4 +20,5 @@ adc1: adc@30610000 {
clocks = <&clks IMX7D_ADC_ROOT_CLK>; clocks = <&clks IMX7D_ADC_ROOT_CLK>;
clock-names = "adc"; clock-names = "adc";
vref-supply = <&reg_vcc_3v3_mcu>; vref-supply = <&reg_vcc_3v3_mcu>;
#io-channel-cells = <1>;
}; };

35
Documentation/devicetree/bindings/memory-controllers/fsl/mmdc.txt Normal file
View File

@ -0,0 +1,35 @@
Freescale Multi Mode DDR controller (MMDC)
Required properties :
- compatible : should be one of following:
for i.MX6Q/i.MX6DL:
- "fsl,imx6q-mmdc";
for i.MX6QP:
- "fsl,imx6qp-mmdc", "fsl,imx6q-mmdc";
for i.MX6SL:
- "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc";
for i.MX6SLL:
- "fsl,imx6sll-mmdc", "fsl,imx6q-mmdc";
for i.MX6SX:
- "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc";
for i.MX6UL/i.MX6ULL/i.MX6ULZ:
- "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc";
for i.MX7ULP:
- "fsl,imx7ulp-mmdc", "fsl,imx6q-mmdc";
- reg : address and size of MMDC DDR controller registers
Optional properties :
- clocks : the clock provided by the SoC to access the MMDC registers
Example :
mmdc0: memory-controller@21b0000 { /* MMDC0 */
compatible = "fsl,imx6q-mmdc";
reg = <0x021b0000 0x4000>;
clocks = <&clks IMX6QDL_CLK_MMDC_P0_IPG>;
};
mmdc1: memory-controller@21b4000 { /* MMDC1 */
compatible = "fsl,imx6q-mmdc";
reg = <0x021b4000 0x4000>;
status = "disabled";
};

3
Documentation/devicetree/bindings/vendor-prefixes.txt
View File

@ -211,6 +211,7 @@ kiebackpeter Kieback & Peter GmbH
kinetic Kinetic Technologies kinetic Kinetic Technologies
kingdisplay King & Display Technology Co., Ltd. kingdisplay King & Display Technology Co., Ltd.
kingnovel Kingnovel Technology Co., Ltd. kingnovel Kingnovel Technology Co., Ltd.
kobo Rakuten Kobo Inc.
koe Kaohsiung Opto-Electronics Inc. koe Kaohsiung Opto-Electronics Inc.
kosagi Sutajio Ko-Usagi PTE Ltd. kosagi Sutajio Ko-Usagi PTE Ltd.
kyo Kyocera Corporation kyo Kyocera Corporation
@ -245,6 +246,7 @@ melexis Melexis N.V.
melfas MELFAS Inc. melfas MELFAS Inc.
mellanox Mellanox Technologies mellanox Mellanox Technologies
memsic MEMSIC Inc. memsic MEMSIC Inc.
menlo Menlo Systems GmbH
merrii Merrii Technology Co., Ltd. merrii Merrii Technology Co., Ltd.
micrel Micrel Inc. micrel Micrel Inc.
microchip Microchip Technology Inc. microchip Microchip Technology Inc.
@ -419,6 +421,7 @@ toumaz Toumaz
tpk TPK U.S.A. LLC tpk TPK U.S.A. LLC
tplink TP-LINK Technologies Co., Ltd. tplink TP-LINK Technologies Co., Ltd.
tpo TPO tpo TPO
tq TQ Systems GmbH
tronfy Tronfy tronfy Tronfy
tronsmart Tronsmart tronsmart Tronsmart
truly Truly Semiconductors Limited truly Truly Semiconductors Limited

25
include/dt-bindings/firmware/imx/rsrc.h
View File

@ -36,15 +36,11 @@
#define IMX_SC_R_DC_0_BLIT1 20 #define IMX_SC_R_DC_0_BLIT1 20
#define IMX_SC_R_DC_0_BLIT2 21 #define IMX_SC_R_DC_0_BLIT2 21
#define IMX_SC_R_DC_0_BLIT_OUT 22 #define IMX_SC_R_DC_0_BLIT_OUT 22
#define IMX_SC_R_DC_0_CAPTURE0 23 #define IMX_SC_R_PERF 23
#define IMX_SC_R_DC_0_CAPTURE1 24
#define IMX_SC_R_DC_0_WARP 25 #define IMX_SC_R_DC_0_WARP 25
#define IMX_SC_R_DC_0_INTEGRAL0 26
#define IMX_SC_R_DC_0_INTEGRAL1 27
#define IMX_SC_R_DC_0_VIDEO0 28 #define IMX_SC_R_DC_0_VIDEO0 28
#define IMX_SC_R_DC_0_VIDEO1 29 #define IMX_SC_R_DC_0_VIDEO1 29
#define IMX_SC_R_DC_0_FRAC0 30 #define IMX_SC_R_DC_0_FRAC0 30
#define IMX_SC_R_DC_0_FRAC1 31
#define IMX_SC_R_DC_0 32 #define IMX_SC_R_DC_0 32
#define IMX_SC_R_GPU_2_PID0 33 #define IMX_SC_R_GPU_2_PID0 33
#define IMX_SC_R_DC_0_PLL_0 34 #define IMX_SC_R_DC_0_PLL_0 34
@ -53,17 +49,11 @@
#define IMX_SC_R_DC_1_BLIT1 37 #define IMX_SC_R_DC_1_BLIT1 37
#define IMX_SC_R_DC_1_BLIT2 38 #define IMX_SC_R_DC_1_BLIT2 38
#define IMX_SC_R_DC_1_BLIT_OUT 39 #define IMX_SC_R_DC_1_BLIT_OUT 39
#define IMX_SC_R_DC_1_CAPTURE0 40
#define IMX_SC_R_DC_1_CAPTURE1 41
#define IMX_SC_R_DC_1_WARP 42 #define IMX_SC_R_DC_1_WARP 42
#define IMX_SC_R_DC_1_INTEGRAL0 43
#define IMX_SC_R_DC_1_INTEGRAL1 44
#define IMX_SC_R_DC_1_VIDEO0 45 #define IMX_SC_R_DC_1_VIDEO0 45
#define IMX_SC_R_DC_1_VIDEO1 46 #define IMX_SC_R_DC_1_VIDEO1 46
#define IMX_SC_R_DC_1_FRAC0 47 #define IMX_SC_R_DC_1_FRAC0 47
#define IMX_SC_R_DC_1_FRAC1 48
#define IMX_SC_R_DC_1 49 #define IMX_SC_R_DC_1 49
#define IMX_SC_R_GPU_3_PID0 50
#define IMX_SC_R_DC_1_PLL_0 51 #define IMX_SC_R_DC_1_PLL_0 51
#define IMX_SC_R_DC_1_PLL_1 52 #define IMX_SC_R_DC_1_PLL_1 52
#define IMX_SC_R_SPI_0 53 #define IMX_SC_R_SPI_0 53
@ -303,8 +293,6 @@
#define IMX_SC_R_M4_0_UART 287 #define IMX_SC_R_M4_0_UART 287
#define IMX_SC_R_M4_0_I2C 288 #define IMX_SC_R_M4_0_I2C 288
#define IMX_SC_R_M4_0_INTMUX 289 #define IMX_SC_R_M4_0_INTMUX 289
#define IMX_SC_R_M4_0_SIM 290
#define IMX_SC_R_M4_0_WDOG 291
#define IMX_SC_R_M4_0_MU_0B 292 #define IMX_SC_R_M4_0_MU_0B 292
#define IMX_SC_R_M4_0_MU_0A0 293 #define IMX_SC_R_M4_0_MU_0A0 293
#define IMX_SC_R_M4_0_MU_0A1 294 #define IMX_SC_R_M4_0_MU_0A1 294
@ -323,8 +311,6 @@
#define IMX_SC_R_M4_1_UART 307 #define IMX_SC_R_M4_1_UART 307
#define IMX_SC_R_M4_1_I2C 308 #define IMX_SC_R_M4_1_I2C 308
#define IMX_SC_R_M4_1_INTMUX 309 #define IMX_SC_R_M4_1_INTMUX 309
#define IMX_SC_R_M4_1_SIM 310
#define IMX_SC_R_M4_1_WDOG 311
#define IMX_SC_R_M4_1_MU_0B 312 #define IMX_SC_R_M4_1_MU_0B 312
#define IMX_SC_R_M4_1_MU_0A0 313 #define IMX_SC_R_M4_1_MU_0A0 313
#define IMX_SC_R_M4_1_MU_0A1 314 #define IMX_SC_R_M4_1_MU_0A1 314
@ -337,7 +323,7 @@
#define IMX_SC_R_IRQSTR_SCU2 321 #define IMX_SC_R_IRQSTR_SCU2 321
#define IMX_SC_R_IRQSTR_DSP 322 #define IMX_SC_R_IRQSTR_DSP 322
#define IMX_SC_R_ELCDIF_PLL 323 #define IMX_SC_R_ELCDIF_PLL 323
#define IMX_SC_R_UNUSED6 324 #define IMX_SC_R_OCRAM 324
#define IMX_SC_R_AUDIO_PLL_0 325 #define IMX_SC_R_AUDIO_PLL_0 325
#define IMX_SC_R_PI_0 326 #define IMX_SC_R_PI_0 326
#define IMX_SC_R_PI_0_PWM_0 327 #define IMX_SC_R_PI_0_PWM_0 327
@ -554,6 +540,11 @@
#define IMX_SC_R_VPU_MU_3 538 #define IMX_SC_R_VPU_MU_3 538
#define IMX_SC_R_VPU_ENC_1 539 #define IMX_SC_R_VPU_ENC_1 539
#define IMX_SC_R_VPU 540 #define IMX_SC_R_VPU 540
#define IMX_SC_R_LAST 541 #define IMX_SC_R_DMA_5_CH0 541
#define IMX_SC_R_DMA_5_CH1 542
#define IMX_SC_R_DMA_5_CH2 543
#define IMX_SC_R_DMA_5_CH3 544
#define IMX_SC_R_ATTESTATION 545
#define IMX_SC_R_LAST 546
#endif /* __DT_BINDINGS_RSCRC_IMX_H */ #endif /* __DT_BINDINGS_RSCRC_IMX_H */