From 97b7ed07278436099a38da48ba6556e7cb25f57b Mon Sep 17 00:00:00 2001 From: Emil Renner Berthing Date: Tue, 20 Dec 2022 09:12:41 +0800 Subject: [PATCH 01/10] dt-bindings: riscv: Add StarFive JH7110 SoC and VisionFive 2 board Add device tree bindings for the StarFive JH7110 RISC-V SoC and the VisionFive 2 board equipped with it. VisionFive 2 board has version A and version B, which are different in gmac and phy chip. The version A board has one 1000Mbps and one 100Mbps Ethernet ports while the version B board has two 1000Mbps Ethernet ports. Link: https://doc-en.rvspace.org/Doc_Center/jh7110.html Link: https://doc-en.rvspace.org/Doc_Center/visionfive_2.html Signed-off-by: Emil Renner Berthing Signed-off-by: Hal Feng Acked-by: Krzysztof Kozlowski Signed-off-by: Conor Dooley --- Documentation/devicetree/bindings/riscv/starfive.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/starfive.yaml b/Documentation/devicetree/bindings/riscv/starfive.yaml index 5d3fcee52d59..60c7c03fcdce 100644 --- a/Documentation/devicetree/bindings/riscv/starfive.yaml +++ b/Documentation/devicetree/bindings/riscv/starfive.yaml @@ -24,6 +24,12 @@ properties: - starfive,visionfive-v1 - const: starfive,jh7100 + - items: + - enum: + - starfive,visionfive-2-va + - starfive,visionfive-2-vb + - const: starfive,jh7110 + additionalProperties: true ... From 444c3dbdabd468196bd55712863f7e125909008f Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Sun, 20 Nov 2022 20:59:41 +0000 Subject: [PATCH 02/10] RISC-V: introduce ARCH_FOO kconfig aliases for SOC_FOO symbols To facilitate a transfer from SOC_FOO to ARCH_FOO, over a release cycle, introduce some aliases so that drivers etc that use the SOC_FOO symbols can be converted. Signed-off-by: Conor Dooley --- To me, the most straight-forward conversion looks like so: - this patch is applied in week 2 of the merge window, to avoid any conflicts with the Renesas tree - all users of the SOC_ variants can be converted over a release cycle (or more) & no trees need to merge an immutable branch. - we convert defconfig etc over after all users are converted - doing it over at least one release cycle means that `make oldconfig` will keep people's configs working as they upgrade - any new SoC families added uses ARCH_FOO --- arch/riscv/Kconfig.socs | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 4b6deb2715f1..665f3455ab47 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -1,5 +1,8 @@ menu "SoC selection" +config ARCH_MICROCHIP_POLARFIRE + def_bool SOC_MICROCHIP_POLARFIRE + config SOC_MICROCHIP_POLARFIRE bool "Microchip PolarFire SoCs" select MCHP_CLK_MPFS @@ -11,6 +14,9 @@ config ARCH_RENESAS help This enables support for the RISC-V based Renesas SoCs. +config ARCH_SIFIVE + def_bool SOC_SIFIVE + config SOC_SIFIVE bool "SiFive SoCs" select SERIAL_SIFIVE if TTY @@ -21,6 +27,9 @@ config SOC_SIFIVE help This enables support for SiFive SoC platform hardware. +config ARCH_STARFIVE + def_bool SOC_STARFIVE + config SOC_STARFIVE bool "StarFive SoCs" select PINCTRL @@ -28,6 +37,9 @@ config SOC_STARFIVE help This enables support for StarFive SoC platform hardware. +config ARCH_VIRT + def_bool SOC_VIRT + config SOC_VIRT bool "QEMU Virt Machine" select CLINT_TIMER if RISCV_M_MODE @@ -42,6 +54,9 @@ config SOC_VIRT help This enables support for QEMU Virt Machine. +config ARCH_CANAAN + def_bool SOC_CANAAN + config SOC_CANAAN bool "Canaan Kendryte K210 SoC" depends on !MMU @@ -57,6 +72,9 @@ config SOC_CANAAN if SOC_CANAAN +config ARCH_CANAAN_K210_DTB_BUILTIN + def_bool SOC_CANAAN_K210_DTB_BUILTIN + config SOC_CANAAN_K210_DTB_BUILTIN bool "Builtin device tree for the Canaan Kendryte K210" depends on SOC_CANAAN @@ -68,6 +86,9 @@ config SOC_CANAAN_K210_DTB_BUILTIN This option should be selected if no bootloader is being used. If unsure, say Y. +config ARCH_CANAAN_K210_DTB_SOURCE + def_bool SOC_CANAAN_K210_DTB_SOURCE + config SOC_CANAAN_K210_DTB_SOURCE string "Source file for the Canaan Kendryte K210 builtin DTB" depends on SOC_CANAAN From fc43211939bb68741d609cd6e7034f01d5d1734b Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Sun, 20 Nov 2022 21:17:06 +0000 Subject: [PATCH 03/10] RISC-V: kconfig.socs: convert usage of SOC_CANAAN to ARCH_CANAAN While we cannot yet drop the SOC_ prefixed symbols, we can convert uses of these symbols within Kconfig.socs to the ARCH_ variants. Signed-off-by: Conor Dooley --- arch/riscv/Kconfig.socs | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 665f3455ab47..ce920f627f6d 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -70,14 +70,14 @@ config SOC_CANAAN help This enables support for Canaan Kendryte K210 SoC platform hardware. -if SOC_CANAAN +if ARCH_CANAAN config ARCH_CANAAN_K210_DTB_BUILTIN def_bool SOC_CANAAN_K210_DTB_BUILTIN config SOC_CANAAN_K210_DTB_BUILTIN bool "Builtin device tree for the Canaan Kendryte K210" - depends on SOC_CANAAN + depends on ARCH_CANAAN default y select OF select BUILTIN_DTB @@ -91,14 +91,14 @@ config ARCH_CANAAN_K210_DTB_SOURCE config SOC_CANAAN_K210_DTB_SOURCE string "Source file for the Canaan Kendryte K210 builtin DTB" - depends on SOC_CANAAN - depends on SOC_CANAAN_K210_DTB_BUILTIN + depends on ARCH_CANAAN + depends on ARCH_CANAAN_K210_DTB_BUILTIN default "k210_generic" help Base name (without suffix, relative to arch/riscv/boot/dts/canaan) for the DTS file that will be used to produce the DTB linked into the kernel. -endif # SOC_CANAAN +endif # ARCH_CANAAN endmenu # "SoC selection" From 19ba9cf70706629709a3304aa977d1dddcfadf43 Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Sun, 20 Nov 2022 21:34:44 +0000 Subject: [PATCH 04/10] RISC-V: kbuild: convert all use of SOC_FOO to ARCH_FOO Convert all non user visible use of SOC_FOO symbols to their ARCH_FOO variants. The canaan DTs are an outlier in that they're gated at the directory and the file level. Drop the directory level gating while we are swapping the symbol names over. Signed-off-by: Conor Dooley --- arch/riscv/Makefile | 2 +- arch/riscv/boot/dts/Makefile | 2 +- arch/riscv/boot/dts/canaan/Makefile | 14 +++++++------- arch/riscv/boot/dts/microchip/Makefile | 8 ++++---- arch/riscv/boot/dts/sifive/Makefile | 4 ++-- arch/riscv/boot/dts/starfive/Makefile | 2 +- 6 files changed, 16 insertions(+), 16 deletions(-) diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index faf2c2177094..12d91b0a73d8 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -131,7 +131,7 @@ endif endif ifneq ($(CONFIG_XIP_KERNEL),y) -ifeq ($(CONFIG_RISCV_M_MODE)$(CONFIG_SOC_CANAAN),yy) +ifeq ($(CONFIG_RISCV_M_MODE)$(CONFIG_ARCH_CANAAN),yy) KBUILD_IMAGE := $(boot)/loader.bin else ifeq ($(CONFIG_EFI_ZBOOT),) diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile index b0ff5fbabb0c..0c97d673b775 100644 --- a/arch/riscv/boot/dts/Makefile +++ b/arch/riscv/boot/dts/Makefile @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 subdir-y += sifive subdir-y += starfive -subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan +subdir-y += canaan subdir-y += microchip subdir-y += renesas diff --git a/arch/riscv/boot/dts/canaan/Makefile b/arch/riscv/boot/dts/canaan/Makefile index befe4eb7527b..520623264c87 100644 --- a/arch/riscv/boot/dts/canaan/Makefile +++ b/arch/riscv/boot/dts/canaan/Makefile @@ -1,9 +1,9 @@ # SPDX-License-Identifier: GPL-2.0 -dtb-$(CONFIG_SOC_CANAAN) += canaan_kd233.dtb -dtb-$(CONFIG_SOC_CANAAN) += k210_generic.dtb -dtb-$(CONFIG_SOC_CANAAN) += sipeed_maix_bit.dtb -dtb-$(CONFIG_SOC_CANAAN) += sipeed_maix_dock.dtb -dtb-$(CONFIG_SOC_CANAAN) += sipeed_maix_go.dtb -dtb-$(CONFIG_SOC_CANAAN) += sipeed_maixduino.dtb +dtb-$(CONFIG_ARCH_CANAAN) += canaan_kd233.dtb +dtb-$(CONFIG_ARCH_CANAAN) += k210_generic.dtb +dtb-$(CONFIG_ARCH_CANAAN) += sipeed_maix_bit.dtb +dtb-$(CONFIG_ARCH_CANAAN) += sipeed_maix_dock.dtb +dtb-$(CONFIG_ARCH_CANAAN) += sipeed_maix_go.dtb +dtb-$(CONFIG_ARCH_CANAAN) += sipeed_maixduino.dtb -obj-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += $(addsuffix .dtb.o, $(CONFIG_SOC_CANAAN_K210_DTB_SOURCE)) +obj-$(CONFIG_ARCH_CANAAN_K210_DTB_BUILTIN) += $(addsuffix .dtb.o, $(CONFIG_ARCH_CANAAN_K210_DTB_SOURCE)) diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/microchip/Makefile index 7427a20934f3..259c3c802cab 100644 --- a/arch/riscv/boot/dts/microchip/Makefile +++ b/arch/riscv/boot/dts/microchip/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 -dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-icicle-kit.dtb -dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-m100pfsevp.dtb -dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-polarberry.dtb -dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-sev-kit.dtb +dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-icicle-kit.dtb +dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-m100pfsevp.dtb +dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-polarberry.dtb +dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-sev-kit.dtb obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y)) diff --git a/arch/riscv/boot/dts/sifive/Makefile b/arch/riscv/boot/dts/sifive/Makefile index d90e4eb0ade8..6a5fbd4ed96a 100644 --- a/arch/riscv/boot/dts/sifive/Makefile +++ b/arch/riscv/boot/dts/sifive/Makefile @@ -1,4 +1,4 @@ # SPDX-License-Identifier: GPL-2.0 -dtb-$(CONFIG_SOC_SIFIVE) += hifive-unleashed-a00.dtb \ - hifive-unmatched-a00.dtb +dtb-$(CONFIG_ARCH_SIFIVE) += hifive-unleashed-a00.dtb \ + hifive-unmatched-a00.dtb obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y)) diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile index 039c143cba33..7b00a48580ca 100644 --- a/arch/riscv/boot/dts/starfive/Makefile +++ b/arch/riscv/boot/dts/starfive/Makefile @@ -1,2 +1,2 @@ # SPDX-License-Identifier: GPL-2.0 -dtb-$(CONFIG_SOC_STARFIVE) += jh7100-beaglev-starlight.dtb jh7100-starfive-visionfive-v1.dtb +dtb-$(CONFIG_ARCH_STARFIVE) += jh7100-beaglev-starlight.dtb jh7100-starfive-visionfive-v1.dtb From b61032557d20d2d1036bfcf833a3c5b4799183ea Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Wed, 5 Oct 2022 18:13:47 +0100 Subject: [PATCH 05/10] RISC-V: stop selecting the PolarFire SoC clock driver The driver is now enabled by default if SOC_MICROCHIP_POLARFIRE so there is no longer a need to select it in Kconfig.socs Signed-off-by: Conor Dooley --- arch/riscv/Kconfig.socs | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index ce920f627f6d..aca5e750772c 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -5,7 +5,6 @@ config ARCH_MICROCHIP_POLARFIRE config SOC_MICROCHIP_POLARFIRE bool "Microchip PolarFire SoCs" - select MCHP_CLK_MPFS help This enables support for Microchip PolarFire SoC platforms. From 0e6aee5bcc0067d5f8a36cbb2dbd8b2702140481 Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Wed, 5 Oct 2022 18:13:48 +0100 Subject: [PATCH 06/10] RISC-V: stop selecting SiFive clock and serial drivers directly The SiFive clock and serial drivers will now default to the value of SOC_SIFIVE so there is no need to directly select their symbols anymore. Signed-off-by: Conor Dooley --- arch/riscv/Kconfig.socs | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index aca5e750772c..b90af1e22bc0 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -18,10 +18,6 @@ config ARCH_SIFIVE config SOC_SIFIVE bool "SiFive SoCs" - select SERIAL_SIFIVE if TTY - select SERIAL_SIFIVE_CONSOLE if TTY - select CLK_SIFIVE - select CLK_SIFIVE_PRCI select ERRATA_SIFIVE if !XIP_KERNEL help This enables support for SiFive SoC platform hardware. From 3af577f9826fdddefac42b35fc5eb3912c5b7d85 Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Wed, 5 Oct 2022 18:13:49 +0100 Subject: [PATCH 07/10] RISC-V: stop directly selecting drivers for SOC_CANAAN The serial and clock drivers will be enabled by default if the symbol itself is enabled, so stop directly selecting the drivers in Kconfigs.socs. Signed-off-by: Conor Dooley --- arch/riscv/Kconfig.socs | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index b90af1e22bc0..34a54e5310a1 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -56,12 +56,9 @@ config SOC_CANAAN bool "Canaan Kendryte K210 SoC" depends on !MMU select CLINT_TIMER if RISCV_M_MODE - select SERIAL_SIFIVE if TTY - select SERIAL_SIFIVE_CONSOLE if TTY select ARCH_HAS_RESET_CONTROLLER select PINCTRL select COMMON_CLK - select COMMON_CLK_K210 help This enables support for Canaan Kendryte K210 SoC platform hardware. From f6beee9118c30c10704e5a20752b2221bce26fc4 Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Wed, 11 Jan 2023 12:41:05 +0000 Subject: [PATCH 08/10] dt-bindings: vendor-prefixes: Add entry for Aldec Per their website: Aldec, Inc. is an industry-leading Electronic Design Automation (EDA) company delivering innovative design creation, simulation and verification solutions to assist in the development of complex FPGA, ASIC, SoC and embedded system designs. Link: https://www.aldec.com/ Acked-by: Krzysztof Kozlowski Signed-off-by: Conor Dooley --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 70ffb3780621..d119e9a7c287 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -69,6 +69,8 @@ patternProperties: description: Annapurna Labs "^alcatel,.*": description: Alcatel + "^aldec,.*": + description: Aldec, Inc. "^alfa-network,.*": description: ALFA Network Inc. "^allegro,.*": From ea913d8865fe51b799f225c46e75e3f6337b5e11 Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Wed, 11 Jan 2023 12:41:06 +0000 Subject: [PATCH 09/10] dt-bindings: riscv: microchip: document the Aldec TySoM The TySOM-M-MPFS250 is a compact SoC prototyping board featuring a Microchip PolarFire SoC MPFS250T-FCG1152. Document rev2 of this board. Link: https://www.aldec.com/en/products/emulation/tysom_boards/polarfire_microchip/tysom_m_mpfs250 Acked-by: Krzysztof Kozlowski Signed-off-by: Conor Dooley --- Documentation/devicetree/bindings/riscv/microchip.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/riscv/microchip.yaml b/Documentation/devicetree/bindings/riscv/microchip.yaml index 714d0fcab399..4a29c890619a 100644 --- a/Documentation/devicetree/bindings/riscv/microchip.yaml +++ b/Documentation/devicetree/bindings/riscv/microchip.yaml @@ -27,6 +27,7 @@ properties: - items: - enum: + - aldec,tysom-m-mpfs250t-rev2 - aries,m100pfsevp - microchip,mpfs-sev-kit - sundance,polarberry From 497e6b37b0099dc415578488287fd84fb74433eb Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Wed, 11 Jan 2023 12:41:07 +0000 Subject: [PATCH 10/10] riscv: dts: microchip: add the Aldec TySoM's devicetree The TySOM-M-MPFS250 is a compact SoC prototyping board featuring a Microchip PolarFire SoC MPFS250T-FCG1152. Features include: - 16 Gib FPGA DDR4 - 16 Gib MSS DDR4 with ECC - eMMC - SPI flash memory - 2x Ethernet 10/100/1000 - USB 2.0 - PCIe x4 Gen2 - HDMI OUT - 2x FMC connector (HPC and LPC) Specifically flag this board as rev2, in case later boards have an FPGA design revision with more features available in the future. Link: https://www.aldec.com/en/products/emulation/tysom_boards/polarfire_microchip/tysom_m_mpfs250 [Fixed a mistake where I read 16 Gib as 16 GiB!] Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/Makefile | 1 + .../dts/microchip/mpfs-tysom-m-fabric.dtsi | 18 ++ .../riscv/boot/dts/microchip/mpfs-tysom-m.dts | 165 ++++++++++++++++++ 3 files changed, 184 insertions(+) create mode 100644 arch/riscv/boot/dts/microchip/mpfs-tysom-m-fabric.dtsi create mode 100644 arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/microchip/Makefile index 7427a20934f3..c54922a325fd 100644 --- a/arch/riscv/boot/dts/microchip/Makefile +++ b/arch/riscv/boot/dts/microchip/Makefile @@ -3,4 +3,5 @@ dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-icicle-kit.dtb dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-m100pfsevp.dtb dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-polarberry.dtb dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-sev-kit.dtb +dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-tysom-m.dtb obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y)) diff --git a/arch/riscv/boot/dts/microchip/mpfs-tysom-m-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-tysom-m-fabric.dtsi new file mode 100644 index 000000000000..98f642e83ad4 --- /dev/null +++ b/arch/riscv/boot/dts/microchip/mpfs-tysom-m-fabric.dtsi @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2022 Microchip Technology Inc */ + +// #include "dt-bindings/mailbox/miv-ihc.h" + +/ { + fabric_clk3: fabric-clk3 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <62500000>; + }; + + fabric_clk1: fabric-clk1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; +}; diff --git a/arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts b/arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts new file mode 100644 index 000000000000..e0797c7e1b35 --- /dev/null +++ b/arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts @@ -0,0 +1,165 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Original all-in-one devicetree: + * Copyright (C) 2020-2022 - Aldec + * Rewritten to use includes: + * Copyright (C) 2022 - Conor Dooley + */ + +/dts-v1/; + +#include "mpfs.dtsi" +#include "mpfs-tysom-m-fabric.dtsi" + +/* Clock frequency (in Hz) of the rtcclk */ +#define MTIMER_FREQ 1000000 + +/ { + model = "Aldec TySOM-M-MPFS250T-REV2"; + compatible = "aldec,tysom-m-mpfs250t-rev2", "microchip,mpfs"; + + aliases { + ethernet0 = &mac0; + ethernet1 = &mac1; + serial0 = &mmuart0; + serial1 = &mmuart1; + serial2 = &mmuart2; + serial3 = &mmuart3; + serial4 = &mmuart4; + gpio0 = &gpio0; + gpio1 = &gpio2; + }; + + chosen { + stdout-path = "serial1:115200n8"; + }; + + cpus { + timebase-frequency = ; + }; + + ddrc_cache_lo: memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x30000000>; + status = "okay"; + }; + + ddrc_cache_hi: memory@1000000000 { + device_type = "memory"; + reg = <0x10 0x00000000 0x0 0x40000000>; + status = "okay"; + }; + + leds { + compatible = "gpio-leds"; + status = "okay"; + + led0 { + gpios = <&gpio1 23 1>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + hwmon: hwmon@45 { + status = "okay"; + compatible = "ti,ina219"; + reg = <0x45>; + shunt-resistor = <2000>; + }; +}; + +&gpio1 { + interrupts = <27>, <28>, <29>, <30>, + <31>, <32>, <33>, <47>, + <35>, <36>, <37>, <38>, + <39>, <40>, <41>, <42>, + <43>, <44>, <45>, <46>, + <47>, <48>, <49>, <50>; + status = "okay"; +}; + +&mac0 { + status = "okay"; + phy-mode = "gmii"; + phy-handle = <&phy0>; + +}; + +&mac1 { + status = "okay"; + phy-mode = "gmii"; + phy-handle = <&phy1>; + phy1: ethernet-phy@1 { + reg = <1>; + }; + phy0: ethernet-phy@0 { + reg = <0>; + }; +}; + +&mbox { + status = "okay"; +}; + +&mmc { + max-frequency = <200000000>; + cap-mmc-highspeed; + cap-sd-highspeed; + no-1-8-v; + disable-wp; + status = "okay"; +}; + +&mmuart1 { + status = "okay"; +}; + +&mmuart2 { + status = "okay"; +}; + +&mmuart3 { + status = "okay"; +}; + +&mmuart4 { + status = "okay"; +}; + +&refclk { + clock-frequency = <125000000>; +}; + +&rtc { + status = "okay"; +}; + +&spi0 { + status = "okay"; +}; + +&spi1 { + status = "okay"; + flash@0 { + compatible = "micron,n25q128a11", "jedec,spi-nor"; + reg = <0x0>; + spi-max-frequency = <10000000>; + }; +}; + +&syscontroller { + status = "okay"; +}; + +&usb { + status = "okay"; + dr_mode = "host"; +};