RISC-V Devicetrees for v6.3-mw0
Microchip: A vendor prefix for Aldec and both a binding and Devicetree for the Aldec TySoM devkit for PolarFire SoC. This Devicetree corresponds to what they are shipping in the SDK for rev2 boards. StarFive: Just the binding for the new StarFive JH7110 SoC and its first-party SDC the VisionFive 2. Other: I was expecting the Devicetree for the aforementioned board to be ready for this window, as the pinctrl driver had seem some review prior to v6.2 and both it & the base clock drivers are heavily based on the existing drivers for the JH7110. That didn't come to be.. Christmas, the RISC-V Summit in December and the Lunar New Year all playing a part perhaps. Because of that, both Palmer and I have the Kconfig.socs work in our branches, although in hindsight it probably wasn't needed here as I only added the TySoM Devicetree & the conflict would've been trivial. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCY9EPgwAKCRB4tDGHoIJi 0l9kAQDJHyrjfXMooRHSFXRUsJFYeN8MpYvD1CLavdrD+Pu+KQD/c1sApjfZrKjo ItyEL37F2QJOAFY1rAxdB7d6ppsUEAQ= =sN4y -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmPX9PcACgkQmmx57+YA GNn4Xg/+MykVFbZuQZbFuzD9DNA3BnHJuJL+5Uz1Ywy9H+Katl4hQGRLlt4WtRzC fWuteoPmNwvsbxuDRQ3sDC2oqRFVFD45u/q7qQ4ce+dKDbL2qpnbgxdmXVXdJrgL e9Wb9V01j8vLimNvFspicnaajFwDEC1uGLbVaZ+RKEk6GxxlJEJqydUsa2FVbQIf QDMEtR967fI3CUZ2wvzplJDDGBBKZbXxuZ/tOaTwEGPKFxbzQ5CBP7CFkbfEEjTZ kbcHsfLloKLL1/11oBeR6aPhY1WQvecBHO9WZ3ANR+/+2GT9SLdPbCWQN+uWM9ZI B5/SvtvJhzyP6HG+ErX/Pc8NPjm6AKMoo6j8fLuy8pASJF+H3tV9bn9mj4ld6B1S Vz8D1/hoh7OIuEaRDdfzW8xHQS6qQF58MRS3J8+I3xTUs4ZP6JifnOdIcrbXYvup +SFRgtoewV4wMxPshM+5FsVqsE4xSnvdwZeuxIjqpFY/CvlubFJdT9FBx8tx+v+G rC7MtoggznsQi1BDShGbu0xNAmE6iJcv9mranFm6NQUXC5/1SObIA9RFb0aBBJoQ DsU1rDqWndh9bILZkoikpPQ0uZWwAOFRpp44CSZ6/YtYPDku99YWozxqCeGGw4gN V18SjBXgL9YZfQKH3Z0biOdv6m2vLJKoj5hxgzu0KFxbCFlrl+A= =SCZP -----END PGP SIGNATURE----- Merge tag 'riscv-dt-for-v6.3-mw0' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into arm/dt RISC-V Devicetrees for v6.3-mw0 Microchip: A vendor prefix for Aldec and both a binding and Devicetree for the Aldec TySoM devkit for PolarFire SoC. This Devicetree corresponds to what they are shipping in the SDK for rev2 boards. StarFive: Just the binding for the new StarFive JH7110 SoC and its first-party SDC the VisionFive 2. Other: I was expecting the Devicetree for the aforementioned board to be ready for this window, as the pinctrl driver had seem some review prior to v6.2 and both it & the base clock drivers are heavily based on the existing drivers for the JH7110. That didn't come to be.. Christmas, the RISC-V Summit in December and the Lunar New Year all playing a part perhaps. Because of that, both Palmer and I have the Kconfig.socs work in our branches, although in hindsight it probably wasn't needed here as I only added the TySoM Devicetree & the conflict would've been trivial. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> * tag 'riscv-dt-for-v6.3-mw0' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux: riscv: dts: microchip: add the Aldec TySoM's devicetree dt-bindings: riscv: microchip: document the Aldec TySoM dt-bindings: vendor-prefixes: Add entry for Aldec RISC-V: stop directly selecting drivers for SOC_CANAAN RISC-V: stop selecting SiFive clock and serial drivers directly RISC-V: stop selecting the PolarFire SoC clock driver RISC-V: kbuild: convert all use of SOC_FOO to ARCH_FOO RISC-V: kconfig.socs: convert usage of SOC_CANAAN to ARCH_CANAAN RISC-V: introduce ARCH_FOO kconfig aliases for SOC_FOO symbols dt-bindings: riscv: Add StarFive JH7110 SoC and VisionFive 2 board Link: https://lore.kernel.org/r/Y9LP+Za1h0fkBa58@spud Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
b453988c59
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@ -27,6 +27,7 @@ properties:
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- items:
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- enum:
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- aldec,tysom-m-mpfs250t-rev2
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- aries,m100pfsevp
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- microchip,mpfs-sev-kit
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- sundance,polarberry
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|
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@ -24,6 +24,12 @@ properties:
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- starfive,visionfive-v1
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- const: starfive,jh7100
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- items:
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- enum:
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- starfive,visionfive-2-va
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- starfive,visionfive-2-vb
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- const: starfive,jh7110
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additionalProperties: true
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...
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@ -69,6 +69,8 @@ patternProperties:
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description: Annapurna Labs
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"^alcatel,.*":
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description: Alcatel
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"^aldec,.*":
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description: Aldec, Inc.
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"^alfa-network,.*":
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description: ALFA Network Inc.
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"^allegro,.*":
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@ -1,8 +1,10 @@
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menu "SoC selection"
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config ARCH_MICROCHIP_POLARFIRE
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def_bool SOC_MICROCHIP_POLARFIRE
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config SOC_MICROCHIP_POLARFIRE
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bool "Microchip PolarFire SoCs"
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select MCHP_CLK_MPFS
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help
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This enables support for Microchip PolarFire SoC platforms.
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@ -11,16 +13,18 @@ config ARCH_RENESAS
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help
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This enables support for the RISC-V based Renesas SoCs.
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config ARCH_SIFIVE
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def_bool SOC_SIFIVE
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config SOC_SIFIVE
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bool "SiFive SoCs"
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select SERIAL_SIFIVE if TTY
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select SERIAL_SIFIVE_CONSOLE if TTY
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select CLK_SIFIVE
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select CLK_SIFIVE_PRCI
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select ERRATA_SIFIVE if !XIP_KERNEL
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help
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This enables support for SiFive SoC platform hardware.
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config ARCH_STARFIVE
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def_bool SOC_STARFIVE
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config SOC_STARFIVE
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bool "StarFive SoCs"
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select PINCTRL
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@ -28,6 +32,9 @@ config SOC_STARFIVE
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help
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This enables support for StarFive SoC platform hardware.
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config ARCH_VIRT
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def_bool SOC_VIRT
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config SOC_VIRT
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bool "QEMU Virt Machine"
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select CLINT_TIMER if RISCV_M_MODE
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@ -42,24 +49,27 @@ config SOC_VIRT
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help
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This enables support for QEMU Virt Machine.
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config ARCH_CANAAN
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def_bool SOC_CANAAN
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config SOC_CANAAN
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bool "Canaan Kendryte K210 SoC"
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depends on !MMU
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select CLINT_TIMER if RISCV_M_MODE
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select SERIAL_SIFIVE if TTY
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select SERIAL_SIFIVE_CONSOLE if TTY
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select ARCH_HAS_RESET_CONTROLLER
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select PINCTRL
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select COMMON_CLK
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select COMMON_CLK_K210
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help
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This enables support for Canaan Kendryte K210 SoC platform hardware.
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if SOC_CANAAN
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if ARCH_CANAAN
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config ARCH_CANAAN_K210_DTB_BUILTIN
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def_bool SOC_CANAAN_K210_DTB_BUILTIN
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config SOC_CANAAN_K210_DTB_BUILTIN
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bool "Builtin device tree for the Canaan Kendryte K210"
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depends on SOC_CANAAN
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depends on ARCH_CANAAN
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default y
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select OF
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select BUILTIN_DTB
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@ -68,16 +78,19 @@ config SOC_CANAAN_K210_DTB_BUILTIN
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This option should be selected if no bootloader is being used.
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If unsure, say Y.
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config ARCH_CANAAN_K210_DTB_SOURCE
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def_bool SOC_CANAAN_K210_DTB_SOURCE
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config SOC_CANAAN_K210_DTB_SOURCE
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string "Source file for the Canaan Kendryte K210 builtin DTB"
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depends on SOC_CANAAN
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depends on SOC_CANAAN_K210_DTB_BUILTIN
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depends on ARCH_CANAAN
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depends on ARCH_CANAAN_K210_DTB_BUILTIN
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default "k210_generic"
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help
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Base name (without suffix, relative to arch/riscv/boot/dts/canaan)
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for the DTS file that will be used to produce the DTB linked into the
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kernel.
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endif # SOC_CANAAN
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endif # ARCH_CANAAN
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endmenu # "SoC selection"
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|
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@ -131,7 +131,7 @@ endif
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endif
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ifneq ($(CONFIG_XIP_KERNEL),y)
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ifeq ($(CONFIG_RISCV_M_MODE)$(CONFIG_SOC_CANAAN),yy)
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ifeq ($(CONFIG_RISCV_M_MODE)$(CONFIG_ARCH_CANAAN),yy)
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KBUILD_IMAGE := $(boot)/loader.bin
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else
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ifeq ($(CONFIG_EFI_ZBOOT),)
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@ -1,7 +1,7 @@
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# SPDX-License-Identifier: GPL-2.0
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subdir-y += sifive
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subdir-y += starfive
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subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan
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subdir-y += canaan
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subdir-y += microchip
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subdir-y += renesas
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@ -1,9 +1,9 @@
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# SPDX-License-Identifier: GPL-2.0
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dtb-$(CONFIG_SOC_CANAAN) += canaan_kd233.dtb
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dtb-$(CONFIG_SOC_CANAAN) += k210_generic.dtb
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dtb-$(CONFIG_SOC_CANAAN) += sipeed_maix_bit.dtb
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dtb-$(CONFIG_SOC_CANAAN) += sipeed_maix_dock.dtb
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dtb-$(CONFIG_SOC_CANAAN) += sipeed_maix_go.dtb
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dtb-$(CONFIG_SOC_CANAAN) += sipeed_maixduino.dtb
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dtb-$(CONFIG_ARCH_CANAAN) += canaan_kd233.dtb
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dtb-$(CONFIG_ARCH_CANAAN) += k210_generic.dtb
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dtb-$(CONFIG_ARCH_CANAAN) += sipeed_maix_bit.dtb
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dtb-$(CONFIG_ARCH_CANAAN) += sipeed_maix_dock.dtb
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dtb-$(CONFIG_ARCH_CANAAN) += sipeed_maix_go.dtb
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dtb-$(CONFIG_ARCH_CANAAN) += sipeed_maixduino.dtb
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obj-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += $(addsuffix .dtb.o, $(CONFIG_SOC_CANAAN_K210_DTB_SOURCE))
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obj-$(CONFIG_ARCH_CANAAN_K210_DTB_BUILTIN) += $(addsuffix .dtb.o, $(CONFIG_ARCH_CANAAN_K210_DTB_SOURCE))
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@ -1,6 +1,7 @@
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# SPDX-License-Identifier: GPL-2.0
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dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-icicle-kit.dtb
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dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-m100pfsevp.dtb
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dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-polarberry.dtb
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dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-sev-kit.dtb
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dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-icicle-kit.dtb
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dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-m100pfsevp.dtb
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dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-polarberry.dtb
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dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-sev-kit.dtb
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dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-tysom-m.dtb
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obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))
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@ -0,0 +1,18 @@
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/* Copyright (c) 2022 Microchip Technology Inc */
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// #include "dt-bindings/mailbox/miv-ihc.h"
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/ {
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fabric_clk3: fabric-clk3 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <62500000>;
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};
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fabric_clk1: fabric-clk1 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <125000000>;
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};
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};
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@ -0,0 +1,165 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Original all-in-one devicetree:
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* Copyright (C) 2020-2022 - Aldec
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* Rewritten to use includes:
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* Copyright (C) 2022 - Conor Dooley <conor.dooley@microchip.com>
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*/
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/dts-v1/;
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#include "mpfs.dtsi"
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#include "mpfs-tysom-m-fabric.dtsi"
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/* Clock frequency (in Hz) of the rtcclk */
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#define MTIMER_FREQ 1000000
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/ {
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model = "Aldec TySOM-M-MPFS250T-REV2";
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compatible = "aldec,tysom-m-mpfs250t-rev2", "microchip,mpfs";
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aliases {
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ethernet0 = &mac0;
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ethernet1 = &mac1;
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serial0 = &mmuart0;
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serial1 = &mmuart1;
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serial2 = &mmuart2;
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serial3 = &mmuart3;
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serial4 = &mmuart4;
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gpio0 = &gpio0;
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gpio1 = &gpio2;
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};
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chosen {
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stdout-path = "serial1:115200n8";
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};
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cpus {
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timebase-frequency = <MTIMER_FREQ>;
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};
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ddrc_cache_lo: memory@80000000 {
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device_type = "memory";
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reg = <0x0 0x80000000 0x0 0x30000000>;
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status = "okay";
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};
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ddrc_cache_hi: memory@1000000000 {
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device_type = "memory";
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reg = <0x10 0x00000000 0x0 0x40000000>;
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status = "okay";
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};
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leds {
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compatible = "gpio-leds";
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status = "okay";
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led0 {
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gpios = <&gpio1 23 1>;
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default-state = "on";
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linux,default-trigger = "heartbeat";
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};
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};
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};
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&i2c0 {
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status = "okay";
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};
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&i2c1 {
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status = "okay";
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hwmon: hwmon@45 {
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status = "okay";
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compatible = "ti,ina219";
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reg = <0x45>;
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shunt-resistor = <2000>;
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};
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||||
};
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&gpio1 {
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interrupts = <27>, <28>, <29>, <30>,
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<31>, <32>, <33>, <47>,
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<35>, <36>, <37>, <38>,
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<39>, <40>, <41>, <42>,
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||||
<43>, <44>, <45>, <46>,
|
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<47>, <48>, <49>, <50>;
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||||
status = "okay";
|
||||
};
|
||||
|
||||
&mac0 {
|
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status = "okay";
|
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phy-mode = "gmii";
|
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phy-handle = <&phy0>;
|
||||
|
||||
};
|
||||
|
||||
&mac1 {
|
||||
status = "okay";
|
||||
phy-mode = "gmii";
|
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phy-handle = <&phy1>;
|
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phy1: ethernet-phy@1 {
|
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reg = <1>;
|
||||
};
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mbox {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mmc {
|
||||
max-frequency = <200000000>;
|
||||
cap-mmc-highspeed;
|
||||
cap-sd-highspeed;
|
||||
no-1-8-v;
|
||||
disable-wp;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mmuart1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mmuart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mmuart3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mmuart4 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&refclk {
|
||||
clock-frequency = <125000000>;
|
||||
};
|
||||
|
||||
&rtc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&spi1 {
|
||||
status = "okay";
|
||||
flash@0 {
|
||||
compatible = "micron,n25q128a11", "jedec,spi-nor";
|
||||
reg = <0x0>;
|
||||
spi-max-frequency = <10000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&syscontroller {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb {
|
||||
status = "okay";
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
|
@ -1,4 +1,4 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
dtb-$(CONFIG_SOC_SIFIVE) += hifive-unleashed-a00.dtb \
|
||||
hifive-unmatched-a00.dtb
|
||||
dtb-$(CONFIG_ARCH_SIFIVE) += hifive-unleashed-a00.dtb \
|
||||
hifive-unmatched-a00.dtb
|
||||
obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))
|
||||
|
|
|
|||
|
|
@ -1,2 +1,2 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
dtb-$(CONFIG_SOC_STARFIVE) += jh7100-beaglev-starlight.dtb jh7100-starfive-visionfive-v1.dtb
|
||||
dtb-$(CONFIG_ARCH_STARFIVE) += jh7100-beaglev-starlight.dtb jh7100-starfive-visionfive-v1.dtb
|
||||
|
|
|
|||
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Reference in New Issue