Merge branch 'net-phy-mscc-PHC-and-timestamping-support'
Antoine Tenart says:
====================
net: phy: mscc: PHC and timestamping support
This series aims at adding support for PHC and timestamping operations
in the MSCC PHY driver, for the VSC858x and VSC8575. Those PHYs are
capable of timestamping in 1-step and 2-step for both L2 and L4 traffic.
As of this series, only IPv4 support was implemented when using L4 mode.
This is because of an hardware limitation which prevents us for
supporting both IPv4 and IPv6 at the same time. Implementing support for
IPv6 should be quite easy (I do have the modifications needed for the
hardware configuration) but I did not see a way to retrieve this
information in hwtstamp(). What would you suggest?
Those PHYs are distributed in hardware packages containing multiple
times the PHY. The VSC8584 for example is composed of 4 PHYs. With
hardware packages, parts of the logic is usually common and one of the
PHY has to be used for some parts of the initialization. Following this
logic, the 1588 blocks of those PHYs are shared between two PHYs and
accessing the registers has to be done using the "base" PHY of the
group. This is handled thanks to helpers in the PTP code (and locks).
We also need the MDIO bus lock while performing a single read or write
to the 1588 registers as the read/write are composed of multiple MDIO
transactions (and we don't want other threads updating the page).
To get and set the PHC time, a GPIO has to be used and changes are only
retrieved or committed when on a rising edge. The same GPIO is shared by
all PHYs, so the granularity of the lock protecting it has to be
different from the ones protecting the 1588 registers (the VSC8584 PHY
has 2 1588 blocks, and a single load/save pin).
Patch 1 extends the recently added helpers to share information between
PHYs of the same hardware package; to allow having part of the probe to
be shared (in addition to the already supported init part). This will be
used when adding support for PHC/TS to initialize locks.
Patches 2 and 3 are mostly cosmetic.
Patch 4 takes into account the 1588 block in the MACsec initialization,
to allow having both the MACsec and 1588 blocks initialized on a running
system.
Patches 5 and 6 add support for PHC and timestamping operations in the
MSCC driver. An initialization of the 1588 block (plus all the registers
definition; and helpers) is added first; and then comes a patch to
implement the PHC and timestamping API.
Patches 7 and 8 add the required hardware description for device trees,
to be able to use the load/save GPIO pin on the PCB120 board.
To use this on a PCB120 board, two other series are needed and have
already been sent upstream (one is merged). There are no dependency
between all those series.
Since v3:
- Fixed a SKB leak.
- Removed ts_lock from the init, as TS and PHC operations aren't
registered at this time.
- Refectored the ts_base_addr/phy intialization.
- Cleaned up the ingr/egr latencies definitons.
- Fixed a comment about locking and the shared GPIO.
- A few cosmetic fixes.
Since v2:
- Removed explicit inlines from .c files.
- Fixed three warnings.
Since v1:
- Removed checks in rxtstamp/txtstamp as skb cannot be NULL here.
- Reworked get_ptp_header_rx/get_ptp_header.
- Reworked the locking logic between the PHC and timestamping
operations.
- Fixed a compilation issue on x86 reported by Jakub.
====================
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
commit
b430081b0c
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|
@ -31,6 +31,8 @@ Optional properties:
|
|||
VSC8531_LINK_100_ACTIVITY (2),
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VSC8531_LINK_ACTIVITY (0) and
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VSC8531_DUPLEX_COLLISION (8).
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- load-save-gpios : GPIO used for the load/save operation of the PTP
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hardware clock (PHC).
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Table: 1 - Edge rate change
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@ -67,4 +69,5 @@ Example:
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vsc8531,edge-slowdown = <7>;
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vsc8531,led-0-mode = <LINK_1000_ACTIVITY>;
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vsc8531,led-1-mode = <LINK_100_ACTIVITY>;
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load-save-gpios = <&gpio 10 GPIO_ACTIVE_HIGH>;
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};
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@ -3,6 +3,7 @@
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/phy/phy-ocelot-serdes.h>
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#include "ocelot.dtsi"
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@ -25,6 +26,11 @@
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pins = "GPIO_4";
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function = "gpio";
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};
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phy_load_save_pins: phy_load_save_pins {
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pins = "GPIO_10";
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function = "ptp2";
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};
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};
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&mdio0 {
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@ -34,27 +40,31 @@
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&mdio1 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&miim1>, <&phy_int_pins>;
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pinctrl-0 = <&miim1>, <&phy_int_pins>, <&phy_load_save_pins>;
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phy7: ethernet-phy@0 {
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reg = <0>;
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interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&gpio>;
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load-save-gpios = <&gpio 10 GPIO_ACTIVE_HIGH>;
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};
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phy6: ethernet-phy@1 {
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reg = <1>;
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interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&gpio>;
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load-save-gpios = <&gpio 10 GPIO_ACTIVE_HIGH>;
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};
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phy5: ethernet-phy@2 {
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reg = <2>;
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interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&gpio>;
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load-save-gpios = <&gpio 10 GPIO_ACTIVE_HIGH>;
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};
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phy4: ethernet-phy@3 {
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reg = <3>;
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interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&gpio>;
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load-save-gpios = <&gpio 10 GPIO_ACTIVE_HIGH>;
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};
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};
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@ -8,3 +8,7 @@ mscc-objs := mscc_main.o
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ifdef CONFIG_MACSEC
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mscc-objs += mscc_macsec.o
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endif
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ifdef CONFIG_NETWORK_PHY_TIMESTAMPING
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mscc-objs += mscc_ptp.o
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endif
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|
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@ -133,6 +133,7 @@ enum rgmii_clock_delay {
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* in the same package.
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*/
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#define MSCC_PHY_PAGE_EXTENDED_GPIO 0x0010 /* Extended reg - GPIO */
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#define MSCC_PHY_PAGE_1588 0x1588 /* PTP (1588) */
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#define MSCC_PHY_PAGE_TEST 0x2a30 /* Test reg */
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#define MSCC_PHY_PAGE_TR 0x52b5 /* Token ring registers */
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@ -252,6 +253,7 @@ enum rgmii_clock_delay {
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/* Test page Registers */
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#define MSCC_PHY_TEST_PAGE_5 5
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#define MSCC_PHY_TEST_PAGE_8 8
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#define TR_CLK_DISABLE 0x8000
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#define MSCC_PHY_TEST_PAGE_9 9
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#define MSCC_PHY_TEST_PAGE_20 20
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#define MSCC_PHY_TEST_PAGE_24 24
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@ -372,6 +374,35 @@ struct vsc8531_private {
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unsigned long ingr_flows;
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unsigned long egr_flows;
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#endif
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struct mii_timestamper mii_ts;
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bool input_clk_init;
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struct vsc85xx_ptp *ptp;
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/* LOAD/SAVE GPIO pin, used for retrieving or setting time to the PHC. */
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struct gpio_desc *load_save;
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/* For multiple port PHYs; the MDIO address of the base PHY in the
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* pair of two PHYs that share a 1588 engine. PHY0 and PHY2 are coupled.
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* PHY1 and PHY3 as well. PHY0 and PHY1 are base PHYs for their
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* respective pair.
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*/
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unsigned int ts_base_addr;
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u8 ts_base_phy;
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/* ts_lock: used for per-PHY timestamping operations.
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* phc_lock: used for per-PHY PHC opertations.
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*/
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struct mutex ts_lock;
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struct mutex phc_lock;
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};
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/* Shared structure between the PHYs of the same package.
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* gpio_lock: used for PHC operations. Common for all PHYs as the load/save GPIO
|
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* is shared.
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*/
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struct vsc85xx_shared_private {
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struct mutex gpio_lock;
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};
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#if IS_ENABLED(CONFIG_OF_MDIO)
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|
|
@ -398,4 +429,36 @@ static inline void vsc8584_config_macsec_intr(struct phy_device *phydev)
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}
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#endif
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#if IS_ENABLED(CONFIG_NETWORK_PHY_TIMESTAMPING)
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void vsc85xx_link_change_notify(struct phy_device *phydev);
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void vsc8584_config_ts_intr(struct phy_device *phydev);
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int vsc8584_ptp_init(struct phy_device *phydev);
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int vsc8584_ptp_probe_once(struct phy_device *phydev);
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int vsc8584_ptp_probe(struct phy_device *phydev);
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irqreturn_t vsc8584_handle_ts_interrupt(struct phy_device *phydev);
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#else
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static inline void vsc85xx_link_change_notify(struct phy_device *phydev)
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{
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}
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static inline void vsc8584_config_ts_intr(struct phy_device *phydev)
|
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{
|
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}
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static inline int vsc8584_ptp_init(struct phy_device *phydev)
|
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{
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return 0;
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}
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static inline int vsc8584_ptp_probe_once(struct phy_device *phydev)
|
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{
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return 0;
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}
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static inline int vsc8584_ptp_probe(struct phy_device *phydev)
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{
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return 0;
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}
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static inline irqreturn_t vsc8584_handle_ts_interrupt(struct phy_device *phydev)
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{
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return IRQ_NONE;
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}
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#endif
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#endif /* _MSCC_PHY_H_ */
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|
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|
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@ -2,7 +2,7 @@
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/*
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* Driver for Microsemi VSC85xx PHYs
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*
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* Copyright (C) 2019 Microsemi Corporation
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* Copyright (C) 2020 Microsemi Corporation
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*/
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#ifndef _MSCC_PHY_FC_BUFFER_H_
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@ -2,7 +2,7 @@
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/*
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* Driver for Microsemi VSC85xx PHYs
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*
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* Copyright (c) 2017 Microsemi Corporation
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* Copyright (c) 2020 Microsemi Corporation
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*/
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#ifndef _MSCC_PHY_LINE_MAC_H_
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|
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@ -1,10 +1,10 @@
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Driver for Microsemi VSC85xx PHYs
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* Driver for Microsemi VSC85xx PHYs - MACsec support
|
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*
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* Author: Nagaraju Lakkaraju
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* Author: Antoine Tenart
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* License: Dual MIT/GPL
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* Copyright (c) 2016 Microsemi Corporation
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* Copyright (c) 2020 Microsemi Corporation
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*/
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#include <linux/phy.h>
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@ -285,7 +285,9 @@ static void vsc8584_macsec_mac_init(struct phy_device *phydev,
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MSCC_MAC_CFG_PKTINF_CFG_STRIP_PREAMBLE_ENA |
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MSCC_MAC_CFG_PKTINF_CFG_INSERT_PREAMBLE_ENA |
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(bank == HOST_MAC ?
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MSCC_MAC_CFG_PKTINF_CFG_ENABLE_TX_PADDING : 0));
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MSCC_MAC_CFG_PKTINF_CFG_ENABLE_TX_PADDING : 0) |
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(IS_ENABLED(CONFIG_NETWORK_PHY_TIMESTAMPING) ?
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MSCC_MAC_CFG_PKTINF_CFG_MACSEC_BYPASS_NUM_PTP_STALL_CLKS(0x8) : 0));
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val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MAC_CFG_MODE_CFG);
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val &= ~MSCC_MAC_CFG_MODE_CFG_DISABLE_DIC;
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@ -2,7 +2,7 @@
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/*
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* Driver for Microsemi VSC85xx PHYs
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*
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* Copyright (c) 2018 Microsemi Corporation
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* Copyright (c) 2020 Microsemi Corporation
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*/
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#ifndef _MSCC_PHY_MACSEC_H_
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|
|
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@ -629,7 +629,7 @@ static int vsc8531_pre_init_seq_set(struct phy_device *phydev)
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if (rc < 0)
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return rc;
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rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_TEST,
|
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MSCC_PHY_TEST_PAGE_8, 0x8000, 0x8000);
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MSCC_PHY_TEST_PAGE_8, TR_CLK_DISABLE, TR_CLK_DISABLE);
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if (rc < 0)
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return rc;
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@ -1026,7 +1026,7 @@ static int vsc8574_config_pre_init(struct phy_device *phydev)
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|||
phy_base_write(phydev, MSCC_PHY_TEST_PAGE_5, 0x1b20);
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reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
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reg |= 0x8000;
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reg |= TR_CLK_DISABLE;
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phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
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phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);
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|
@ -1046,7 +1046,7 @@ static int vsc8574_config_pre_init(struct phy_device *phydev)
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|||
phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);
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||||
|
||||
reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
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reg &= ~0x8000;
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reg &= ~TR_CLK_DISABLE;
|
||||
phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
|
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|
||||
phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
|
||||
|
|
@ -1196,7 +1196,7 @@ static int vsc8584_config_pre_init(struct phy_device *phydev)
|
|||
phy_base_write(phydev, MSCC_PHY_TEST_PAGE_5, 0x1f20);
|
||||
|
||||
reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
|
||||
reg |= 0x8000;
|
||||
reg |= TR_CLK_DISABLE;
|
||||
phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
|
||||
|
||||
phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);
|
||||
|
|
@ -1225,7 +1225,7 @@ static int vsc8584_config_pre_init(struct phy_device *phydev)
|
|||
phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);
|
||||
|
||||
reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
|
||||
reg &= ~0x8000;
|
||||
reg &= ~TR_CLK_DISABLE;
|
||||
phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
|
||||
|
||||
phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
|
||||
|
|
@ -1299,10 +1299,26 @@ static void vsc8584_get_base_addr(struct phy_device *phydev)
|
|||
__phy_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
|
||||
mutex_unlock(&phydev->mdio.bus->mdio_lock);
|
||||
|
||||
if (val & PHY_ADDR_REVERSED)
|
||||
/* In the package, there are two pairs of PHYs (PHY0 + PHY2 and
|
||||
* PHY1 + PHY3). The first PHY of each pair (PHY0 and PHY1) is
|
||||
* the base PHY for timestamping operations.
|
||||
*/
|
||||
vsc8531->ts_base_addr = phydev->mdio.addr;
|
||||
vsc8531->ts_base_phy = addr;
|
||||
|
||||
if (val & PHY_ADDR_REVERSED) {
|
||||
vsc8531->base_addr = phydev->mdio.addr + addr;
|
||||
else
|
||||
if (addr > 1) {
|
||||
vsc8531->ts_base_addr += 2;
|
||||
vsc8531->ts_base_phy += 2;
|
||||
}
|
||||
} else {
|
||||
vsc8531->base_addr = phydev->mdio.addr - addr;
|
||||
if (addr > 1) {
|
||||
vsc8531->ts_base_addr -= 2;
|
||||
vsc8531->ts_base_phy -= 2;
|
||||
}
|
||||
}
|
||||
|
||||
vsc8531->addr = addr;
|
||||
}
|
||||
|
|
@ -1418,6 +1434,10 @@ static int vsc8584_config_init(struct phy_device *phydev)
|
|||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = vsc8584_ptp_init(phydev);
|
||||
if (ret)
|
||||
goto err;
|
||||
|
||||
phy_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
|
||||
|
||||
val = phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_1);
|
||||
|
|
@ -1455,12 +1475,20 @@ err:
|
|||
|
||||
static irqreturn_t vsc8584_handle_interrupt(struct phy_device *phydev)
|
||||
{
|
||||
irqreturn_t ret;
|
||||
int irq_status;
|
||||
|
||||
irq_status = phy_read(phydev, MII_VSC85XX_INT_STATUS);
|
||||
if (irq_status < 0 || !(irq_status & MII_VSC85XX_INT_MASK_MASK))
|
||||
if (irq_status < 0)
|
||||
return IRQ_NONE;
|
||||
|
||||
/* Timestamping IRQ does not set a bit in the global INT_STATUS, so
|
||||
* irq_status would be 0.
|
||||
*/
|
||||
ret = vsc8584_handle_ts_interrupt(phydev);
|
||||
if (!(irq_status & MII_VSC85XX_INT_MASK_MASK))
|
||||
return ret;
|
||||
|
||||
if (irq_status & MII_VSC85XX_INT_MASK_EXT)
|
||||
vsc8584_handle_macsec_interrupt(phydev);
|
||||
|
||||
|
|
@ -1900,6 +1928,7 @@ static int vsc85xx_config_intr(struct phy_device *phydev)
|
|||
|
||||
if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
|
||||
vsc8584_config_macsec_intr(phydev);
|
||||
vsc8584_config_ts_intr(phydev);
|
||||
|
||||
rc = phy_write(phydev, MII_VSC85XX_INT_MASK,
|
||||
MII_VSC85XX_INT_MASK_MASK);
|
||||
|
|
@ -1999,6 +2028,7 @@ static int vsc8584_probe(struct phy_device *phydev)
|
|||
u32 default_mode[4] = {VSC8531_LINK_1000_ACTIVITY,
|
||||
VSC8531_LINK_100_ACTIVITY, VSC8531_LINK_ACTIVITY,
|
||||
VSC8531_DUPLEX_COLLISION};
|
||||
int ret;
|
||||
|
||||
if ((phydev->phy_id & MSCC_DEV_REV_MASK) != VSC8584_REVB) {
|
||||
dev_err(&phydev->mdio.dev, "Only VSC8584 revB is supported.\n");
|
||||
|
|
@ -2012,8 +2042,8 @@ static int vsc8584_probe(struct phy_device *phydev)
|
|||
phydev->priv = vsc8531;
|
||||
|
||||
vsc8584_get_base_addr(phydev);
|
||||
devm_phy_package_join(&phydev->mdio.dev, phydev,
|
||||
vsc8531->base_addr, 0);
|
||||
devm_phy_package_join(&phydev->mdio.dev, phydev, vsc8531->base_addr,
|
||||
sizeof(struct vsc85xx_shared_private));
|
||||
|
||||
vsc8531->nleds = 4;
|
||||
vsc8531->supp_led_modes = VSC8584_SUPP_LED_MODES;
|
||||
|
|
@ -2024,6 +2054,16 @@ static int vsc8584_probe(struct phy_device *phydev)
|
|||
if (!vsc8531->stats)
|
||||
return -ENOMEM;
|
||||
|
||||
if (phy_package_probe_once(phydev)) {
|
||||
ret = vsc8584_ptp_probe_once(phydev);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = vsc8584_ptp_probe(phydev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return vsc85xx_dt_led_modes_get(phydev, default_mode);
|
||||
}
|
||||
|
||||
|
|
@ -2403,6 +2443,7 @@ static struct phy_driver vsc85xx_driver[] = {
|
|||
.get_sset_count = &vsc85xx_get_sset_count,
|
||||
.get_strings = &vsc85xx_get_strings,
|
||||
.get_stats = &vsc85xx_get_stats,
|
||||
.link_change_notify = &vsc85xx_link_change_notify,
|
||||
}
|
||||
|
||||
};
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,477 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
|
||||
/*
|
||||
* Driver for Microsemi VSC85xx PHYs
|
||||
*
|
||||
* Copyright (c) 2020 Microsemi Corporation
|
||||
*/
|
||||
|
||||
#ifndef _MSCC_PHY_PTP_H_
|
||||
#define _MSCC_PHY_PTP_H_
|
||||
|
||||
/* 1588 page Registers */
|
||||
#define MSCC_PHY_TS_BIU_ADDR_CNTL 16
|
||||
#define BIU_ADDR_EXE 0x8000
|
||||
#define BIU_ADDR_READ 0x4000
|
||||
#define BIU_ADDR_WRITE 0x0000
|
||||
#define BIU_BLK_ID(x) ((x) << 11)
|
||||
#define BIU_CSR_ADDR(x) (x)
|
||||
#define BIU_ADDR_CNT_MAX 8
|
||||
|
||||
#define MSCC_PHY_TS_CSR_DATA_LSB 17
|
||||
#define MSCC_PHY_TS_CSR_DATA_MSB 18
|
||||
|
||||
#define MSCC_PHY_1588_INGR_VSC85XX_INT_STATUS 0x002d
|
||||
#define MSCC_PHY_1588_VSC85XX_INT_STATUS 0x004d
|
||||
#define VSC85XX_1588_INT_FIFO_ADD 0x0004
|
||||
#define VSC85XX_1588_INT_FIFO_OVERFLOW 0x0001
|
||||
|
||||
#define MSCC_PHY_1588_INGR_VSC85XX_INT_MASK 0x002e
|
||||
#define MSCC_PHY_1588_VSC85XX_INT_MASK 0x004e
|
||||
#define VSC85XX_1588_INT_MASK_MASK (VSC85XX_1588_INT_FIFO_ADD | \
|
||||
VSC85XX_1588_INT_FIFO_OVERFLOW)
|
||||
|
||||
/* TS CSR addresses */
|
||||
#define MSCC_PHY_ANA_ETH1_NTX_PROT 0x0000
|
||||
#define ANA_ETH1_NTX_PROT_SIG_OFF_MASK GENMASK(20, 16)
|
||||
#define ANA_ETH1_NTX_PROT_SIG_OFF(x) (((x) << 16) & ANA_ETH1_NTX_PROT_SIG_OFF_MASK)
|
||||
#define ANA_ETH1_NTX_PROT_COMPARATOR_MASK GENMASK(2, 0)
|
||||
#define ANA_ETH1_NTX_PROT_PTP_OAM 0x0005
|
||||
#define ANA_ETH1_NTX_PROT_MPLS 0x0004
|
||||
#define ANA_ETH1_NTX_PROT_IP_UDP_ACH_2 0x0003
|
||||
#define ANA_ETH1_NTX_PROT_IP_UDP_ACH_1 0x0002
|
||||
#define ANA_ETH1_NTX_PROT_ETH2 0x0001
|
||||
|
||||
#define MSCC_PHY_PTP_IFACE_CTRL 0x0000
|
||||
#define PTP_IFACE_CTRL_CLK_ENA 0x0040
|
||||
#define PTP_IFACE_CTRL_INGR_BYPASS 0x0008
|
||||
#define PTP_IFACE_CTRL_EGR_BYPASS 0x0004
|
||||
#define PTP_IFACE_CTRL_MII_PROT 0x0003
|
||||
#define PTP_IFACE_CTRL_GMII_PROT 0x0002
|
||||
#define PTP_IFACE_CTRL_XGMII_64_PROT 0x0000
|
||||
|
||||
#define MSCC_PHY_ANA_ETH1_NTX_PROT_VLAN_TPID 0x0001
|
||||
#define ANA_ETH1_NTX_PROT_VLAN_TPID_MASK GENMASK(31, 16)
|
||||
#define ANA_ETH1_NTX_PROT_VLAN_TPID(x) (((x) << 16) & ANA_ETH1_NTX_PROT_VLAN_TPID_MASK)
|
||||
|
||||
#define MSCC_PHY_PTP_ANALYZER_MODE 0x0001
|
||||
#define PTP_ANA_SPLIT_ENCAP_FLOW 0x1000000
|
||||
#define PTP_ANA_EGR_ENCAP_FLOW_MODE_MASK GENMASK(22, 20)
|
||||
#define PTP_ANA_EGR_ENCAP_FLOW_MODE(x) (((x) << 20) & PTP_ANA_EGR_ENCAP_FLOW_MODE_MASK)
|
||||
#define PTP_ANA_INGR_ENCAP_FLOW_MODE_MASK GENMASK(18, 16)
|
||||
#define PTP_ANA_INGR_ENCAP_FLOW_MODE(x) (((x) << 16) & PTP_ANA_INGR_ENCAP_FLOW_MODE_MASK)
|
||||
#define PTP_ANALYZER_MODE_EGR_ENA_MASK GENMASK(6, 4)
|
||||
#define PTP_ANALYZER_MODE_EGR_ENA(x) (((x) << 4) & PTP_ANALYZER_MODE_EGR_ENA_MASK)
|
||||
#define PTP_ANALYZER_MODE_INGR_ENA_MASK GENMASK(2, 0)
|
||||
#define PTP_ANALYZER_MODE_INGR_ENA(x) ((x) & PTP_ANALYZER_MODE_INGR_ENA_MASK)
|
||||
|
||||
#define MSCC_PHY_ANA_ETH1_NXT_PROT_TAG 0x0002
|
||||
#define ANA_ETH1_NXT_PROT_TAG_ENA 0x0001
|
||||
|
||||
#define MSCC_PHY_PTP_MODE_CTRL 0x0002
|
||||
#define PTP_MODE_CTRL_MODE_MASK GENMASK(2, 0)
|
||||
#define PTP_MODE_CTRL_PKT_MODE 0x0004
|
||||
|
||||
#define MSCC_PHY_ANA_ETH1_NXT_PROT_ETYPE_MATCH 0x0003
|
||||
#define ANA_ETH1_NXT_PROT_ETYPE_MATCH_ENA 0x10000
|
||||
#define ANA_ETH1_NXT_PROT_ETYPE_MATCH_MASK GENMASK(15, 0)
|
||||
#define ANA_ETH1_NXT_PROT_ETYPE_MATCH(x) ((x) & ANA_ETH1_NXT_PROT_ETYPE_MATCH_MASK)
|
||||
|
||||
#define MSCC_PHY_PTP_VERSION_CODE 0x0003
|
||||
#define PTP_IP_VERSION_MASK GENMASK(7, 0)
|
||||
#define PTP_IP_VERSION_2_1 0x0021
|
||||
|
||||
#define MSCC_ANA_ETH1_FLOW_ENA(x) (0x0010 + ((x) << 4))
|
||||
#define ETH1_FLOW_ENA_CHANNEL_MASK_MASK GENMASK(9, 8)
|
||||
#define ETH1_FLOW_ENA_CHANNEL_MASK(x) (((x) << 8) & ETH1_FLOW_ENA_CHANNEL_MASK_MASK)
|
||||
#define ETH1_FLOW_VALID_CH1 ETH1_FLOW_ENA_CHANNEL_MASK(2)
|
||||
#define ETH1_FLOW_VALID_CH0 ETH1_FLOW_ENA_CHANNEL_MASK(1)
|
||||
#define ETH1_FLOW_ENA 0x0001
|
||||
|
||||
#define MSCC_ANA_ETH1_FLOW_MATCH_MODE(x) (MSCC_ANA_ETH1_FLOW_ENA(x) + 1)
|
||||
#define ANA_ETH1_FLOW_MATCH_VLAN_TAG_MASK GENMASK(7, 6)
|
||||
#define ANA_ETH1_FLOW_MATCH_VLAN_TAG(x) (((x) << 6) & ANA_ETH1_FLOW_MATCH_VLAN_TAG_MASK)
|
||||
#define ANA_ETH1_FLOW_MATCH_VLAN_TAG2 0x0200
|
||||
#define ANA_ETH1_FLOW_MATCH_VLAN_VERIFY 0x0010
|
||||
|
||||
#define MSCC_ANA_ETH1_FLOW_ADDR_MATCH1(x) (MSCC_ANA_ETH1_FLOW_ENA(x) + 2)
|
||||
|
||||
#define MSCC_ANA_ETH1_FLOW_ADDR_MATCH2(x) (MSCC_ANA_ETH1_FLOW_ENA(x) + 3)
|
||||
#define ANA_ETH1_FLOW_ADDR_MATCH2_MASK_MASK GENMASK(22, 20)
|
||||
#define ANA_ETH1_FLOW_ADDR_MATCH2_ANY_MULTICAST 0x400000
|
||||
#define ANA_ETH1_FLOW_ADDR_MATCH2_FULL_ADDR 0x100000
|
||||
#define ANA_ETH1_FLOW_ADDR_MATCH2_SRC_DEST_MASK GENMASK(17, 16)
|
||||
#define ANA_ETH1_FLOW_ADDR_MATCH2_SRC_DEST 0x020000
|
||||
#define ANA_ETH1_FLOW_ADDR_MATCH2_SRC 0x010000
|
||||
#define ANA_ETH1_FLOW_ADDR_MATCH2_DEST 0x000000
|
||||
|
||||
#define MSCC_ANA_ETH1_FLOW_VLAN_RANGE_I_TAG(x) (MSCC_ANA_ETH1_FLOW_ENA(x) + 4)
|
||||
#define MSCC_ANA_ETH1_FLOW_VLAN_TAG1(x) (MSCC_ANA_ETH1_FLOW_ENA(x) + 5)
|
||||
#define MSCC_ANA_ETH1_FLOW_VLAN_TAG2_I_TAG(x) (MSCC_ANA_ETH1_FLOW_ENA(x) + 6)
|
||||
|
||||
#define MSCC_PHY_PTP_LTC_CTRL 0x0010
|
||||
#define PTP_LTC_CTRL_CLK_SEL_MASK GENMASK(14, 12)
|
||||
#define PTP_LTC_CTRL_CLK_SEL(x) (((x) << 12) & PTP_LTC_CTRL_CLK_SEL_MASK)
|
||||
#define PTP_LTC_CTRL_CLK_SEL_INTERNAL_250 PTP_LTC_CTRL_CLK_SEL(5)
|
||||
#define PTP_LTC_CTRL_AUTO_ADJ_UPDATE 0x0010
|
||||
#define PTP_LTC_CTRL_ADD_SUB_1NS_REQ 0x0008
|
||||
#define PTP_LTC_CTRL_ADD_1NS 0x0004
|
||||
#define PTP_LTC_CTRL_SAVE_ENA 0x0002
|
||||
#define PTP_LTC_CTRL_LOAD_ENA 0x0001
|
||||
|
||||
#define MSCC_PHY_PTP_LTC_LOAD_SEC_MSB 0x0011
|
||||
#define PTP_LTC_LOAD_SEC_MSB(x) (((x) & GENMASK_ULL(47, 32)) >> 32)
|
||||
|
||||
#define MSCC_PHY_PTP_LTC_LOAD_SEC_LSB 0x0012
|
||||
#define PTP_LTC_LOAD_SEC_LSB(x) ((x) & GENMASK(31, 0))
|
||||
|
||||
#define MSCC_PHY_PTP_LTC_LOAD_NS 0x0013
|
||||
#define PTP_LTC_LOAD_NS(x) ((x) & GENMASK(31, 0))
|
||||
|
||||
#define MSCC_PHY_PTP_LTC_SAVED_SEC_MSB 0x0014
|
||||
#define MSCC_PHY_PTP_LTC_SAVED_SEC_LSB 0x0015
|
||||
#define MSCC_PHY_PTP_LTC_SAVED_NS 0x0016
|
||||
|
||||
#define MSCC_PHY_PTP_LTC_SEQUENCE 0x0017
|
||||
#define PTP_LTC_SEQUENCE_A_MASK GENMASK(3, 0)
|
||||
#define PTP_LTC_SEQUENCE_A(x) ((x) & PTP_LTC_SEQUENCE_A_MASK)
|
||||
|
||||
#define MSCC_PHY_PTP_LTC_SEQ 0x0018
|
||||
#define PTP_LTC_SEQ_ADD_SUB 0x80000
|
||||
#define PTP_LTC_SEQ_ERR_MASK GENMASK(18, 0)
|
||||
#define PTP_LTC_SEQ_ERR(x) ((x) & PTP_LTC_SEQ_ERR_MASK)
|
||||
|
||||
#define MSCC_PHY_PTP_LTC_AUTO_ADJ 0x001a
|
||||
#define PTP_AUTO_ADJ_NS_ROLLOVER(x) ((x) & GENMASK(29, 0))
|
||||
#define PTP_AUTO_ADJ_ADD_SUB_1NS_MASK GENMASK(31, 30)
|
||||
#define PTP_AUTO_ADJ_SUB_1NS 0x80000000
|
||||
#define PTP_AUTO_ADJ_ADD_1NS 0x40000000
|
||||
|
||||
#define MSCC_PHY_PTP_LTC_1PPS_WIDTH_ADJ 0x001b
|
||||
#define PTP_LTC_1PPS_WIDTH_ADJ_MASK GENMASK(29, 0)
|
||||
|
||||
#define MSCC_PHY_PTP_TSTAMP_FIFO_SI 0x0020
|
||||
#define PTP_TSTAMP_FIFO_SI_EN 0x0001
|
||||
|
||||
#define MSCC_PHY_PTP_INGR_PREDICTOR 0x0022
|
||||
#define PTP_INGR_PREDICTOR_EN 0x0001
|
||||
|
||||
#define MSCC_PHY_PTP_EGR_PREDICTOR 0x0026
|
||||
#define PTP_EGR_PREDICTOR_EN 0x0001
|
||||
|
||||
#define MSCC_PHY_PTP_INGR_TSP_CTRL 0x0035
|
||||
#define PHY_PTP_INGR_TSP_CTRL_FRACT_NS 0x0004
|
||||
#define PHY_PTP_INGR_TSP_CTRL_LOAD_DELAYS 0x0001
|
||||
|
||||
#define MSCC_PHY_PTP_INGR_LOCAL_LATENCY 0x0037
|
||||
#define PTP_INGR_LOCAL_LATENCY_MASK GENMASK(22, 0)
|
||||
#define PTP_INGR_LOCAL_LATENCY(x) ((x) & PTP_INGR_LOCAL_LATENCY_MASK)
|
||||
|
||||
#define MSCC_PHY_PTP_INGR_DELAY_FIFO 0x003a
|
||||
#define PTP_INGR_DELAY_FIFO_DEPTH_MACSEC 0x0013
|
||||
#define PTP_INGR_DELAY_FIFO_DEPTH_DEFAULT 0x000f
|
||||
|
||||
#define MSCC_PHY_PTP_INGR_TS_FIFO(x) (0x005c + (x))
|
||||
#define PTP_INGR_TS_FIFO_EMPTY 0x80000000
|
||||
|
||||
#define MSCC_PHY_PTP_INGR_REWRITER_CTRL 0x0044
|
||||
#define PTP_INGR_REWRITER_REDUCE_PREAMBLE 0x0010
|
||||
#define PTP_INGR_REWRITER_FLAG_VAL 0x0008
|
||||
#define PTP_INGR_REWRITER_FLAG_BIT_OFF_M GENMASK(2, 0)
|
||||
#define PTP_INGR_REWRITER_FLAG_BIT_OFF(x) ((x) & PTP_INGR_REWRITER_FLAG_BIT_OFF_M)
|
||||
|
||||
#define MSCC_PHY_PTP_EGR_STALL_LATENCY 0x004f
|
||||
|
||||
#define MSCC_PHY_PTP_EGR_TSP_CTRL 0x0055
|
||||
#define PHY_PTP_EGR_TSP_CTRL_FRACT_NS 0x0004
|
||||
#define PHY_PTP_EGR_TSP_CTRL_LOAD_DELAYS 0x0001
|
||||
|
||||
#define MSCC_PHY_PTP_EGR_LOCAL_LATENCY 0x0057
|
||||
#define PTP_EGR_LOCAL_LATENCY_MASK GENMASK(22, 0)
|
||||
#define PTP_EGR_LOCAL_LATENCY(x) ((x) & PTP_EGR_LOCAL_LATENCY_MASK)
|
||||
|
||||
#define MSCC_PHY_PTP_EGR_DELAY_FIFO 0x005a
|
||||
#define PTP_EGR_DELAY_FIFO_DEPTH_MACSEC 0x0013
|
||||
#define PTP_EGR_DELAY_FIFO_DEPTH_DEFAULT 0x000f
|
||||
|
||||
#define MSCC_PHY_PTP_EGR_TS_FIFO_CTRL 0x005b
|
||||
#define PTP_EGR_TS_FIFO_RESET 0x10000
|
||||
#define PTP_EGR_FIFO_LEVEL_LAST_READ_MASK GENMASK(15, 12)
|
||||
#define PTP_EGR_FIFO_LEVEL_LAST_READ(x) (((x) & PTP_EGR_FIFO_LEVEL_LAST_READ_MASK) >> 12)
|
||||
#define PTP_EGR_TS_FIFO_THRESH_MASK GENMASK(11, 8)
|
||||
#define PTP_EGR_TS_FIFO_THRESH(x) (((x) << 8) & PTP_EGR_TS_FIFO_THRESH_MASK)
|
||||
#define PTP_EGR_TS_FIFO_SIG_BYTES_MASK GENMASK(4, 0)
|
||||
#define PTP_EGR_TS_FIFO_SIG_BYTES(x) ((x) & PTP_EGR_TS_FIFO_SIG_BYTES_MASK)
|
||||
|
||||
#define MSCC_PHY_PTP_EGR_TS_FIFO(x) (0x005c + (x))
|
||||
#define PTP_EGR_TS_FIFO_EMPTY 0x80000000
|
||||
#define PTP_EGR_TS_FIFO_0_MASK GENMASK(15, 0)
|
||||
|
||||
#define MSCC_PHY_PTP_EGR_REWRITER_CTRL 0x0064
|
||||
#define PTP_EGR_REWRITER_REDUCE_PREAMBLE 0x0010
|
||||
#define PTP_EGR_REWRITER_FLAG_VAL 0x0008
|
||||
#define PTP_EGR_REWRITER_FLAG_BIT_OFF_M GENMASK(2, 0)
|
||||
#define PTP_EGR_REWRITER_FLAG_BIT_OFF(x) ((x) & PTP_EGR_REWRITER_FLAG_BIT_OFF_M)
|
||||
|
||||
#define MSCC_PHY_PTP_SERIAL_TOD_IFACE 0x006e
|
||||
#define PTP_SERIAL_TOD_IFACE_LS_AUTO_CLR 0x0004
|
||||
|
||||
#define MSCC_PHY_PTP_LTC_OFFSET 0x0070
|
||||
#define PTP_LTC_OFFSET_ADJ BIT(31)
|
||||
#define PTP_LTC_OFFSET_ADD BIT(30)
|
||||
#define PTP_LTC_OFFSET_VAL(x) (x)
|
||||
|
||||
#define MSCC_PHY_PTP_ACCUR_CFG_STATUS 0x0074
|
||||
#define PTP_ACCUR_PPS_OUT_CALIB_ERR 0x20000
|
||||
#define PTP_ACCUR_PPS_OUT_CALIB_DONE 0x10000
|
||||
#define PTP_ACCUR_PPS_IN_CALIB_ERR 0x4000
|
||||
#define PTP_ACCUR_PPS_IN_CALIB_DONE 0x2000
|
||||
#define PTP_ACCUR_EGR_SOF_CALIB_ERR 0x1000
|
||||
#define PTP_ACCUR_EGR_SOF_CALIB_DONE 0x0800
|
||||
#define PTP_ACCUR_INGR_SOF_CALIB_ERR 0x0400
|
||||
#define PTP_ACCUR_INGR_SOF_CALIB_DONE 0x0200
|
||||
#define PTP_ACCUR_LOAD_SAVE_CALIB_ERR 0x0100
|
||||
#define PTP_ACCUR_LOAD_SAVE_CALIB_DONE 0x0080
|
||||
#define PTP_ACCUR_CALIB_TRIGG 0x0040
|
||||
#define PTP_ACCUR_PPS_OUT_BYPASS 0x0010
|
||||
#define PTP_ACCUR_PPS_IN_BYPASS 0x0008
|
||||
#define PTP_ACCUR_EGR_SOF_BYPASS 0x0004
|
||||
#define PTP_ACCUR_INGR_SOF_BYPASS 0x0002
|
||||
#define PTP_ACCUR_LOAD_SAVE_BYPASS 0x0001
|
||||
|
||||
#define MSCC_PHY_ANA_ETH2_NTX_PROT 0x0090
|
||||
#define ANA_ETH2_NTX_PROT_COMPARATOR_MASK GENMASK(2, 0)
|
||||
#define ANA_ETH2_NTX_PROT_PTP_OAM 0x0005
|
||||
#define ANA_ETH2_NTX_PROT_MPLS 0x0004
|
||||
#define ANA_ETH2_NTX_PROT_IP_UDP_ACH_2 0x0003
|
||||
#define ANA_ETH2_NTX_PROT_IP_UDP_ACH_1 0x0002
|
||||
#define ANA_ETH2_NTX_PROT_ETH2 0x0001
|
||||
|
||||
#define MSCC_PHY_ANA_ETH2_NXT_PROT_ETYPE_MATCH 0x0003
|
||||
#define ANA_ETH2_NXT_PROT_ETYPE_MATCH_ENA 0x10000
|
||||
#define ANA_ETH2_NXT_PROT_ETYPE_MATCH_MASK GENMASK(15, 0)
|
||||
#define ANA_ETH2_NXT_PROT_ETYPE_MATCH(x) ((x) & ANA_ETH2_NXT_PROT_ETYPE_MATCH_MASK)
|
||||
|
||||
#define MSCC_ANA_ETH2_FLOW_ENA(x) (0x00a0 + ((x) << 4))
|
||||
#define ETH2_FLOW_ENA_CHANNEL_MASK_MASK GENMASK(9, 8)
|
||||
#define ETH2_FLOW_ENA_CHANNEL_MASK(x) (((x) << 8) & ETH2_FLOW_ENA_CHANNEL_MASK_MASK)
|
||||
#define ETH2_FLOW_VALID_CH1 ETH2_FLOW_ENA_CHANNEL_MASK(2)
|
||||
#define ETH2_FLOW_VALID_CH0 ETH2_FLOW_ENA_CHANNEL_MASK(1)
|
||||
|
||||
#define MSCC_PHY_ANA_MPLS_COMP_NXT_COMP 0x0120
|
||||
#define ANA_MPLS_NTX_PROT_COMPARATOR_MASK GENMASK(2, 0)
|
||||
#define ANA_MPLS_NTX_PROT_PTP_OAM 0x0005
|
||||
#define ANA_MPLS_NTX_PROT_MPLS 0x0004
|
||||
#define ANA_MPLS_NTX_PROT_IP_UDP_ACH_2 0x0003
|
||||
#define ANA_MPLS_NTX_PROT_IP_UDP_ACH_1 0x0002
|
||||
#define ANA_MPLS_NTX_PROT_ETH2 0x0001
|
||||
|
||||
#define MSCC_ANA_MPLS_FLOW_CTRL(x) (0x0130 + ((x) << 4))
|
||||
#define MPLS_FLOW_CTRL_CHANNEL_MASK_MASK GENMASK(25, 24)
|
||||
#define MPLS_FLOW_CTRL_CHANNEL_MASK(x) (((x) << 24) & MPLS_FLOW_CTRL_CHANNEL_MASK_MASK)
|
||||
#define MPLS_FLOW_VALID_CH1 MPLS_FLOW_CTRL_CHANNEL_MASK(2)
|
||||
#define MPLS_FLOW_VALID_CH0 MPLS_FLOW_CTRL_CHANNEL_MASK(1)
|
||||
|
||||
#define MSCC_ANA_IP1_NXT_PROT_NXT_COMP 0x01b0
|
||||
#define ANA_IP1_NXT_PROT_NXT_COMP_BYTES_HDR_MASK GENMASK(15, 8)
|
||||
#define ANA_IP1_NXT_PROT_NXT_COMP_BYTES_HDR(x) (((x) << 8) & ANA_IP1_NXT_PROT_NXT_COMP_BYTES_HDR_MASK)
|
||||
#define ANA_IP1_NXT_PROT_NXT_COMP_PTP_OAM 0x0005
|
||||
#define ANA_IP1_NXT_PROT_NXT_COMP_IP_UDP_ACH2 0x0003
|
||||
|
||||
#define MSCC_ANA_IP1_NXT_PROT_IP1_MODE 0x01b1
|
||||
#define ANA_IP1_NXT_PROT_FLOW_OFFSET_IPV4 0x0c00
|
||||
#define ANA_IP1_NXT_PROT_FLOW_OFFSET_IPV6 0x0800
|
||||
#define ANA_IP1_NXT_PROT_IPV6 0x0001
|
||||
#define ANA_IP1_NXT_PROT_IPV4 0x0000
|
||||
|
||||
#define MSCC_ANA_IP1_NXT_PROT_IP_MATCH1 0x01b2
|
||||
#define ANA_IP1_NXT_PROT_IP_MATCH1_PROT_OFF_MASK GENMASK(20, 16)
|
||||
#define ANA_IP1_NXT_PROT_IP_MATCH1_PROT_OFF(x) (((x) << 16) & ANA_IP1_NXT_PROT_IP_MATCH1_PROT_OFF_MASK)
|
||||
#define ANA_IP1_NXT_PROT_IP_MATCH1_PROT_MASK_MASK GENMASK(15, 8)
|
||||
#define ANA_IP1_NXT_PROT_IP_MATCH1_PROT_MASK(x) (((x) << 15) & ANA_IP1_NXT_PROT_IP_MATCH1_PROT_MASK_MASK)
|
||||
#define ANA_IP1_NXT_PROT_IP_MATCH1_PROT_MATCH_MASK GENMASK(7, 0)
|
||||
#define ANA_IP1_NXT_PROT_IP_MATCH1_PROT_MATCH(x) ((x) & ANA_IP1_NXT_PROT_IP_MATCH1_PROT_MATCH_MASK)
|
||||
|
||||
#define MSCC_ANA_IP1_NXT_PROT_MATCH2_UPPER 0x01b3
|
||||
#define MSCC_ANA_IP1_NXT_PROT_MATCH2_LOWER 0x01b4
|
||||
#define MSCC_ANA_IP1_NXT_PROT_MASK2_UPPER 0x01b5
|
||||
#define MSCC_ANA_IP1_NXT_PROT_MASK2_LOWER 0x01b6
|
||||
|
||||
#define MSCC_ANA_IP1_NXT_PROT_OFFSET2 0x01b7
|
||||
#define ANA_IP1_NXT_PROT_OFFSET2_MASK GENMASK(6, 0)
|
||||
#define ANA_IP1_NXT_PROT_OFFSET2(x) ((x) & ANA_IP1_NXT_PROT_OFFSET2_MASK)
|
||||
|
||||
#define MSCC_ANA_IP1_NXT_PROT_UDP_CHKSUM 0x01b8
|
||||
#define IP1_NXT_PROT_UDP_CHKSUM_OFF_MASK GENMASK(15, 8)
|
||||
#define IP1_NXT_PROT_UDP_CHKSUM_OFF(x) (((x) << 8) & IP1_NXT_PROT_UDP_CHKSUM_OFF_MASK)
|
||||
#define IP1_NXT_PROT_UDP_CHKSUM_WIDTH_MASK GENMASK(5, 4)
|
||||
#define IP1_NXT_PROT_UDP_CHKSUM_WIDTH(x) (((x) << 4) & IP1_NXT_PROT_UDP_CHKSUM_WIDTH_MASK)
|
||||
#define IP1_NXT_PROT_UDP_CHKSUM_UPDATE 0x0002
|
||||
#define IP1_NXT_PROT_UDP_CHKSUM_CLEAR 0x0001
|
||||
|
||||
#define MSCC_ANA_IP1_FLOW_ENA(x) (0x01c0 + ((x) << 4))
|
||||
#define IP1_FLOW_MATCH_ADDR_MASK GENMASK(9, 8)
|
||||
#define IP1_FLOW_MATCH_DEST_SRC_ADDR 0x0200
|
||||
#define IP1_FLOW_MATCH_DEST_ADDR 0x0100
|
||||
#define IP1_FLOW_MATCH_SRC_ADDR 0x0000
|
||||
#define IP1_FLOW_ENA_CHANNEL_MASK_MASK GENMASK(5, 4)
|
||||
#define IP1_FLOW_ENA_CHANNEL_MASK(x) (((x) << 4) & IP1_FLOW_ENA_CHANNEL_MASK_MASK)
|
||||
#define IP1_FLOW_VALID_CH1 IP1_FLOW_ENA_CHANNEL_MASK(2)
|
||||
#define IP1_FLOW_VALID_CH0 IP1_FLOW_ENA_CHANNEL_MASK(1)
|
||||
#define IP1_FLOW_ENA 0x0001
|
||||
|
||||
#define MSCC_ANA_OAM_PTP_FLOW_ENA(x) (0x1e0 + ((x) << 4))
|
||||
#define MSCC_ANA_OAM_PTP_FLOW_MATCH_LOWER(x) (MSCC_ANA_OAM_PTP_FLOW_ENA(x) + 2)
|
||||
#define MSCC_ANA_OAM_PTP_FLOW_MASK_LOWER(x) (MSCC_ANA_OAM_PTP_FLOW_ENA(x) + 4)
|
||||
|
||||
#define MSCC_ANA_OAM_PTP_FLOW_PTP_0_FIELD(x) (MSCC_ANA_OAM_PTP_FLOW_ENA(x) + 8)
|
||||
|
||||
#define MSCC_ANA_IP1_FLOW_MATCH_UPPER(x) (MSCC_ANA_IP1_FLOW_ENA(x) + 1)
|
||||
#define MSCC_ANA_IP1_FLOW_MATCH_UPPER_MID(x) (MSCC_ANA_IP1_FLOW_ENA(x) + 2)
|
||||
#define MSCC_ANA_IP1_FLOW_MATCH_LOWER_MID(x) (MSCC_ANA_IP1_FLOW_ENA(x) + 3)
|
||||
#define MSCC_ANA_IP1_FLOW_MATCH_LOWER(x) (MSCC_ANA_IP1_FLOW_ENA(x) + 4)
|
||||
#define MSCC_ANA_IP1_FLOW_MASK_UPPER(x) (MSCC_ANA_IP1_FLOW_ENA(x) + 5)
|
||||
#define MSCC_ANA_IP1_FLOW_MASK_UPPER_MID(x) (MSCC_ANA_IP1_FLOW_ENA(x) + 6)
|
||||
#define MSCC_ANA_IP1_FLOW_MASK_LOWER_MID(x) (MSCC_ANA_IP1_FLOW_ENA(x) + 7)
|
||||
#define MSCC_ANA_IP1_FLOW_MASK_LOWER(x) (MSCC_ANA_IP1_FLOW_ENA(x) + 8)
|
||||
|
||||
#define MSCC_ANA_IP2_NXT_PROT_NXT_COMP 0x0240
|
||||
#define ANA_IP2_NXT_PROT_NXT_COMP_BYTES_HDR_MASK GENMASK(15, 8)
|
||||
#define ANA_IP2_NXT_PROT_NXT_COMP_BYTES_HDR(x) (((x) << 8) & ANA_IP2_NXT_PROT_NXT_COMP_BYTES_HDR_MASK)
|
||||
#define ANA_IP2_NXT_PROT_NXT_COMP_PTP_OAM 0x0005
|
||||
#define ANA_IP2_NXT_PROT_NXT_COMP_IP_UDP_ACH2 0x0003
|
||||
|
||||
#define MSCC_ANA_IP2_NXT_PROT_UDP_CHKSUM 0x0248
|
||||
#define IP2_NXT_PROT_UDP_CHKSUM_OFF_MASK GENMASK(15, 8)
|
||||
#define IP2_NXT_PROT_UDP_CHKSUM_OFF(x) (((x) << 8) & IP2_NXT_PROT_UDP_CHKSUM_OFF_MASK)
|
||||
#define IP2_NXT_PROT_UDP_CHKSUM_WIDTH_MASK GENMASK(5, 4)
|
||||
#define IP2_NXT_PROT_UDP_CHKSUM_WIDTH(x) (((x) << 4) & IP2_NXT_PROT_UDP_CHKSUM_WIDTH_MASK)
|
||||
|
||||
#define MSCC_ANA_IP2_FLOW_ENA(x) (0x0250 + ((x) << 4))
|
||||
#define IP2_FLOW_ENA_CHANNEL_MASK_MASK GENMASK(5, 4)
|
||||
#define IP2_FLOW_ENA_CHANNEL_MASK(x) (((x) << 4) & IP2_FLOW_ENA_CHANNEL_MASK_MASK)
|
||||
#define IP2_FLOW_VALID_CH1 IP2_FLOW_ENA_CHANNEL_MASK(2)
|
||||
#define IP2_FLOW_VALID_CH0 IP2_FLOW_ENA_CHANNEL_MASK(1)
|
||||
|
||||
#define MSCC_ANA_PTP_FLOW_ENA(x) (0x02d0 + ((x) << 4))
|
||||
#define PTP_FLOW_ENA_CHANNEL_MASK_MASK GENMASK(5, 4)
|
||||
#define PTP_FLOW_ENA_CHANNEL_MASK(x) (((x) << 4) & PTP_FLOW_ENA_CHANNEL_MASK_MASK)
|
||||
#define PTP_FLOW_VALID_CH1 PTP_FLOW_ENA_CHANNEL_MASK(2)
|
||||
#define PTP_FLOW_VALID_CH0 PTP_FLOW_ENA_CHANNEL_MASK(1)
|
||||
#define PTP_FLOW_ENA 0x0001
|
||||
|
||||
#define MSCC_ANA_PTP_FLOW_MATCH_UPPER(x) (MSCC_ANA_PTP_FLOW_ENA(x) + 1)
|
||||
#define PTP_FLOW_MSG_TYPE_MASK 0x0F000000
|
||||
#define PTP_FLOW_MSG_PDELAY_RESP 0x04000000
|
||||
#define PTP_FLOW_MSG_PDELAY_REQ 0x02000000
|
||||
#define PTP_FLOW_MSG_DELAY_REQ 0x01000000
|
||||
#define PTP_FLOW_MSG_SYNC 0x00000000
|
||||
|
||||
#define MSCC_ANA_PTP_FLOW_MATCH_LOWER(x) (MSCC_ANA_PTP_FLOW_ENA(x) + 2)
|
||||
#define MSCC_ANA_PTP_FLOW_MASK_UPPER(x) (MSCC_ANA_PTP_FLOW_ENA(x) + 3)
|
||||
#define MSCC_ANA_PTP_FLOW_MASK_LOWER(x) (MSCC_ANA_PTP_FLOW_ENA(x) + 4)
|
||||
|
||||
#define MSCC_ANA_PTP_FLOW_DOMAIN_RANGE(x) (MSCC_ANA_PTP_FLOW_ENA(x) + 5)
|
||||
#define PTP_FLOW_DOMAIN_RANGE_ENA 0x0001
|
||||
|
||||
#define MSCC_ANA_PTP_FLOW_PTP_ACTION(x) (MSCC_ANA_PTP_FLOW_ENA(x) + 6)
|
||||
#define PTP_FLOW_PTP_ACTION_MOD_FRAME_STATUS_UPDATE 0x10000000
|
||||
#define PTP_FLOW_PTP_ACTION_MOD_FRAME_STATUS_BYTE_OFFSET_MASK GENMASK(26, 24)
|
||||
#define PTP_FLOW_PTP_ACTION_MOD_FRAME_STATUS_BYTE_OFFSET(x) (((x) << 24) & PTP_FLOW_PTP_ACTION_MOD_FRAME_STATUS_BYTE_OFFSET_MASK)
|
||||
#define PTP_FLOW_PTP_ACTION_PTP_CMD_MASK GENMASK(3, 0)
|
||||
#define PTP_FLOW_PTP_ACTION_PTP_CMD(x) ((x) & PTP_FLOW_PTP_ACTION_PTP_CMD_MASK)
|
||||
#define PTP_FLOW_PTP_ACTION_SUB_DELAY_ASYM 0x00200000
|
||||
#define PTP_FLOW_PTP_ACTION_ADD_DELAY_ASYM 0x00100000
|
||||
#define PTP_FLOW_PTP_ACTION_TIME_OFFSET_MASK GENMASK(15, 10)
|
||||
#define PTP_FLOW_PTP_ACTION_TIME_OFFSET(x) (((x) << 10) & PTP_FLOW_PTP_ACTION_TIME_OFFSET_MASK)
|
||||
#define PTP_FLOW_PTP_ACTION_CORR_OFFSET_MASK GENMASK(9, 5)
|
||||
#define PTP_FLOW_PTP_ACTION_CORR_OFFSET(x) (((x) << 5) & PTP_FLOW_PTP_ACTION_CORR_OFFSET_MASK)
|
||||
#define PTP_FLOW_PTP_ACTION_SAVE_LOCAL_TIME 0x00000010
|
||||
|
||||
#define MSCC_ANA_PTP_FLOW_PTP_ACTION2(x) (MSCC_ANA_PTP_FLOW_ENA(x) + 7)
|
||||
#define PTP_FLOW_PTP_ACTION2_REWRITE_OFFSET_MASK GENMASK(15, 8)
|
||||
#define PTP_FLOW_PTP_ACTION2_REWRITE_OFFSET(x) (((x) << 8) & PTP_FLOW_PTP_ACTION2_REWRITE_OFFSET_MASK)
|
||||
#define PTP_FLOW_PTP_ACTION2_REWRITE_BYTES_MASK GENMASK(3, 0)
|
||||
#define PTP_FLOW_PTP_ACTION2_REWRITE_BYTES(x) ((x) & PTP_FLOW_PTP_ACTION2_REWRITE_BYTES_MASK)
|
||||
|
||||
#define MSCC_ANA_PTP_FLOW_PTP_0_FIELD(x) (MSCC_ANA_PTP_FLOW_ENA(x) + 8)
|
||||
#define PTP_FLOW_PTP_0_FIELD_PTP_FRAME 0x8000
|
||||
#define PTP_FLOW_PTP_0_FIELD_RSVRD_CHECK 0x4000
|
||||
#define PTP_FLOW_PTP_0_FIELD_OFFSET_MASK GENMASK(13, 8)
|
||||
#define PTP_FLOW_PTP_0_FIELD_OFFSET(x) (((x) << 8) & PTP_FLOW_PTP_0_FIELD_OFFSET_MASK)
|
||||
#define PTP_FLOW_PTP_0_FIELD_BYTES_MASK GENMASK(3, 0)
|
||||
#define PTP_FLOW_PTP_0_FIELD_BYTES(x) ((x) & PTP_FLOW_PTP_0_FIELD_BYTES_MASK)
|
||||
|
||||
#define MSCC_ANA_PTP_IP_CHKSUM_SEL 0x0330
|
||||
#define ANA_PTP_IP_CHKSUM_SEL_IP_COMP_2 0x0001
|
||||
#define ANA_PTP_IP_CHKSUM_SEL_IP_COMP_1 0x0000
|
||||
|
||||
#define MSCC_PHY_ANA_FSB_CFG 0x331
|
||||
#define ANA_FSB_ADDR_FROM_BLOCK_SEL_MASK GENMASK(1, 0)
|
||||
#define ANA_FSB_ADDR_FROM_IP2 0x0003
|
||||
#define ANA_FSB_ADDR_FROM_IP1 0x0002
|
||||
#define ANA_FSB_ADDR_FROM_ETH2 0x0001
|
||||
#define ANA_FSB_ADDR_FROM_ETH1 0x0000
|
||||
|
||||
#define MSCC_PHY_ANA_FSB_REG(x) (0x332 + (x))
|
||||
|
||||
#define COMP_MAX_FLOWS 8
|
||||
#define PTP_COMP_MAX_FLOWS 6
|
||||
|
||||
#define PPS_WIDTH_ADJ 0x1dcd6500
|
||||
#define STALL_EGR_LATENCY(x) (1536000 / (x))
|
||||
|
||||
/* PHC clock available frequencies. */
|
||||
enum {
|
||||
PHC_CLK_125MHZ,
|
||||
PHC_CLK_156_25MHZ,
|
||||
PHC_CLK_200MHZ,
|
||||
PHC_CLK_250MHZ,
|
||||
PHC_CLK_500MHZ,
|
||||
};
|
||||
|
||||
enum ptp_cmd {
|
||||
PTP_NOP = 0,
|
||||
PTP_WRITE_1588 = 5,
|
||||
PTP_WRITE_NS = 7,
|
||||
PTP_SAVE_IN_TS_FIFO = 11, /* invalid when writing in reg */
|
||||
};
|
||||
|
||||
enum vsc85xx_ptp_msg_type {
|
||||
PTP_MSG_TYPE_SYNC,
|
||||
PTP_MSG_TYPE_DELAY_REQ,
|
||||
};
|
||||
|
||||
struct vsc85xx_ptphdr {
|
||||
u8 tsmt; /* transportSpecific | messageType */
|
||||
u8 ver; /* reserved0 | versionPTP */
|
||||
__be16 msglen;
|
||||
u8 domain;
|
||||
u8 rsrvd1;
|
||||
__be16 flags;
|
||||
__be64 correction;
|
||||
__be32 rsrvd2;
|
||||
__be64 clk_identity;
|
||||
__be16 src_port_id;
|
||||
__be16 seq_id;
|
||||
u8 ctrl;
|
||||
u8 log_interval;
|
||||
} __attribute__((__packed__));
|
||||
|
||||
/* Represents an entry in the timestamping FIFO */
|
||||
struct vsc85xx_ts_fifo {
|
||||
u32 ns;
|
||||
u64 secs:48;
|
||||
u8 sig[16];
|
||||
} __attribute__((__packed__));
|
||||
|
||||
struct vsc85xx_ptp {
|
||||
struct phy_device *phydev;
|
||||
struct ptp_clock *ptp_clock;
|
||||
struct ptp_clock_info caps;
|
||||
struct sk_buff_head tx_queue;
|
||||
enum hwtstamp_tx_types tx_type;
|
||||
enum hwtstamp_rx_filters rx_filter;
|
||||
u8 configured:1;
|
||||
};
|
||||
|
||||
#endif /* _MSCC_PHY_PTP_H_ */
|
||||
|
|
@ -244,7 +244,8 @@ struct phy_package_shared {
|
|||
};
|
||||
|
||||
/* used as bit number in atomic bitops */
|
||||
#define PHY_SHARED_F_INIT_DONE 0
|
||||
#define PHY_SHARED_F_INIT_DONE 0
|
||||
#define PHY_SHARED_F_PROBE_DONE 1
|
||||
|
||||
/*
|
||||
* The Bus class for PHYs. Devices which provide access to
|
||||
|
|
@ -1566,14 +1567,25 @@ static inline int __phy_package_write(struct phy_device *phydev,
|
|||
return __mdiobus_write(phydev->mdio.bus, shared->addr, regnum, val);
|
||||
}
|
||||
|
||||
static inline bool phy_package_init_once(struct phy_device *phydev)
|
||||
static inline bool __phy_package_set_once(struct phy_device *phydev,
|
||||
unsigned int b)
|
||||
{
|
||||
struct phy_package_shared *shared = phydev->shared;
|
||||
|
||||
if (!shared)
|
||||
return false;
|
||||
|
||||
return !test_and_set_bit(PHY_SHARED_F_INIT_DONE, &shared->flags);
|
||||
return !test_and_set_bit(b, &shared->flags);
|
||||
}
|
||||
|
||||
static inline bool phy_package_init_once(struct phy_device *phydev)
|
||||
{
|
||||
return __phy_package_set_once(phydev, PHY_SHARED_F_INIT_DONE);
|
||||
}
|
||||
|
||||
static inline bool phy_package_probe_once(struct phy_device *phydev)
|
||||
{
|
||||
return __phy_package_set_once(phydev, PHY_SHARED_F_PROBE_DONE);
|
||||
}
|
||||
|
||||
extern struct bus_type mdio_bus_type;
|
||||
|
|
|
|||
Loading…
Reference in New Issue